阅读说明：本技术 具迟滞功能的比较电路与比较模块 (Comparison circuit with hysteresis function and comparison module ) 是由 费晓冬 王伟 黄三岳 于 2020-04-26 设计创作，主要内容包括：本发明是为一种具迟滞功能的比较电路与比较模块。比较模块包含彼此电连接的第一电阻、第二电阻,以及前述的比较电路。比较电压根据输入电压、第一电阻的电阻值,与第二电阻的电阻值而决定。比较电路包含输入电路、外接电路以及耦合模块。耦合模块包含：第一耦合晶体管、第二耦合晶体管、第三耦合晶体管与第四耦合晶体管。第一耦合晶体管的控制端与第二耦合晶体管的控制端均选择性电连接于第一节点与第二节点中的一者。第三耦合晶体管与第四耦合晶体管的第二端均选择性电连接于第一节点与第二节点中的一者。(The invention relates to a comparison circuit with a hysteresis function and a comparison module. The comparison module comprises a first resistor, a second resistor and the comparison circuit, wherein the first resistor and the second resistor are electrically connected with each other. The comparison voltage is determined according to the input voltage, the resistance value of the first resistor and the resistance value of the second resistor. The comparison circuit comprises an input circuit, an external circuit and a coupling module. The coupling module includes: the first coupling transistor, the second coupling transistor, the third coupling transistor and the fourth coupling transistor. The control end of the first coupling transistor and the control end of the second coupling transistor are both selectively and electrically connected to one of the first node and the second node. The second ends of the third coupling transistor and the fourth coupling transistor are selectively electrically connected to one of the first node and the second node.)

1. A comparator circuit with hysteresis function comprises:

an input circuit, comprising:

a first input transistor receiving a reference voltage; and

a second input transistor receiving a comparison voltage;

an external circuit, comprising:

a first external transistor electrically connected to the first input transistor through a first node; and

a second external transistor electrically connected to the second input transistor through a second node; and the number of the first and second groups,

a coupling module, comprising:

a first current amplification circuit, comprising:

a first coupling transistor having a first terminal, a second terminal, and a control terminal, wherein the second terminal of the first coupling transistor is electrically connected to the first node, and the control terminal of the first coupling transistor is selectively electrically connected to one of the first node and the second node; and

a second coupling transistor having a first terminal, a second terminal, and a control terminal, wherein the second terminal of the second coupling transistor is electrically connected to the second node, and the control terminal of the second coupling transistor is selectively electrically connected to one of the first node and the second node; and

a second current amplification circuit, comprising:

a third coupling transistor having a first terminal, a second terminal and a control terminal, wherein the second terminal of the third coupling transistor is selectively electrically connected to one of the first node and the second node, and the control terminal of the third coupling transistor is electrically connected to the second node; and

a fourth coupling transistor having a first terminal, a second terminal and a control terminal, wherein the second terminal of the fourth coupling transistor is selectively electrically connected to one of the first node and the second node, and the control terminal of the fourth coupling transistor is electrically connected to the first node.

2. The comparison circuit of claim 1, wherein when the comparison circuit is in a first mode,

the control terminal of the first coupling transistor is electrically connected to the first node;

the control terminal of the second coupling transistor is electrically connected to the second node;

the second end of the third coupling transistor is electrically connected to the first node; and the number of the first and second groups,

the second terminal of the fourth coupling transistor is electrically connected to the second node.

3. The comparison circuit of claim 2, wherein the coupling module further comprises:

a first switch electrically connected between the second terminal of the third coupling transistor and the first node;

a second switch electrically connected between the second end of the fourth coupling transistor and the second node;

a third switch electrically connected between the control terminal of the first coupling transistor and the first node; and

a fourth switch electrically connected between the control terminal of the second coupling transistor and the second node,

wherein the first switch, the second switch, the third switch, and the fourth switch are turned on in the first mode.

4. The comparison circuit of claim 1, wherein when the comparison circuit is in a second mode,

the control terminal of the first coupling transistor is electrically connected to the second node;

the control terminal of the second coupling transistor is electrically connected to the first node;

the second end of the third coupling transistor is electrically connected to the second node; and the number of the first and second groups,

the second terminal of the fourth coupling transistor is electrically connected to the first node.

5. The comparison circuit of claim 4, wherein the coupling module further comprises:

a fifth switch electrically connected between the second terminal of the third coupling transistor and the second node;

a sixth switch electrically connected to the second terminal of the fourth coupling transistor and the first node;

a seventh switch electrically connected between the control terminal of the first coupling transistor and the second node; and the number of the first and second groups,

an eighth switch electrically connected between the control terminal of the second coupling transistor and the first node,

wherein the fifth switch, the sixth switch, the seventh switch, and the eighth switch are turned on in the second mode.

6. The comparison circuit of claim 1, wherein the first terminals of the coupling transistors are electrically connected to a supply voltage.

7. The comparison circuit of claim 1, further comprising:

a current mirror circuit, comprising:

a reference source transistor electrically connected to the first external transistor; and

and the mirror image transistor is electrically connected with the second external transistor.

8. The comparison circuit of claim 7 wherein the mirror transistor generates an output signal, wherein the output signal is at a first level in a first mode and at a second level in a second mode.

9. The comparison circuit of claim 1, further comprising:

a current source, electrically connected to the first input transistor and the second input transistor, for providing a sum current.

10. The comparison circuit of claim 9, wherein a sum of a first current flowing through the first input transistor and a second current flowing through the second input transistor is equal to the sum current when the first input transistor and the second input transistor are both on.

11. The comparison circuit of claim 9, wherein a first current flowing through the first input transistor is equal to the sum current when the first input transistor is on and the second input transistor is off.

12. The comparison circuit of claim 1, wherein the coupling module further comprises:

a switch circuit electrically connected to the first node, the second node and the coupling transistor for receiving a first control signal and a second control signal,

the switch circuit selectively turns on the first node and the control terminal of the first coupling transistor, the control terminal of the second coupling transistor, the second terminal of the third coupling transistor and the second terminal of the fourth coupling transistor according to the control signal, and

the switch circuit selectively turns on the second node and the control terminal of the first coupling transistor, the control terminal of the second coupling transistor, the second terminal of the third coupling transistor, and the second terminal of the fourth coupling transistor according to the control signal.

13. The comparison circuit of claim 12 wherein the first control signal is in the same direction as an output signal and the second control signal is in the opposite direction of the output signal.

14. The comparison circuit of claim 1 wherein a current amplification of the first coupling transistor is equal to a current amplification of the second coupling transistor.

15. The comparison circuit of claim 1 wherein the current amplification of the third coupling transistor is equal to the current amplification of the fourth coupling transistor.

16. The comparison circuit of claim 1 wherein the current amplification of the third coupling transistor is greater than the current amplification of the first coupling transistor.

17. The comparison circuit of claim 1, wherein the first and second input transistors are NMOS transistors and the first external transistor, the second external transistor, and the coupling transistor are PMOS transistors.

18. A comparison module with hysteresis function, comprising:

a first resistor for receiving an input voltage;

a second resistor, electrically connected to the first resistor, for receiving a ground voltage, wherein a comparison voltage is determined according to the input voltage, a resistance of the first resistor, and a resistance of the second resistor; and the number of the first and second groups,

a comparison circuit, comprising:

an input circuit, comprising:

a first input transistor receiving a reference voltage; and

a second input transistor for receiving the comparison voltage;

an external circuit, comprising:

a first external transistor electrically connected to the first input transistor through a first node; and

a second external transistor (MP2) electrically connected to the second input transistor through a second node; and the number of the first and second groups,

a coupling module (18) comprising:

a first current amplification circuit, comprising:

a first coupling transistor having a first terminal, a second terminal, and a control terminal, wherein the second terminal of the first coupling transistor is electrically connected to the first node, and the control terminal of the first coupling transistor is selectively electrically connected to one of the first node and the second node; and

a second coupling transistor having a first terminal, a second terminal, and a control terminal, wherein the second terminal of the second coupling transistor is electrically connected to the second node, and the control terminal of the second coupling transistor is selectively electrically connected to one of the first node and the second node; and

a second current amplification circuit, comprising:

a third coupling transistor having a first terminal, a second terminal and a control terminal, wherein the second terminal of the third coupling transistor is selectively electrically connected to one of the first node and the second node, and the control terminal of the third coupling transistor is electrically connected to the second node; and

a fourth coupling transistor having a first terminal, a second terminal and a control terminal, wherein the second terminal of the fourth coupling transistor is selectively electrically connected to one of the first node and the second node, and the control terminal of the fourth coupling transistor is electrically connected to the first node.

19. The comparison module of claim 18 wherein the coupling module further comprises:

a first inverter, electrically connected to the comparison circuit, for receiving an output signal and generating a first control signal in an inverse direction of the output signal; and the number of the first and second groups,

and the second inverter is electrically connected with the first inverter and the comparison circuit and is used for receiving the first control signal and generating a second control signal in the same direction as the output signal.

20. The comparison module of claim 18, further comprising:

a first switch electrically connected between the second terminal of the third coupling transistor and the first node;

a second switch electrically connected between the second end of the fourth coupling transistor and the second node;

a third switch electrically connected between the control terminal of the first coupling transistor and the first node;

a fourth switch electrically connected between the control terminal of the second coupling transistor and the second node;

a fifth switch electrically connected between the second terminal of the third coupling transistor and the second node;

a sixth switch electrically connected between the second terminal of the fourth coupling transistor and the first node;

a seventh switch electrically connected between the control terminal of the first coupling transistor and the second node; and the number of the first and second groups,

an eighth switch electrically connected between the control terminal of the second coupling transistor and the first node,

the first switch, the second switch, the third switch, and the fourth switch are turned on in a first mode and turned off in a second mode, and the fifth switch, the sixth switch, the seventh switch, and the eighth switch are turned off in the first mode and turned on in the second mode.

Technical Field

The present invention relates to a comparator circuit and a comparator module with hysteresis function, and more particularly, to a comparator circuit and a comparator module with hysteresis function that meet the requirements of both hysteresis mode and high gain mode.

Background

The comparison circuit has a wide range of applications, for example, the comparison circuit can be used in analog to digital converters (analog to digital converters), clock-recovery circuits (clock-recovery circuits), window detectors (window detectors), and Schmitt triggers (Schmitt triggers). The comparison circuit receives the input voltage Vin and the reference voltage Vref and generates an output signal Vo, wherein the voltage of the output signal Vo represents the magnitude relationship between the input voltage Vin and the reference voltage Vref. For example, if the input voltage Vin is greater than the reference voltage Vref, the output signal Vo is at a high level; and if the input voltage Vin is less than the reference voltage Vref, the output signal Vo is at a low level.

The basic comparison circuit is easy to generate jitter in the output signal Vo due to the disturbance of the input voltage Vin. For this reason, a comparator circuit having a hysteresis function is further developed. The comparison circuit with the hysteresis function has the characteristics of strong anti-interference capability and low sensitivity. Therefore, when the input voltage Vin varies slightly, the output signal Vo does not vary immediately, so the comparator circuit with hysteresis function has better anti-interference capability. However, in the comparator circuit with hysteresis function of the prior art, the magnitude of the hysteresis voltage Vhys is affected by the reference voltage Vref. Once the reference voltage Vref decreases, its hysteresis voltage Vhys also decreases. In conjunction, the accuracy of the comparison circuit is affected.

Disclosure of Invention

The invention relates to a comparison circuit and a comparison module, which can be operated in a hysteresis mode and a high gain mode. In the hysteresis mode, the comparison circuit and the comparison module can provide hysteresis voltage which is not influenced by the variation of the reference voltage. By selecting the transistor size, the gain of the comparison circuit and the comparison module in a high gain mode can be further improved.

According to a first aspect of the present invention, a comparator circuit with hysteresis function is provided. The comparison circuit includes: input circuit, external circuit and coupling module. The input circuit includes: a first input transistor and a second input transistor. The first input transistor receives a reference voltage and the second input transistor receives a comparison voltage. The external circuit includes: a first external transistor and a second external transistor. The first external transistor is electrically connected to the first input transistor through a first node, and the second external transistor is electrically connected to the second input transistor through a second node. The coupling module includes: a first current amplification circuit and a second current amplification circuit. A first current amplification circuit comprising: the first coupling transistor and the second coupling transistor. The first coupling transistor has a first terminal, a second terminal and a control terminal. The second end of the first coupling transistor is electrically connected to the first node, and the control end of the first coupling transistor is selectively electrically connected to one of the first node and the second node. The second coupling transistor has a first terminal, a second terminal and a control terminal. The second end of the second coupling transistor is electrically connected to the second node, and the control end of the second coupling transistor is selectively electrically connected to one of the first node and the second node. The second current amplification circuit includes: the third coupling transistor and the fourth coupling transistor. The third coupling transistor has a first terminal, a second terminal and a control terminal. The second end of the third coupling transistor is selectively electrically connected to one of the first node and the second node, and the control end of the third coupling transistor is electrically connected to the second node. The fourth coupling transistor has a first terminal, a second terminal and a control terminal. The second end of the fourth coupling transistor is selectively electrically connected to one of the first node and the second node, and the control end of the fourth coupling transistor is electrically connected to the first node.

According to a second aspect of the present invention, a comparing module with hysteresis function is provided, which includes a first resistor, a second resistor and a comparing circuit electrically connected to each other. The first resistor receives an input voltage. The second resistor receives a ground voltage. The comparison voltage is determined according to the input voltage, the resistance value of the first resistor and the resistance value of the second resistor. The comparison circuit includes: input circuit, external circuit and coupling module. The input circuit includes: a first input transistor and a second input transistor. The first input transistor receives a reference voltage and the second input transistor receives a comparison voltage. The external circuit includes: a first external transistor and a second external transistor. The first external transistor is electrically connected to the first input transistor through a first node, and the second external transistor is electrically connected to the second input transistor through a second node. The coupling module includes: a first current amplification circuit and a second current amplification circuit. The first current amplification circuit includes: the first coupling transistor and the second coupling transistor. The first coupling transistor has a first terminal, a second terminal and a control terminal. The second end of the first coupling transistor is electrically connected to the first node, and the control end of the first coupling transistor is selectively electrically connected to one of the first node and the second node. The second coupling transistor has a first terminal, a second terminal and a control terminal. The second end of the second coupling transistor is electrically connected to the second node, and the control end of the second coupling transistor is selectively electrically connected to one of the first node and the second node. The high current amplification circuit includes: the third coupling transistor and the fourth coupling transistor. The third coupling transistor has a first terminal, a second terminal and a control terminal. The second end of the third coupling transistor is selectively electrically connected to one of the first node and the second node, and the control end of the third coupling transistor is electrically connected to the second node. The fourth coupling transistor has a first terminal, a second terminal and a control terminal. The second end of the fourth coupling transistor is selectively electrically connected to one of the first node and the second node, and the control end of the fourth coupling transistor is electrically connected to the first node.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments is made with reference to the accompanying drawings, in which:

drawings

Fig. 1, which is a schematic diagram of a comparison module contemplated in accordance with the present invention.

Fig. 2A is a schematic diagram of the comparison circuit of fig. 1 generating an output signal Vo according to the comparison voltage Vcmp.

Fig. 2B is a schematic diagram of the comparison module of fig. 1 generating the output signal Vo according to the difference of the input voltage Vin.

Fig. 3 is a block diagram of an embodiment of a comparison circuit contemplated in accordance with the present invention.

Fig. 4 is a schematic diagram of an internal circuit of a comparison circuit according to an embodiment of the present invention.

Fig. 5A is a schematic diagram illustrating the relationship between the comparison voltage Vcmp and the output signal Vo when the comparison circuit is in the hysteresis Mode (Mode 1).

Fig. 5B is a diagram illustrating the relationship between the comparison voltage Vcmp and the output signal Vo when the comparison circuit is in the high gain Mode (Mode 2).

FIG. 6A is a schematic diagram of switches S1-S4 implemented as pass gates.

Fig. 6B shows the connection relationship of the internal circuit of the coupling module in the hysteresis Mode (Mode 1).

Fig. 7A and 7B are schematic diagrams of the current flow direction of the comparator circuit in the hysteresis Mode (Mode 1).

FIG. 8A is a schematic diagram of switches S5-S8 implemented as pass gates.

Fig. 8B shows the connection relationship of the internal circuit of the coupling module in the high gain Mode (Mode 2).

Fig. 9 is a schematic diagram showing the flow of current when the comparator circuit is in the high gain Mode (Mode 2).

Fig. 10 is a schematic diagram of transistors included in the coupling module.

FIG. 11 is a schematic diagram illustrating how transistors in the coupling module are dynamically connected according to the mode of the comparator.

Detailed Description

Please refer to fig. 1, which is a schematic diagram of a comparison module according to the present invention. The comparison module 10 includes resistors R1 and R2, and a comparison circuit 13. Wherein it is assumed that the comparison circuit 13 has a hysteresis voltage Vhys.

Resistor R1 has one end electrically connected to input voltage Vin and the other end electrically connected to comparison node Ncmp. The resistor R2 has one end electrically connected to the comparison node Ncmp and the other end electrically connected to the ground voltage Gnd. For convenience of explanation, the voltage at the comparison node Ncmp is defined as the comparison voltage Vcmp, and R1 and R2 directly represent the resistance values of the resistors R1 and R2, respectively.

The inverting input terminal (inverting terminal) of the comparing circuit 13 receives the reference voltage Vref, and the non-inverting input terminal (non-inverting terminal) receives the comparison voltage Vcmp, and then generates the output signal Vo. In addition, the comparison circuit 10 may further include inverters 11a and 11 b. The input terminal of the inverter 11a is electrically connected to the output terminal of the comparison circuit 13. The input terminal of the inverter 11b is electrically connected to the output terminal of the inverter 11a, and the output terminals of the inverters 11a and 11b are electrically connected to the comparator circuit 13. The output terminals of the inverters 11a, 11b output control signals Sct, Sctn fed back to the comparison circuit 13. The phase of the control signal Sctn is the same as the phase of the output signal Vo, and the phase of the control signal Sct is opposite to the phase of the output signal Vo.

The comparison circuit 13 receives a reference voltage Vref and a comparison voltage Vcmp. The magnitude of the reference voltage Vref may vary according to different applications. For the same application, the magnitude of the reference voltage Vref is a preset value. On the other hand, the magnitude of the comparison voltage Vcmp varies with the input voltage Vin. Since in fig. 1, the resistors R1, R2 are connected in series with each other, and the resistor R1 receives the input voltage Vin. The comparison voltage Vcmp can be calculated by matching a voltage division formula with the input voltage Vin and the resistance values R1 and R2. That is, the comparison voltage Vcmp is [ R2/(R1+ R2) ] Vin.

Please refer to fig. 2A, which is a schematic diagram of the comparison circuit of fig. 1 generating the output signal Vo according to the comparison voltage Vcmp. In this figure, the vertical axis represents the output signal Vo, and the horizontal axis represents the comparison voltage Vcmp.

When the comparison voltage Vcmp received by the comparison circuit 13 is equal to the reference voltage Vref, the level of the output signal Vo generated by the comparison circuit 13 will change. For example, from low to high, or from high to low. The voltage value of the comparison voltage Vcmp at this time is referred to as an inversion point. In fig. 2, two inversion points are plotted, which represent the upward inversion voltage Vinvu and the downward inversion voltage Vinvd, respectively.

First, a change pattern of the output signal Vo when the comparison voltage Vcmp is continuously increased from 0V will be described. The output signal Vo is low when the comparison voltage Vcmp is initially equal to 0V. When the comparison voltage Vcmp continues to increase but is still less than the up-inversion voltage Vinvu, the output signal Vo is maintained at a low level. When the comparison voltage Vcmp continues to increase to be equal to the upward inversion voltage Vinvu, the output signal Vo will instantaneously transition from the low level to the high level. If the comparison voltage Vcmp continues to increase and is still greater than the up-inversion voltage Vinvu, the output signal Vo is maintained at a high level.

Next, a description will be given of a manner of change of the output signal Vo when the comparison voltage Vcmp is gradually decreased from the up-inversion voltage Vinvu. Assume that the comparison voltage Vcmp is initially equal to the up-inversion voltage Vinvu, when the output signal Vo is high. When the comparison voltage Vcmp continues to drop close to but slightly greater than the down-reversed voltage Vinvd, the output signal Vo is maintained at a high level. When the comparison voltage Vcmp continuously decreases to the down-reversed voltage Vinvd, the output signal Vo will instantaneously transition from a high level to a low level. Thereafter, the output signal Vo is maintained at a low level while the comparison voltage Vcmp continues to decrease. The difference between the up-inversion voltage Vinvu and the down-inversion voltage Vinvd is defined as the hysteresis voltage Vhys.

As can be seen from the foregoing description, when the output signal Vo varies, the reference voltage Vref received by the input terminal of the comparing circuit 13 is equal to the comparison voltage Vcmp, [ R2/(R1+ R2) ]. That is, in this case, the formula (1) can be obtained.

The equation (1) is used to solve the problem of Vref, Vcmp, R2/(R1+ R2) and vin

Further, by converting equation (1), it can be seen that equation (2) holds when the comparison voltage Vcmp is at the inversion point.

The

From equation (2), the input voltage Vin ═ Vref [ (R1+ R2)/R2] when the output signal Vo is inverted can be obtained. Accordingly, the turning point (Vref [ (R1+ R2)/R2]) of the input voltage Vin of the comparison module 10 shown in fig. 1 depends on the reference voltage Vref and the resistance values of the resistors R1 and R2.

Please refer to fig. 2B, which is a schematic diagram of the comparison module of fig. 1 generating the output signal Vo according to the difference of the input voltage Vin. Since the comparison voltage Vcmp can be expressed as Vcmp ═ Vin [ R2/(R1+ R2) ] according to the input voltage Vin and the resistance values of the resistors R1, R2. After conversion, the input voltage Vin can be expressed as a result of multiplying the voltage dividing coefficient (R1+ R2)/R2 by the input voltage Vcmp, i.e., Vin ═ R1+ R2)/R2 Vcmp. Therefore, the respective values (the hysteresis voltage Vhys _ in, the upward inversion voltage Vinvu _ in, and the downward inversion voltage Vinvd _ in) shown in fig. 2B can be obtained by multiplying the respective values (the hysteresis voltage Vhys, the upward inversion voltage Vinvu, and the downward inversion voltage Vinvd) of the comparison circuit 13 shown in fig. 2A by the voltage division coefficient (R1+ R2)/R2.

The operation of the comparator circuit 13 can be divided into two modes, one is a hysteresis mode (hysteresis mode) and one is a high gain mode (high gain mode). For ease of illustration, the hysteresis Mode is defined herein as Mode1, and the high gain Mode is defined herein as Mode 2. In the hysteresis Mode (Mode1), the comparator circuit 13 needs to provide good noise immunity against voltage variations of the input voltage Vcmp; in the high gain Mode (Mode2), the comparator circuit 13 needs to provide a high gain so that the output signal Vo can quickly reflect the voltage difference between the input voltage Vcmp and the reference voltage Vref.

Please refer to fig. 3, which is a block diagram of an embodiment of a comparison circuit contemplated by the present invention. The comparison circuit 13 includes: an input circuit 151, a current source 153, a coupling module 18, an external circuit 173, and a current mirror circuit 171. In addition, the comparison circuit 13 may be further divided into a first stage amplifier 15 and a second stage amplifier 17. The first stage amplifier 15 provides a first stage gain of A_VN1The second stage amplifier 17 provides a second stage gain A_VN2。

First stage amplifier 15 includes input circuit 151, current source 153, and a portion of coupling block 18. The input circuit 151 further includes input transistors 151a and 151 b. The first-stage amplifier 15 receives a reference voltage Vref via an input transistor 151a, and a comparison voltage Vcmp through an input transistor 151 b. Current source 153 provides a sum current that flows through input circuit 151. The first stage amplifier 15 generates a first stage amplified signal at nodes N1, N2.

The second stage amplifier 17 includes an external circuit 173, a current mirror circuit 171, and a part of the coupling module 18. The external circuit 173 further includes external transistors 173a and 173 b. The external transistor 173a is electrically connected to the node N1, and the external transistor 173b is electrically connected to the node N2. The current mirror circuit 171 further includes a reference source transistor 171a and a mirror transistor 171 b. Wherein, the reference source crystalThe transistor 171a is electrically connected to the external transistor 173a, and the mirror transistor 171b is electrically connected to the external transistor 173 b. The second stage amplifier 17 receives the first stage amplified signal from the nodes N1, N2 and provides a second stage gain A_VN2And generates a second stage amplified signal (equivalent to the output signal Vo).

Please refer to fig. 4, which is a schematic diagram of an internal circuit of a comparison circuit according to an embodiment of the invention. Please refer to fig. 3 and fig. 4.

The input circuit 151 includes transistors MN1 (input transistor 151a), MN2 (input transistor 151 b). The gate of the transistor MN1 receives the reference voltage Vref, and the gate of the transistor MN2 receives the comparison voltage Vcmp. The drains of the transistors MN1 and MN2 are electrically connected to the coupling module 18 through the nodes N1 and N2, respectively, and the sources of the transistors MN1 and MN2 are electrically connected to the current source 153.

The current source 153 includes a transistor MN5 having a source electrically connected to the ground voltage Gnd and a drain electrically connected to the sources of the transistors MN1 and MN 2; and its gate continuously receives the bias voltage VPB. The transistor MN5 continues to generate the sum current I due to the bias voltage VPB continuing to turn on the transistor MN5_mn5。

In the current mirror circuit 171, the transistor MN3 serves as a reference source transistor 171a for providing a reference current (Imn3), and the transistor MN4 serves as a mirror transistor 171b for generating a mirror current (Imn4) corresponding to the reference current (Imn 3). The drain of the transistor MN3 is connected to the gate and commonly connected to the gate of the transistor MN 4. The sources of the transistors MN3 and MN4 are electrically connected to the ground voltage Gnd. The drain of the transistor MN3 is electrically connected to the external transistor 173a, and the drain of the transistor MN4 is electrically connected to the external transistor 173 b.

The transistors MP1 and MP2 are used as external transistors 173a and 173b, respectively. The sources of the transistors MP1 and MP2 are electrically connected to the supply voltage Vdd. The drain of the transistor MP1 is electrically connected to the drain of the transistor MP 3; the gate is electrically connected to node N1. The drain of the transistor MP2 is electrically connected to the drain of the transistor MP 4; the gate is electrically connected to node N2. In this drawing, the transistors MP1 to MP6 are assumed to be PMOS transistors, and the transistors MN1 to MN5 are assumed to be NMOS transistors. In practical applications, the kind of the transistor is not limited to this embodiment.

As shown in FIG. 4, the coupling module 18 includes transistors MP 3-MP 6 and switches S1-S8. In this context, the sources of the transistors MP 3-MP 6 are all electrically connected to the supply voltage Vdd. In addition, the coupling of the gates and the drains of the transistors MP 3-MP 6 may be changed, and they are referred to as coupling transistors. Please refer to table 1, which is a list of connection modes of the switches S1-S8.

TABLE 1

Switch with a switch body	Node connected with switch	Transistor connected with switch
			S1	N1	Drain of transistor MP5
S2	N2	Drain of transistor MP6
			S3	N1	Gate of transistor MP3
S4	N2	Gate of transistor MP4
			S5	N2	CrystalDrain of tube MP5
S6	N1	Drain of transistor MP6
			S7	N2	Gate of transistor MP3
S8	N1	Gate of transistor MP4

Next, the connection relationships between the transistors MP3 to MP6 and the nodes N1 and N2 with the switching of the switches S1 to S8 will be described in the order of the transistors MP3 to MP 6. Please refer to fig. 4 and table 1.

The gate of the transistor MP3 is electrically connected to the switches S3 and S7. If the switch S3 is turned on, the gate of the transistor MP3 is electrically connected to the node N1; if the switch S7 is turned on, the gate of the transistor MP3 is electrically connected to the node N2. Since the switches S3 and S7 are turned on alternately, the gate of the transistor MP3 is not connected to the nodes N1 and N2 at the same time. In addition, the drain of the transistor MP3 is electrically connected to the node N1.

The gate of the transistor MP4 is electrically connected to the switches S8 and S4. If the switch S8 is turned on, the gate of the transistor MP4 is electrically connected to the node N1; if the switch S4 is turned on, the gate of the transistor MP4 is electrically connected to the node N2. Since the switches S8 and S4 are turned on alternately, the gate of the transistor MP4 is not connected to the nodes N1 and N2 at the same time. In addition, the drain of the transistor MP4 is electrically connected to the node N2.

The gate of the transistor MP5 is electrically connected to the node N1. The drain of the transistor MP5 is electrically connected to the switches S1 and S5. If the switch S1 is turned on, the drain of the transistor MP5 is electrically connected to the node N1; if the switch S5 is turned on, the drain of the transistor MP5 is electrically connected to the node N2. Since the switches S1 and S5 are turned on alternately, the drain of the transistor MP5 is not connected to the nodes N1 and N2 at the same time.

The gate of the transistor MP6 is electrically connected to the node N1. The drain of the transistor MP6 is electrically connected to the switches S6 and S2. If the switch S6 is turned on, the drain of the transistor MP6 is electrically connected to the node N1; if the switch S2 is turned on, the drain of the transistor MP6 is electrically connected to the node N2. Since the switches S6 and S2 are turned on alternately, the gate of the transistor MP6 is not connected to the nodes N1 and N2 at the same time.

According to the foregoing description, the connection modes of the transistors MP 3-MP 6 can be divided into two types: the first type is that the electrical connection of the gate is fixed, but the drain changes the connected node according to the mode (i.e., transistors MP5, MP 6); the second type is a node (i.e., transistors MP3, MP4) to which the drain is electrically connected but the gate is connected according to a pattern. Herein, the transistors MP5, MP6 may be defined as high current amplification transistors, and the transistors MP3, MP4 may be defined as low current amplification transistors, according to the difference in current amplification. A combination of the transistors MP5 and MP6 is defined as a high-current amplification circuit, and a combination of the transistors MP3 and MP4 is defined as a low-current amplification circuit.

According to the contemplated embodiment of the present invention, the switches S1-S8 can be divided into two parts, one part (including the switches S1-S4) being controlled by the control signal Sct, and the other part (including the switches S5-S8) being controlled by the control signal Sctn. Table 2 is a list of the modes in which the switches S1 to S8 are turned on and the control signals corresponding thereto.

TABLE 2

As shown in fig. 1, the output signal Vo generates the control signal Sct after passing through the inverter 11a, and the control signal Sct generates the control signal Sctn after passing through the inverter 11 b. Therefore, the control signal Sct is opposite to the output signal Vo, and the control signal Sctn is in the same direction as the output signal Vo.

Since the output signal Vo is at a low level in the hysteresis Mode (Mode1), the control signals Sct and Sctn are at high and low levels, respectively, in the hysteresis Mode (Mode 1). In addition, the switches S1 to S4 controlled by the control signal Sct are turned on in the hysteresis Mode (Mode1), and the switches S5 to S8 controlled by the control signal Sctn are turned off in the hysteresis Mode (Mode 1). Therefore, the switch S1 will turn on the node N1 and the drain of the transistor MP 5; the switch S2 will turn on the node N2 and the drain of the transistor MP 6; the switch S3 will turn on the node N1 and the gate of the transistor MP 3; and, the switch S4 will turn on the node N2 and the gate of the transistor MP 4.

On the other hand, since the output signal Vo is at a high level in the high gain Mode (Mode2), the control signals Sct and Sctn are at a low level and a high level in the high gain Mode (Mode2), respectively. In parallel, switches S1 to S4 controlled by control signal Sct are turned off in the high gain Mode (Mode2), and switches S5 to S8 controlled by control signal Sctn are turned on in the high gain Mode (Mode 2). Therefore, the switch S5 will turn on the node N2 and the drain of the transistor MP 5; the switch S6 will turn on the node N1 and the drain of the transistor MP 6; the switch S7 will turn on N2 and the gate of the transistor MP 3; and, the switch S8 will turn on the node N1 and the gate of the transistor MP 4.

For convenience of explanation, the symbols associated with each of the transistors MN 1-MN 5, MP 1-MP are referred to herein by subscripts and lower case letters. For example, the current flowing through the transistor MP1 is denoted as I_mp1The current amplification of the transistor MP6 is denoted as β_mp6(ii) a The channel width of the transistor MP3 is denoted as W_mp3(ii) a And, the channel length of the transistor MP3 is denoted as L_mp3And the like. Other representations of the characteristics associated with each transistor can be analogized and are not described in detail herein.

Fig. 5A is a schematic diagram illustrating the relationship between the comparison voltage Vcmp and the output signal Vo when the comparison circuit is in the hysteresis Mode (Mode 1). Fig. 5A represents, as a line L1, the circuit behavior of the comparator circuit 13 in the hysteresis Mode (Mode1), i.e., the process of increasing the comparison voltage Vcmp from 0V to the upward reversal voltage Vinvu. Line L1 corresponds to the case where the comparative voltage Vcmp fluctuates slightly, but the fluctuation range is still small. The comparator circuit 13 needs to have better noise immunity in the hysteresis Mode (Mode 1). The line L1 further includes line segments L1a, L1b, and L1c, and for the description of these line segments L1a, L1b, and L1c, see below.

Please refer to fig. 5B, which is a diagram illustrating a relationship between the comparison voltage Vcmp and the output signal Vo when the comparison circuit is in the high gain Mode (Mode 2). Fig. 5B represents, by a line L2, the circuit behavior of the comparator circuit in the high gain Mode (Mode2), i.e., the process of the comparison voltage Vcmp dropping from the upward-reversal voltage Vinvu to be equal to the downward-reversal voltage Vinvd. The line L2 is equivalent to the situation that the variation of the comparison voltage Vcmp should be reflected in the output signal Vo in real time, i.e. the comparison circuit 13 should be able to generate the output signal Vo in response to the voltage difference between the comparison voltage Vcmp at the input terminal and the reference voltage Vref. The comparator circuit 13 is required to provide a higher gain in the high gain Mode (Mode 2).

As can be seen from fig. 5A, in the hysteresis Mode (Mode1), the comparison circuit 13 needs to maintain the stability of the output signal Vo, and it is not desirable that the output signal Vo fluctuates due to slight variations of the comparison voltage Vcmp. On the other hand, as can be seen from fig. 5B, in the high gain Mode (Mode2), the comparison circuit 13 needs to have the output signal Vo quickly reflect the signal change at the input terminal.

According to a contemplated embodiment of the present invention, the coupling module 18 in the comparison circuit 13 has an elasticated design. In the flexible design, the switches S1 to S8 can be switched according to the difference between the hysteresis Mode (Mode1) and the high gain Mode (Mode 2). With the switching of the switches S1 to S8, the connection relationships between the transistors MP3 to MP6 and the nodes N1 and N2 are also changed, and the arrangement of the first-stage amplifier 15 and the second-stage amplifier 17 is changed according to the change of the mode.

Next, the operation of the comparator circuit 13 in the hysteresis Mode (Mode1) will be described with reference to fig. 6A, 6B, 7A, and 7B. Please refer to fig. 6A, which is a schematic diagram of the switches S1-S4 implemented by transmission gates (transmission gates). The transmission gates for implementing the switches S1-S4 include a PMOS transistor P1 and an NMOS transistor N1, wherein the gate of the NMOS transistor N1 receives the control signal Sctn and the gate of the PMOS transistor P1 receives the control signal Sctn.

Please refer to fig. 5A and fig. 6A simultaneously. As can be seen from fig. 5A, the output signal Vo is low in the hysteresis Mode (Mode 1). Therefore, in the hysteresis Mode (Mode1), the control signal Sct is at a high level and the control signal Sctn is at a low level. At the same time, the gate of the NMOS transistor N1 in fig. 6A is the high-level control signal Sct, and the gate of the PMOS transistor P1 is the low-level control signal Sctn, so that the switches S1 to S4 are turned on.

Referring to fig. 5B and fig. 6A, it can be seen from fig. 5B that the output signal Vo is at a high level in the high gain Mode (Mode 2). Therefore, in the high gain Mode (Mode2), the control signal Sct is at a low level and the control signal Sctn is at a high level. At the same time, the gate of the NMOS transistor N1 shown in fig. 6A is the low-level control signal Sct, and the gate of the PMOS transistor P1 is the high-level control signal Sctn, so that the switches S1 to S4 are turned off.

Fig. 6B shows the connection relationship of the internal circuit of the coupling module in the hysteresis Mode (Mode 1). As illustrated in fig. 4, in the hysteresis Mode (Mode1), the switches S1 to S4 are turned on; the switches S5-S8 are off. In order to show the connection relationship between the transistors more clearly, FIG. 6B does not show the switches S5-S8 in the open state. Table 3 further summarizes the connection relationship between the terminals of the transistors MP 3-MP 6 in the hysteresis Mode (Mode 1).

TABLE 3

Please refer to fig. 6B and table 3. In the hysteresis Mode (Mode1), the source of the transistor MP3 is electrically connected to the supply voltage Vdd, the drain is electrically connected to the node N1, and the gate is electrically connected to the node N1 due to the conduction of the switch S3; the source of the transistor MP4 is electrically connected to the supply voltage Vdd, the drain is electrically connected to the node N2, and the gate is electrically connected to the node N2 when the switch S4 is turned on; the source of the transistor MP5 is electrically connected to the supply voltage Vdd, the drain is electrically connected to the node N2 due to the switch S1 being turned on, and the gate is electrically connected to the node N2; the transistor MP6 has a source electrically connected to the supply voltage Vdd, a drain electrically connected to the node N2 when the switch S2 is turned on, and a gate electrically connected to the node N1.

Fig. 7A and 7B are schematic diagrams illustrating the current flow direction of the comparator circuit in the hysteresis Mode (Mode 1). When the comparator circuit 13 is in the hysteresis Mode (Mode1), the switches S1 to S8 of the coupling module 18 are connected to the transistors MP3 to MP6 as shown in fig. 6B. For convenience of illustration, in fig. 7A and 7B, the switches S1 to S4 in fig. 6B have been further omitted, and the positions of the transistors are adjusted, so that the connection relationship between the elements is simplified.

Please refer to the line L1a in fig. 5A and fig. 7A. The line segment L1a of fig. 5A corresponds to the case where the comparison voltage Vmp is smaller than the threshold voltage Vth. First, the states of the transistors (MP3, MP1, and MP6) whose gates are connected to the node N1 will be described. At this time, the transistor MN1 is turned on due to the gate continuously receiving the reference voltage Vref, and a current I flowing through the transistor MN1 is generated_mn1. At this time, because of the current I_mn1The voltage at the node N1 is lowered, and the transistors MP3, MP1, and MP6 are turned on.

Next, the states of the transistors (MP5, MP4, MP2) whose gates are connected to the node N2 will be described. At this time, the comparison voltage Vcmp received through the gate of the transistor MN2 is still small enough not to turn on the transistor MN 2. Therefore, the transistor MN2 is in an off state. In conjunction, the gates of the transistors MP5, MP4, MP2 are also floating because they are connected to the node N2. Therefore, the transistors MP5, MP4, MP2 will be turned off.

At this time, although the transistor MP6 is turned on by the gate receiving the low voltage of the node N1, no current flows through the transistor MP6 because the drain of the transistor MP6 is connected to the node N2 in a floating state. Therefore, in fig. 7A, the total current I flowing through the transistor MN5_mn5All from the current I flowing through the transistor MN1_mn1。

When the comparison voltage Vcmp is gradually increased to Vcmp-Vref-Vgs_mn1+Vt_mn2At this time, the transistor MN2 starts to be turned on. Accordingly, the threshold voltage Vth in fig. 7A can be defined as Vth-Vref-Vgs_mn1+Vt_mn2。

Please refer to the line L1B in fig. 5A and fig. 7B. The comparison voltage Vcmp is increased from the threshold voltage Vth to near but still less than the upward reversal voltage Vinvu.

First, the states of the transistors (MP3, MP1, and MP6) whose gates are connected to the node N1 will be described. At this time, the transistor MN1 is turned on due to the gate continuously receiving the reference voltage Vref, and a current I flowing through the transistor MN1 is generated_mn1. At this time, because of the current I_mn1The voltage at the node N1 is lowered, and the transistors MP3, MP1, and MP6 are turned on. At this time, a current I flowing through the transistor MN1_mn1Equal to the current I flowing through the transistor MP3_mp3。

Next, the states of the transistors (MP5, MP4, MP2) whose gates are connected to the node N2 will be described. At this time, the comparison voltage Vcmp received through the gate of the transistor MN2 is sufficient to turn on the transistor MN 2. Therefore, the transistor MN2 is in a conductive state. At this time, the current I flowing through the transistor MP6_mp6The voltage at node N2 will be raised and the transistors MP5, MP4, MP2 will remain off. At this time, the current I flowing through the transistor MP6_mp6Will further flow through transistor MN2 to form a current I_mn2. I.e. I_mp6＝I_mn2。

Therefore, in fig. 7B, the total current I flowing through the transistor MN5_mn5Part of the current I flowing through the transistor MN1_mn1Part of the current I flowing through the transistor MN2_mn2. And, because the transistor MP5 is turned off, the current I flowing through the transistor MN1_mn1Equal to the current I flowing through the transistor MP3_mp3(i.e., I)_mn1＝I_mp3) (ii) a Because the transistor MP4 is turned off, the current I flowing through the transistor MN2_mn2Equal to the current I flowing through the transistor MP6_mp6(i.e., I)_mn2＝I_mp6). Wherein the current I flowing through the transistor MP6_mp6With the current I flowing through the transistor MP3_mp3The relationship between the current amplification factor and the current amplification factor can be determined according to the current amplification factor beta of the transistor MP6_mp6Beta of transistor MP3_mp3Is represented by_mp6＜(β_mp6/β_mp3)*I_mp3。

Please refer to the line L1c in fig. 5A and fig. 7B. When the comparison voltage Vcmp is equal to the upward-inversion voltage Vinvu, a current I flowing through the transistor MP6_mp6Further increases, and the current I flowing through the transistor MP3_mp6With the current I flowing through the transistor MP6_mp3In a relationship of_mp6＝(β_mp6/β_mp3)*I_mp3。

The current relationship corresponding to the line segment L1c can be arranged as the formulas (3) to (6).

I_mn1＝I_mp3..

I_mn2＝I_mp6The

I_mp6＝(β_mp6/β_mp3)*I_mp3＝[(W_mp6/L_mp6)/(W_mp3/L_mp3)]*I_mp3..

I_mn2＝I_mn5-I_mn1..

In fig. 7B, the reference voltage Vref can be expressed as a voltage difference (Vgs) between the gate and the source of the transistor MN1_mn1) And the voltage difference between the drain and source of transistor MN5 (Vds)_mn5) The sum of (a) and (b) is as shown in formula (7).

Vref＝Vgs_mn1+Vds_mn5..

On the other hand, in fig. 7B, the comparison voltage Vcmp can be expressed as a voltage difference between the gate and the source (Vgs) of the transistor MN2_mn2) And the voltage difference between the drain and source of transistor MN5 (Vds)_mn5) The sum of (a) and (b) is shown in formula (8).

Vcmp＝Vgs_mn2+Vds_mn5..

Furthermore, at the upward inversion point, the comparison voltage Vcmp is equal to the sum of the reference voltage Vref and the hysteresis voltage Vhys, as shown in equation (9).

.

From equations (8) and (9), equation (10) can be further derived.

Vcmp＝Vref+Vhys＝Vgs_mn2+Vds_mn5..

Then, using equation (10), the hysteresis voltage Vhys can be expressed as the voltage difference (Vgs) between the gate and the source of the transistor MN2_mn2) And the voltage difference (Vgs) between the gate and source of transistor MN1_mn1) The difference from each other is as shown in equation (11).

Vhys＝Vgs_mn2+Vds_mn5-V_ref

＝Vgs_mn2+Vds_mn5-(Vgs_smn1+Vds_mn5)

＝Vgs_mn2-Vgs_mn1..

The current I flowing through the transistor MN2 according to the current formula of the transistor_mn2Can be based on the voltage difference Vgs between the gate and the source of the transistor MN2_mn2And with the current amplification beta of transistor MN2_mn2And is shown as

Similarly, current I flowing through transistor MN1_mn1Can be based on the voltage difference Vgs between the gate and the source of the transistor MN1_mn1And with the current amplification beta of transistor MN1_mn1But is instead shown as being, for example,

equation (11) can be further modified from equations (12) and (13), and hysteresis voltage Vhys can be expressed as equation (14).

As can be seen from equation (14), the hysteresis voltage Vhys of the comparator circuit 13 is only equal to the current amplification factor β of the transistor MN1_mn1Current amplification factor beta of transistor MN2_mn2Current I flowing through transistor MN1_mn1And a current I flowing through the transistor MN2_mn2And (4) correlating. Accordingly, the hysteresis voltage Vhys is not affected by the magnitude of the reference voltage Vref.

As can be seen from the foregoing description, in the hysteresis Mode (Mode1), the transistors MP5, MP4, and MP2 are kept off, and the transistors MN1, MP4, MP1, MN3, MN4, and MN5 are kept on. In addition, the transistor MN2 is OFF when the comparison voltage Vcmp is less than the threshold voltage Vth (i.e., Vcmp < Vth), but the transistor MN2 will be ON when the comparison voltage Vcmp is greater than or equal to the threshold voltage Vth (i.e., Vcmp ≧ Vth).

Next, the operation of the comparator circuit 13 in the high gain Mode (Mode2) will be described with reference to fig. 8A, 8B, and 9. Please refer to fig. 8A, which is a schematic diagram of the switches S5-S8 implemented by transmission gates. The transmission gates for implementing the switches S5-S8 include a PMOS transistor P2 and an NMOS transistor N2, wherein the gate of the NMOS transistor N2 receives the control signal Sctn and the gate of the PMOS transistor P2 receives the control signal Sct.

Please refer to fig. 5A and fig. 8A simultaneously. As can be seen from fig. 5A, the output signal Vo is low in the hysteresis Mode (Mode 1). Therefore, in the hysteresis Mode (Mode1), the control signal Sct is at a high level and the control signal Sctn is at a low level. At the same time, the gate of the NMOS transistor N2 in fig. 8A is the low-level control signal Sctn, and the gate of the PMOS transistor P2 is the high-level control signal Sct, so that the switches S5 to S8 are turned off.

Referring to fig. 5B and fig. 8A, it can be seen from fig. 5B that the output signal Vo is at a high level in the high gain Mode (Mode 2). Therefore, in the high gain Mode (Mode2), the control signal Sct is at a low level and the control signal Sctn is at a high level. At the same time, the gate of the NMOS transistor N2 in fig. 8A is the high-level control signal Sctn, and the gate of the PMOS transistor P2 is the low-level control signal Sct, so that the switches S5 to S8 are turned on.

Fig. 8B shows the connection relationship of the internal circuit of the coupling module in the high gain Mode (Mode 2). As described above, in the high gain Mode (Mode2), the switches S1 to S4 are off; the switches S5-S8 are turned on. In order to more clearly show the connection relationship between the transistors, fig. 8B does not show the switches S1 to S4 in the off state. Table 4 further summarizes the connection relationship between the terminals of the transistors MP 3-MP 6 in the high gain Mode (Mode 2).

TABLE 4

Please refer to fig. 8B and table 4. In the high gain Mode (Mode2), the source of the transistor MP3 is electrically connected to the supply voltage Vdd, the drain is electrically connected to the node N1, and the gate is electrically connected to the node N2 when the switch S7 is turned on; the source of the transistor MP4 is electrically connected to the supply voltage Vdd, the drain is electrically connected to the node N2, and the gate is electrically connected to the node N1 when the switch S8 is turned on; the source of the transistor MP5 is electrically connected to the supply voltage Vdd, the drain is electrically connected to the node N2 due to the switch S5 being turned on, and the gate is electrically connected to the node N2; the transistor MP6 has a source electrically connected to the supply voltage Vdd, a drain electrically connected to the node N1 when the switch S6 is turned on, and a gate electrically connected to the node N1.

Fig. 9 is a schematic diagram of the current flow of the comparator circuit in the high gain Mode (Mode 2). When the comparison circuit 13 is in the high gain Mode (Mode2), the switches S1 to S8 of the coupling module 18 are connected to the transistors MP3 to MP6 as shown in fig. 6B. For convenience of illustration, in fig. 9, the switches S5-S8 in fig. 8B have been further omitted, and the positions of the transistors are adjusted to make the connection relationship between the elements simpler. At this time, the transistors MP3 and MP4 are both turned on, and generate the current I flowing through the transistor MP3_mp3Current I flowing through transistor MP4_mp4。

As described above, in fig. 9, the following relationship is provided between the currents. Current I flowing through transistor MN1_mn1Is the current I flowing through the transistor MP3_mp3With the current I flowing through the transistor MP6_mp6Sum of (i.e., I)_mn1＝I_mp3+I_mp6) (ii) a Current I flowing through transistor MN2_mn2Is the current I flowing through the transistor MP4_mp4With the current I flowing through the transistor MP5_mp5Sum of (i.e., I)_mn2＝I_mp4+I_mp5) (ii) a And, the total current I flowing through the transistor MN5_mn5Is the current I flowing through the transistor MN1_mn1With the current I flowing through the transistor MN2_mn2Sum of (i.e., I)_mn5＝I_mn1+I_mn2)。

In fig. 9, transistors MP5, MP6, MP1, MP2, MN3, MN4 collectively form the second-stage amplifier 17 that generates the output signal Vo according to the voltages of the nodes N1, N2. Second stage gain A provided by second stage amplifier 17_VN2May be based on the transconductance gm of the transistor MP2_mp2And the conductance (reciprocal resistance) gds between the source and the drain of the transistor MP2_mp2The conductance gds between the source and the drain of the transistor MN4_mn4As shown below.

The transistors MN1, MN2, MP3, and MP4 together form the first-stage amplifier 15 that determines the voltages of the nodes N1 and N2 according to the reference voltage Vref and the comparison voltage Vcmp. First stage amplifier 15 provides a first stage gain A_VN1Can be based on mutual conductance gm of transistor MN2_mn2And mutual conductance gm of transistor MP5_mp5And mutual conductance gm of transistor MP4_mp4As shown below.

Also, the ratio of the mutual conductance of the transistors is equal to the ratio of the current amplification, i.e.,thus, the first stage gain A of equation (16)_VN1Can be further represented by formula (17).

First stage gain A according to equation (17)_VN1Second-stage gain A of the formula (15)_VN2Further, the gain a of the comparator circuit 13 in the high gain Mode (Mode2) can be calculated_VN. As shown in equation (18), the gain a of the comparator circuit 13 in the high gain Mode (Mode2)_VNCan be expressed as a first stage gain A_VN1And a second stage gain A_VN2The product of (a).

As can be seen from equation (18), the comparison circuit architecture of the present disclosure is equivalent to calculating the gain a_VNAdditionally introducing a gain factorBy selecting a suitable current amplification factor beta_mp4、β_mp5The value of the gain coefficient C can be increased, thereby improving the gain effect. For example, if the current amplification factor β is selected_mp4、β_mp5Ratio (β) of_mp4/β_mp) Is beta_mp4/β_mp5When 3/4, the gain factor C is 4. Associated, gain A_VNA further four-fold increase is possible.

As can be seen from the description of fig. 9, if the current amplification factor β of the transistor MP4 is larger than the current amplification factor β of the transistor MP4_mp4Less than the current amplification beta of the transistor MP5_mp5(i.e.. beta.)_mp4＜β_mp5) In this case, the gain A of the comparator circuit 13 can be increased_VN. That is, if the transistors MP3, MP4 having a smaller current amplification factor are used in the first-stage amplifier 15 and the transistors MP5, MP6 having a larger current amplification factor are used in the second-stage amplifier 17, it is possible to provideThe gain a of the step-up comparison circuit 13 in the high gain Mode (Mode2)_VN。

Please refer to table 5, which is a comparison table of connection modes of the transistors in the collection and coupling module 18, which are changed according to different operation modes. Details of table 5 are already described above and will not be described in detail here.

TABLE 5

Fig. 10 is a schematic diagram of transistors included in the coupling module. In fig. 10, the coupling module 18 includes a switch circuit 185, a high current amplification circuit 18a and a low current amplification circuit 18 b. The switch circuit 185 includes switches S1-S8; the high-current amplification circuit 18a includes transistors MP5, MP 6; and, the low-current amplification circuit 18b includes transistors MP3, MP 4. According to an embodiment contemplated by the present invention, the current amplification β of the transistors MP3, MP4, MP5, MP6_mp3、β_mp4、β_mp5、β_mp6Has the following relationship: beta is a_mp6＝β_mp5＞β_mp4＝β_mp3。

In fig. 10, the broken line represents the connection relationship in the hysteresis Mode (Mode 1). The switches S1-S4 are also indicated by dashed boxes due to the switches S1-S4 being turned on in the hysteretic Mode (Mode 1). On the other hand, fig. 10 represents the connection relationship in the high gain Mode (Mode2) with a solid line. The switches S5-S8 are indicated by solid line boxes due to the switches S5-S8 being turned on in the high gain Mode (Mode 2).

Please refer to fig. 6B and fig. 10. In the hysteresis Mode (Mode1), the node N1 is connected to the drain of the transistor MP5 via the switch S1 and to the gate of the transistor MP3 via the switch S3. On the other hand, the node N2 is connected to the drain of the transistor MP6 via the switch S2 and to the gate of the transistor MP4 via the switch S4.

Please refer to fig. 7B and fig. 10. In the high gain Mode (Mode2), the node N1 is connected to the drain of the transistor MP6 via the switch S6 and to the gate of the transistor MP4 via the switch S8. On the other hand, the node N2 is connected to the drain of the transistor MP5 via the switch S5 and to the gate of the transistor MP3 via the switch S7.

Accordingly, the gates of the transistors MP5 and MP6 are electrically connected in a fixed manner, and the drains are electrically connected to one of the nodes N2 and N1 according to different modes. For example, in the hysteretic Mode (Mode1), the drain of transistor MP5, which is connected to node N1, is connected to node N2 instead of being in the high-gain Mode (Mode 2). For another example, in the hysteresis Mode (Mode1), the drain of the transistor MP6 connected to the node N2 is connected to the node N1 in the high gain Mode (Mode 2).

On the other hand, the drains of the transistors MP3 and MP4 are electrically connected, and the gates are electrically connected to one of the nodes N2 and N1 according to the mode. For example, in the hysteresis Mode (Mode1), the gate of the transistor MP3 connected to the node N1 is connected to the node N2 in the high gain Mode (Mode 2). For another example, in the hysteresis Mode (Mode1), the gate of the transistor MP4 connected to the node N2 is connected to the node N1 in the high gain Mode (Mode 2).

As shown in fig. 3, a part of the coupling module 18 belongs to the first stage amplifier 15, and another part belongs to the second stage amplifier 17. As shown in fig. 10, the coupling module 18 includes a switch circuit 185, a high current amplification circuit 18a and a low current amplification circuit 18 b. Herein, the correspondence between the elements (switches S1-S8, transistors MP 3-MP 6) in the coupling module 18 and the first-stage amplifier 15 and the second-stage amplifier 17 is not fixed, but varies with the operation mode of the comparison circuit 13. Next, the correspondence between the elements (switches S1 to S8, transistors MP3 to MP6) in the coupling module 18 and the first-stage amplifier 15 and the second-stage amplifier 17 is described herein with reference to fig. 11.

Please refer to fig. 11, which is a schematic diagram of dynamically adjusting transistors in the coupling module according to different modes of the comparison circuit. The top of fig. 11 shows the transistor configuration of the coupling module 18 in the hysteresis Mode (Mode1), wherein the arrangement of the transistors MP 3-MP 6 is equivalent to the relative positions of the simplified connection relationships of the transistors in fig. 7A and 7B. The lower portion of fig. 11 is the transistor configuration of coupling module 18 in the high gain Mode (Mode 2). The arrangement of the transistors MP 3-MP 6 is equivalent to the relative position of the simplified connection relationship of the transistors in fig. 8.

Table 6 summarizes how the high current amplification circuit 18a and the low current amplification circuit 18b enable the transistors to be coupled across each other or form an external current mirror with the transistors MP1 and MP2 according to the different modes of the comparison circuit 13.

TABLE 6

In the hysteresis Mode (Mode1), the transistors MP5, MP6 in the high current amplification circuit 18a are connected in a cross-connected manner. At the same time, the transistors MP3, MP4 in the low-current amplification circuit 18b form external current mirrors 21a, 21b with the transistors MP1, MP2, respectively. Therefore, in the hysteresis Mode (Mode1), the high-current amplification circuit 18a belongs to the first-stage amplifier 15, and the low-current amplification circuit 18b belongs to the second-stage amplifier 17.

In the high gain Mode (Mode2), the transistors MP3, MP4 in the low current amplification circuit 18b are connected in a cross-connected manner. At the same time, the transistors MP5, MP6 in the high current amplification circuit 18a and the transistors MP2, MP1 form external current mirrors 22b, 22a, respectively. Therefore, in the high gain Mode (Mode2), the low current amplification circuit 18b belongs to the first-stage amplifier 15, and the high current amplification circuit 18a belongs to the second-stage amplifier 17.

As can be seen from the foregoing description, the comparison circuit 13 of the present disclosure has a symmetrical circuit structure. Therefore, the comparison circuit 13 adopting the architecture of the present disclosure can reduce the mismatch for the circuit layout. In addition, the architecture of the comparison circuit 13 according to the embodiment of the disclosure can improve the effects of hysteresis and gain while maintaining the same power consumption and area.

In summary, the present disclosure provides a switch circuit in a comparison circuit. The switching circuit can dynamically change the connection mode of the transistor according to different modes of the comparison circuit. Since the switch circuit can change the connection relationship of the transistors according to the mode, the comparison circuit can select a relatively appropriate mode to set the configuration of the first-stage amplifier and the second-stage amplifier according to the mode.

In the hysteresis Mode (Mode1), the hysteresis voltage Vhys is only equal to the sizes of the transistors MN1, MN2, MP3, MP6 and the current I flowing through the transistor MN1_mn1Current I flowing through transistor MN2_mn2The correlation is not affected by the magnitude of the reference voltage Vref. In addition, the comparison circuit of the invention can provide higher gain in the high gain Mode (Mode 2).

While the present invention has been described with reference to the above embodiments, it is not intended to be limited thereto. Various modifications and adaptations may occur to those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the appended claims.