阅读说明：本技术 制造集成电路的方法和设计集成电路的计算系统 (Method for manufacturing integrated circuit and computing system for designing integrated circuit ) 是由 金曜澖 于 2019-05-31 设计创作，主要内容包括：提供了一种制造集成电路的方法和一种设计集成电路的计算系统。一种制造其中设置有半导体器件的集成电路的方法包括：根据接收到的工艺变量,通过使用包括多个模型参数的模型参数文件,对半导体器件的电特性进行仿真,基于仿真的结果生成布局数据,以及根据基于布局数据的半导体器件布局制造集成电路,其中,多个模型参数以关于工艺变量的至少一个函数的形式存储在模型参数文件中。(A method of manufacturing an integrated circuit and a computing system for designing an integrated circuit are provided. A method of manufacturing an integrated circuit having a semiconductor device disposed therein includes: the method includes simulating electrical characteristics of the semiconductor device according to the received process variables by using a model parameter file including a plurality of model parameters stored in the model parameter file in the form of at least one function with respect to the process variables, generating layout data based on results of the simulation, and fabricating the integrated circuit according to the semiconductor device layout based on the layout data.)

1. A method of manufacturing an integrated circuit having a semiconductor device disposed therein, the method comprising:

simulating, using at least one processor, characteristics of the semiconductor device based on at least one received process variable using a model parameter file comprising a plurality of model parameters, the plurality of model parameters corresponding to at least one function associated with the at least one process variable;

generating, using the at least one processor, semiconductor device layout data based on results of the simulation; and

the integrated circuit is fabricated according to a semiconductor device layout based on the semiconductor device layout data.

2. The method of claim 1, wherein simulating the characteristic comprises:

receiving information relating to the at least one process variable;

determining a model parameter from the plurality of model parameters corresponding to the value of the at least one process variable; and

outputting characteristic data corresponding to the value of the at least one process variable based on the determined model parameter, the characteristic data including an electrical or physical characteristic of the semiconductor device.

3. The method of claim 1, further comprising:

modeling, using the at least one processor, the semiconductor device;

generating, using the at least one processor, the model parameter file including the plurality of model parameters based on a result of modeling the semiconductor device, and

generating the model parameter file includes:

receiving characteristic data of a plurality of semiconductor devices, the characteristic data corresponding to internal conditions of the plurality of semiconductor devices,

extracting point model parameters respectively corresponding to the internal conditions of the plurality of semiconductor devices based on each internal condition of each of the plurality of semiconductor devices and the value of the characteristic data, an

Based on the point model parameters, interval model parameters are extracted, the interval model parameters corresponding to intervals between different internal conditions associated with each of the plurality of semiconductor devices.

4. The method of claim 3, wherein extracting the interval model parameters comprises determining an accuracy of the point model parameters.

5. The method of claim 3, wherein extracting the interval model parameters comprises: extracting the interval model parameters corresponding to an interval between the different internal conditions based on the point model parameters and a desired regression equation.

6. The method of claim 1, wherein the at least one process variable comprises:

internal process variables corresponding to physical and structural characteristics in the semiconductor device; and

external process variables corresponding to physical and structural characteristics due to the peripheral environment of the semiconductor device.

7. The method of claim 6, wherein simulating the characteristic comprises:

receiving information relating to the internal process variable and information relating to the external process variable;

determining an internal model parameter from the plurality of model parameters corresponding to a value of the internal process variable;

determining an external model parameter based on the value of the internal process variable, the value of the external process variable, and an external model formula; and

outputting characteristic data including an electrical characteristic of the semiconductor device, the electrical characteristic corresponding to the value of the internal process variable and the value of the external process variable, based on the determined external model parameters;

wherein the external model formula comprises a formula for converting the internal model parameters to the external model parameters, and at least one function on the internal process variables and the external process variables.

8. The method of claim 6, wherein the internal process variables comprise at least one of a length of a gate line in a transistor and a width of an active area of the transistor.

9. The method of claim 6, wherein the external process variables include physical and structural characteristics of the semiconductor device related to local layout effects caused by another semiconductor device disposed around the semiconductor device.

10. The method of claim 1, wherein,

the model parameter file comprises a plurality of model parameter sets, each model parameter set comprising a plurality of model parameters; and is

Simulating the characteristic includes selecting one of the plurality of model parameter sets based on a range of values of the received process variable.

11. A method of fabricating an integrated circuit, the method comprising:

generating, using at least one processor, a model parameter file including a plurality of model parameters based on results of modeling a semiconductor device included in the integrated circuit, the generating the model parameter file including:

receiving first characteristic data of a first semiconductor device, the first characteristic data corresponding to a first internal condition of the first semiconductor device,

receiving second characteristic data of a second semiconductor device, the second characteristic data corresponding to a second internal condition of the second semiconductor device,

extracting a plurality of first point model parameters corresponding to the first internal condition,

extracting a plurality of second point model parameters corresponding to the second internal condition based on the first internal condition, the second internal condition, the value of the first characteristic data, and the value of the second characteristic data, an

Calculating an interval model parameter corresponding to an interval between the first internal condition and the second internal condition based on the plurality of first point model parameters and the plurality of second point model parameters;

simulating, using the at least one processor, characteristics of the semiconductor device based on the model parameter file in accordance with the received process variables;

generating, using the at least one processor, semiconductor device layout data based on results of the simulation; and

the integrated circuit is fabricated according to a semiconductor device layout based on the semiconductor device layout data.

12. The method of claim 11, further comprising:

calculating, using the at least one processor, the interval model parameters; and

determining, using the at least one processor, an accuracy of the plurality of first point model parameters and the plurality of second point model parameters.

13. The method of claim 11, wherein calculating the interval model parameters comprises:

calculating the interval model parameter corresponding to a condition interval between the first internal condition and the second internal condition based on the plurality of first point model parameters, the plurality of second point model parameters, and a desired regression equation.

14. The method of claim 11, wherein the first internal condition and the second internal condition are adjacent to each other.

15. A computing system for designing an integrated circuit, the computing system comprising:

a memory configured to store a circuit simulation program for extracting characteristics of a semiconductor device included in the integrated circuit and a model parameter file including a plurality of model parameters including a plurality of point model parameters as constants and a plurality of interval model parameters provided as a function related to at least one process variable; and

at least one processor configured to access the processor and run the circuit emulation program, the circuit emulation program causing the at least one processor to:

receiving information relating to the at least one process variable,

determining from the model parameter file model parameters corresponding to the values of the at least one process variable, an

Based on the determined model parameters, characteristic data including characteristics of the semiconductor device is output.

16. The computing system of claim 15, wherein the circuit emulation program causes the at least one processor to:

acquiring the point model parameters from the model parameter file as a plurality of model parameter sets; and

obtaining the interval model parameters from the model parameter file as a plurality of model formulas, and outputting the characteristic data includes:

selecting some of the plurality of model parameter sets,

selecting one of the plurality of model equations based on the received information about the at least one process variable, an

Outputting the characteristic data based on the selected model parameter set and the selected model formula.

17. The computing system of claim 16, wherein the at least one process variable comprises:

internal process variables corresponding to physical and structural characteristics in the semiconductor device, an

External process variables corresponding to physical and structural characteristics due to the peripheral environment of the semiconductor device.

18. The computing system of claim 17, wherein the plurality of model formulas comprises:

a plurality of internal model equations comprising functions related to the internal process variables; and

a plurality of external model equations comprising functions on the internal process variables and the external process variables.

19. The computing system of claim 18, wherein the circuit emulation program causes the at least one processor to:

determining internal model parameters corresponding to the values of the internal process variables;

selecting one of the plurality of external model equations based on the values of the internal process variables and the values of the external process variables;

determining external model parameters based on the internal model parameters, the values of the external process variables, and the external model formula; and

outputting the characteristic data based on the determined external model parameters, the characteristic data including a characteristic of the semiconductor device, the characteristic corresponding to a value of the internal process variable and a value of the external process variable.

20. The computing system of claim 17, wherein the external process variables comprise:

physical and structural characteristics of the semiconductor device corresponding to a local layout effect caused by another semiconductor device disposed around the semiconductor device.

Technical Field

Various example embodiments of the inventive concepts relate to a computing system for designing an integrated circuit by analyzing characteristics of a semiconductor device based on extracted model parameters, an apparatus thereof, a method of manufacturing an integrated circuit using the computing system, and/or a non-transitory computer-readable medium thereof.

Background

As semiconductor devices become highly integrated and miniaturized, factors in processes for designing and manufacturing semiconductor devices have been combined, which results in various unintended electrical characteristics of the semiconductor devices. Therefore, in order to overcome the limitations of semiconductor processes and devices, understand phenomena, and reduce experimental costs, the semiconductor industry has an increasing demand for a Technology Computer Aided Design (TCAD) process-device simulation environment based on physical simulation. In addition, in order to provide accurate specifications of semiconductor device products, characteristics of semiconductor devices need to be predicted and simulated.

Disclosure of Invention

Various example embodiments according to the inventive concepts provide a computing system for designing an integrated circuit, an apparatus of the computing system, a method of manufacturing an integrated circuit by using the computing system, and/or a non-transitory computer-readable medium of the computing system, which is capable of accurately predicting electrical characteristics of a semiconductor device included in an integrated circuit by reflecting different processing conditions for manufacturing the semiconductor device.

According to an aspect of at least one example embodiment of the inventive concept, there is provided a method of manufacturing an integrated circuit having a semiconductor device disposed therein, the method including: simulating, using at least one processor, characteristics of the semiconductor device based on at least one received process variable using a model parameter file comprising a plurality of model parameters, the plurality of model parameters corresponding to a function associated with the at least one process variable; generating, using the at least one processor, semiconductor device layout data based on results of the simulation; and manufacturing the integrated circuit according to a semiconductor device layout based on the semiconductor device layout data.

According to another aspect of at least one example embodiment of the inventive concept, there is provided a method of manufacturing an integrated circuit, the method including: generating, using at least one processor, a model parameter file including a plurality of model parameters based on results of modeling a semiconductor device included in the integrated circuit, the generating the model parameter file including: receiving first characteristic data of a first semiconductor device, the first characteristic data corresponding to a first internal condition of the first semiconductor device, receiving second characteristic data of a second semiconductor device, the second characteristic data corresponding to a second internal condition of the second semiconductor device, extracting a plurality of first point model parameters corresponding to the first internal condition, extracting a plurality of second point model parameters corresponding to the second internal condition based on the first internal condition, the second internal condition, a value of the first characteristic data, and a value of the second characteristic data, and calculating a section model parameter corresponding to a section between the first internal condition and the second internal condition based on the plurality of first point model parameters and the plurality of second point model parameters; simulating, using the at least one processor, characteristics of the semiconductor device based on the model parameter file in accordance with the received process variables; generating, using the at least one processor, semiconductor device layout data based on results of the simulation; and manufacturing the integrated circuit according to a semiconductor device layout based on the semiconductor device layout data.

According to another aspect of at least one example embodiment of the inventive concept, there is provided a computing system for designing an integrated circuit, the computing system comprising: a memory configured to store a circuit simulation program for extracting characteristics of a semiconductor device included in the integrated circuit and a model parameter file including a plurality of model parameters including a plurality of first point model parameters as constants and a plurality of interval model parameters provided as a function related to at least one process variable; and at least one processor configured to access the processor and run the circuit emulation program, the circuit emulation program causing the at least one processor to perform operations comprising: the method includes receiving information related to the at least one process variable, determining a model parameter from the model parameter file corresponding to a value of the at least one process variable, and outputting characteristic data including a characteristic of the semiconductor device based on the determined model parameter.

Drawings

Example embodiments of the present inventive concept will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a flow chart illustrating a method of fabricating an integrated circuit according to at least one example embodiment;

FIG. 2 is a block diagram of a computing system for designing an integrated circuit, according to at least one example embodiment;

FIG. 3 is a diagram depicting a circuit simulation program stored in a computing system, according to at least one example embodiment;

FIG. 4 is a flow chart illustrating a method of fabricating an integrated circuit according to at least one example embodiment;

FIG. 5 is a flow chart illustrating a method of fabricating an integrated circuit according to at least one example embodiment;

FIG. 6 is a flow chart illustrating a method of fabricating an integrated circuit according to at least one example embodiment;

FIG. 7 is a diagram for describing internal conditions of a semiconductor device included in an integrated circuit, according to at least one example embodiment;

fig. 8 is a diagram for describing internal conditions of the first and eighth semiconductor devices of fig. 7, according to at least one example embodiment;

fig. 9A to 9C are diagrams for describing a process of extracting point model parameters and a process of extracting interval model parameters in fig. 5, according to at least one example embodiment;

FIG. 10 is a graph depicting a change in an electrical characteristic of a semiconductor device as a function of a change in an internal condition of the semiconductor device, in accordance with at least one example embodiment;

FIG. 11A is a diagram depicting a circuit simulation program stored in a computing system, according to at least one example embodiment;

FIG. 11B is a flow chart illustrating a method of fabricating an integrated circuit according to at least one example embodiment;

12A and 12B are diagrams for describing external conditions, according to at least one example embodiment;

FIG. 13 is a graph depicting electrical characteristics of a semiconductor device as a function of differences between external conditions, according to at least one example embodiment; and

fig. 14 is a graph depicting a predicted change in an electrical characteristic of a semiconductor device based on a change in an external condition of the semiconductor device, according to at least one example embodiment.

Detailed Description

Hereinafter, one or more example embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

FIG. 1 is a flow chart illustrating a method of fabricating an integrated circuit according to at least one example embodiment.

Referring to fig. 1, the method of manufacturing an integrated circuit may include operations such as generating a model parameter file (S10), designing an integrated circuit (S20), and/or manufacturing an integrated circuit (S30), but example embodiments are not limited thereto. The designing of the integrated circuit (S20) includes a process of designing a layout of the integrated circuit and may be performed by a tool for designing the integrated circuit. For example, the tool for designing an integrated circuit may be a special purpose computer program comprising a plurality of special purpose computer readable instructions for execution by at least one processor, the special purpose computer program converting the at least one processor into the at least one special purpose processor. Accordingly, the design of the integrated circuit (S20) may be referred to as a computer-implemented method for designing the integrated circuit. The manufacturing of the integrated circuit (S30) includes a process of manufacturing the integrated circuit based on the designed layout, and may be performed in a semiconductor processing module, but is not limited thereto. Hereinafter, each process included in the design (S20) of the integrated circuit and the manufacture (S30) of the integrated circuit will be described below.

In operation S10, a semiconductor device to be included in an integrated circuit may be modeled to generate a model parameter file. For example, model parameters representing a correlation (and/or relationship) between at least one process variable of the semiconductor device and at least one electrical and/or physical characteristic of the semiconductor device are extracted to generate a model parameter file. Operation S10 will be described later with reference to fig. 5.

In operation S20, electrical characteristics (e.g., electromagnetic field interference, parasitic capacitance, current leakage, poor electrical response, incorrect electrical response, etc.) and/or physical characteristics (e.g., optical interference, premature physical wear, undesirable cracking, thermal characteristics, etc.) of a semiconductor device included in an integrated circuit and a circuit to which the semiconductor device is connected are simulated by using a model parameter file (S210), and layout data (e.g., semiconductor device layout data, etc.) may be generated based on the simulation result (S220). For example, at the time of generating the layout data (S220), a synthesis operation for laying out and routing standard cells defining the integrated circuit and a place and route (P & R) operation may be performed, and the simulation result based on the model parameter file may be reflected in the synthesis operation and the P & R operation. In operation S210, a process of simulating electrical and/or physical characteristics of a semiconductor device included in an integrated circuit based on a model parameter file will be described later with reference to fig. 4.

A "synthesis operation" is an operation of generating a netlist for an integrated circuit design by converting input data of the integrated circuit into a hardware form including logic gates, and may be referred to as a logic synthesis. The input data may be an abstract form of behavior of the integrated circuit (e.g., data defined in a Register Transfer Level (RTL), etc.), but is not so limited. The netlist may be generated from input data (e.g., RTL code) using a standard cell library and/or may be a gate-level netlist. In at least one example embodiment, the RTL code may be provided as an input file to a synthesis tool and the netlist may be output from the synthesis tool as an output file. A netlist may include a plurality of standard cells (e.g., code for common integrated circuit types, logic gates, logic circuits, IP cores, etc.) and information about the connection relationships between the standard cells.

The P & R operation may be an operation of performing P & R on standard cells and/or specialized cells (e.g., custom cells, one-time-use logic circuits, etc.) that define an integrated circuit and generating layout data for the integrated circuit. For example, the layout data may be data having a Graphic Design System (GDS) II format, but example embodiments are not limited thereto.

In operation S310, at least one mask (e.g., a semiconductor layout mask in a photolithography process for semiconductor manufacturing, etc.) may be generated based on the layout data. First, Optical Proximity Correction (OPC) may be performed based on layout data. Here, OPC denotes a process of changing a layout by reflecting an error caused by an optical proximity effect. Next, a mask may be manufactured according to a layout changed according to the result of OPC. Here, the mask may be manufactured by using a layout in which OPC is reflected (e.g., GDS II in which OPC is reflected, etc.).

In operation S320, a semiconductor device implementing an integrated circuit may be manufactured by using a mask. Various semiconductor processes are performed on a semiconductor substrate, such as a wafer, by using a plurality of masks to form a semiconductor device on which an integrated circuit is implemented. For example, the process using the mask may be a patterning process by using a photolithography process, but example embodiments are not limited thereto. Through the above-described patterning process, a desired pattern may be disposed on a semiconductor substrate and/or a material layer (e.g., a photoresist layer, an oxide layer, a metal layer, etc.). Here, the semiconductor process may include a deposition process, an etching process, an ion process, a cleaning process, and the like. In addition, the semiconductor process may include a packaging process in which the semiconductor device is mounted on, for example, a Printed Circuit Board (PCB) or the like, and/or a testing process in which a test is performed on the semiconductor device or the semiconductor package.

FIG. 2 is a block diagram of a computing system 10 for designing an integrated circuit, according to at least one example embodiment.

Referring to fig. 2, a computing system 10 for designing an integrated circuit (hereinafter, referred to as "integrated circuit design system 10") may include at least one processor 11, at least one memory 13, input/output devices 15, storage devices 17, and/or a bus 19, among others, although example embodiments are not limited thereto. For example, integrated circuit design system 10 may perform operation S20 of fig. 1, and so on. In one or more example embodiments, the integrated circuit design system 10 may be implemented as an integrated device (e.g., a device customized to perform the integrated circuit design method of at least one example embodiment, etc.), and thus may also be referred to as an integrated circuit design apparatus. Integrated circuit design system 10 may be provided as an apparatus dedicated to designing integrated circuits of semiconductor devices, but may be a computer for driving and/or executing various simulation tools and/or design tools. Integrated circuit design system 10 may be a fixed computing system, such as a desktop computer, workstation, server, distributed computing system, cloud computing system, etc., or a portable computing system, such as a laptop computer, etc.

At least one processor 11 (hereinafter processor 11) may be configured to execute special-purpose computer-readable instructions to perform at least one of various operations for designing an integrated circuit. The processor 11 may communicate with the memory 13, the input/output device 15, and the storage device 17 via a bus 19. The processor 11 may execute an application program loaded on the memory 13, the application program comprising computer readable instructions. For example, the processor 11 may execute the circuit simulation program 100 loaded on the memory 13, and the circuit simulation program 100 may extract the electrical and/or physical characteristics of the semiconductor device and the electrical and/or physical characteristics of the circuit including the semiconductor device.

The memory 13 may store a program including instructions for designing a layout of an integrated circuit and for performing a simulation according to the designed layout. In at least one example embodiment, a circuit simulation program 100 for extracting electrical and/or physical characteristics of a semiconductor device configuring an integrated circuit and electrical and/or physical characteristics of a circuit including the semiconductor device, and a model parameter file 200 may be loaded on the memory 13. For example, the electrical and/or physical characteristics of the semiconductor device may include a threshold voltage of the transistor, an on-current of the transistor, a current-voltage characteristic of the transistor, and the like.

The memory 13 may also include various tools such as simulation tools and the like. The memory 13 may be a volatile memory such as a Static Random Access Memory (SRAM) and a dynamic ram (dram), or a nonvolatile memory such as a phase change ram (pram), a magnetic ram (mram), a resistive ram (reram), a ferroelectric ram (fram), a flash memory, or the like.

The input/output device 15 may control user input and output from/to the user interface device. For example, the input/output device 15 may include an input device such as a keyboard, mouse, touch pad, or the like to receive input integrated circuit design data. For example, the input/output device 15 may include an output device such as a display, a speaker, or the like to display the layout data and the simulation result.

The storage device 17 may store a program such as the circuit simulation program 100 and the model parameter file 200, and the program or at least a part of the program may be loaded from the storage device 17 to the memory 13 before the processor 11 executes the program. The storage means 17 may store data to be processed by the processor 11 or data processed by the processor 11. For example, the storage 17 may store data to be processed by the circuit simulation program 100 (e.g., the model parameter file 200 generated in operation S10 of fig. 1) and characteristic data of the semiconductor device generated by the circuit simulation program 100. The circuit simulation program 100 may extract the electrical characteristics and/or physical characteristics of the semiconductor devices included in the integrated circuit based on the information on the model parameters of the model parameter file 200 stored in the storage device 17.

The storage 17 may include a non-volatile memory such as an Electrically Erasable Programmable Read Only Memory (EEPROM), a flash memory, a PRAM, a RRAM, an MRAM, a FRAM, or the like, or a storage medium such as a memory card (multi media card (MMC), eMMC, Secure Digital (SD), microSD, or the like), a Solid State Disk (SSD), a Hard Disk Drive (HDD), a magnetic tape, an optical disk, a magnetic disk, or the like. In addition, the storage device 17 may be removably attached to the computing system 10 for designing integrated circuits.

Bus 19 may be a system bus used to provide a network in computing system 10. The processor 11, the memory 13, the input/output device 15, and the storage device 17 may be electrically connected to each other via a bus 19 and may exchange data with each other. However, the bus 19 is not limited to the above example, and may also include a relay unit for efficient management.

FIG. 3 is a diagram depicting a circuit simulation program 100 stored in computing system 10, according to at least one example embodiment. As shown in fig. 2, the memory 13 may store a circuit simulation program 100, and the circuit simulation program 100 may cause the processor 11 to extract electrical characteristics and/or physical characteristics of a semiconductor device included in an integrated circuit. That is, the circuit simulation program 100 may include a plurality of instructions executable by the processor 11, and the plurality of instructions in the circuit simulation program 100 may cause the processor 11 to perform operations for extracting electrical characteristics and/or physical characteristics of the semiconductor device. Here, the circuit simulation program 100 may extract the electrical characteristics and/or the physical characteristics of the semiconductor device by using the model parameter file 200 generated in operation S10 of fig. 1.

Referring to fig. 3, the circuit simulation program 100 may include a plurality of programs, i.e., a core model module 110 and/or a model interface 120, etc., standardized according to a desired standard (e.g., an international standard), but is not limited thereto. A program may represent a sequence of computer readable instructions for performing a specific task. A program may be referred to as a function, routine, subroutine, subprogram, etc. Each program may process data provided from external sources (e.g., PV1, PV2, and model parameter file 200) and/or data generated by another program. According to at least one example embodiment, the processor 11 of fig. 1 performs operations by executing programs (e.g., 110 and/or 120, etc.), which may be expressed as programs (e.g., 110 and/or 120, etc.) performing the above-described operations.

The core model module 110 may obtain a plurality of sets of model parameters from the model parameter file 200. For example, the plurality of model parameter sets may include first to kth model parameter sets, where k may be 5 or an integer greater than 5. However, the number of model parameter sets included in the core model module 110 according to at least one example embodiment may be less than 5.

The plurality of model parameter sets may correspond to at least one of electrical and/or physical characteristics of the semiconductor device. For example, assuming that a plurality of model parameter sets for simulating the magnitude of the threshold voltage of the transistor are shown in fig. 3, the core model module 110 may further include other model parameter sets regarding other characteristics than the magnitude of the threshold voltage of the transistor in addition to the plurality of model parameter sets shown in fig. 3. However, example embodiments are not so limited, and other electrical and/or physical characteristics (e.g., electrical response time, current leakage, interference, etc.) may be modeled.

The first through kth model parameter sets may each include a plurality of model parameters P1 through Pn corresponding to values of the first process variable PV1 and values of the second process variable PV 2. Here, n may be 4 or an integer greater than 4, but example embodiments are not limited thereto, and the number of model parameters P1 through Pn may vary depending on a desired range and/or a necessary range for simulating electrical and/or physical characteristics of a semiconductor device, or a value of the first process variable PV1 and a value of the second process variable PV2, which are obtained according to the kind of circuit model.

The plurality of model parameters P1 through Pn included in each of the first through k-th model parameter sets may be expressed as constants. For example, the first model parameter set may include a plurality of first constants C11 through C1n, the second model parameter set may include a plurality of second constants C21 through C2n, and the kth model parameter set may include a plurality of first constants Ck1 through Ckn. Here, when at least one of the values of the first and second process variables PV1 and PV2 is changed, the corresponding set of model parameters may also be changed, so that the values of the plurality of model parameters P1 to Pn corresponding to the values of the first and second process variables PV1 and PV2 may be changed.

The process variables may also represent physical/structural characteristics of the semiconductor device. For example, the process variables may include a length of a gate line, a width of an active region, a channel length, a device width, a doping profile, a thickness of an oxide layer, a dielectric constant of an oxide layer, a modulation index of a channel length, a temperature of a driving semiconductor device, and the like, but example embodiments are not limited thereto. Hereinafter, for convenience of description, it will be assumed that the first process variable is a length of a gate line of a transistor and the second process variable is a width of an active area of the transistor, but example embodiments are not limited thereto. When the value of at least one of the gate line length of the transistor and the active region width of the transistor changes, the values of the plurality of model parameters P1 to Pn corresponding thereto may also change.

In fig. 3, it is described that the values of the model parameters vary according to two process variables (i.e., the first process variable and the second process variable), but example embodiments are not limited thereto, and the number of variables corresponding to each of the plurality of model parameters P1 to Pn may vary according to the electrical and/or physical characteristics of the semiconductor device desired to be obtained by calculating the values of the model parameters.

The set of model parameters applied may vary depending on the value of at least one process variable, e.g. the value of the first process variable PV1 and/or the value of the second process variable PV 2. For example, when the value of the first process variable PV1 is a first value and the value of the second process variable PV2 is a first value, the plurality of first constants C11 to C1n included in the first model parameter set may be selected as the plurality of model parameters P1 to Pn. In addition, when the value of the first process variable PV1 is the second value and the value of the second process variable PV2 is the second value, the plurality of second constants C21 to C2n included in the second model parameter set may be selected as the plurality of model parameters P1 to Pn. In addition, when the value of the first process variable PV1 is the kth value and the value of the second process variable PV2 is the kth value, the plurality of kth constants Ck1 to Ckn included in the kth model parameter set may be selected as the plurality of model parameters P1 to Pn. However, the example embodiments are not limited to the above examples.

Model interface 120 may be an Application Programming Interface (API) that helps describe additional equations above each set of model parameters. The model interface 120 is an interface for controlling the functionality provided by the circuit simulation program 100, and may include, for example, at least one interface and functionality (e.g., computer readable instructions) for controlling the model parameter file 200, control libraries, etc., and/or control data and equations over individual model parameters. Here, the model interface 120 may determine model parameters corresponding to at least one received process variable and may output characteristic DATA _ C of the semiconductor device, which includes information on predicted electrical and/or physical characteristics of the semiconductor device.

The model interface 120 may obtain a plurality of model formulas from the model parameter file 200 to determine model parameters corresponding to at least one received process variable, and may receive a plurality of sets of model parameters from the core model module 110. The plurality of model formulas may be expressions relating to and/or corresponding to model parameters that vary according to the values of the first process variable PV1 and the second process variable PV 2. The model interface 120 may determine model parameters corresponding to input values of the first process variable PV1 and values of the second process variable PV2 based on a plurality of model formulas and a plurality of sets of model parameters, and may output the characteristic DATA _ C of the semiconductor device.

The plurality of model formulas may include a first model formula connecting the first model parameter set to the second model parameter set, a second model formula connecting the second model parameter set to the third model parameter set, and a (k-1) th model formula connecting the (k-1) th model parameter set to the k-th model parameter set. For example, the first model formula may include: the model formula of the first model parameter set P1 to the first model parameter set P1 of the second model parameter set, the model formula of the second model parameter set P2 to the second model parameter set P2 of the first model parameter set, and the model formula of the nth model parameter Pn of the first model parameter set to the nth model parameter Pn of the second model parameter set. However, the first model formula may include a smaller number of model formulas than the number of model parameters included in one model parameter set (e.g., less than n). The above description about the first model formula may be applied to the second to k-th model formulas.

The applied model formula may vary depending on the range of values of the first process variable PV1 (e.g., multiple desired values of the at least one process variable PV) and the range of values of the second process variable PV 2. For example, when receiving a value of the first process variable PV1 that is greater than or equal to a first value and less than or equal to a second value and a value of the second process variable PV2 that is greater than or equal to the first value and less than or equal to the second value, the model interface 120 may determine model parameters corresponding to the value of the first process variable PV1 and the value of the second process variable PV2 based on the first set of model parameters, the second set of model parameters, and the first model formula. The model interface 120 may output, based on the determined model parameters, characteristic DATA _ C of the semiconductor device, which includes information about predicted electrical and/or physical characteristics of the semiconductor device corresponding to the values of the first and second process variables PV1 and PV 2.

In addition, when receiving the value of the first process variable PV1 that is greater than or equal to the second value and less than or equal to the third value and the value of the second process variable PV2 that is greater than or equal to the second value and less than or equal to the third value, the model interface 120 may determine model parameters corresponding to the value of the first process variable PV1 and the value of the second process variable PV2 based on the second set of model parameters, the third set of model parameters, and the second model formula. The model interface 120 may output, based on the determined model parameters, characteristic DATA _ C of the semiconductor device, which includes information about predicted electrical and/or physical characteristics of the semiconductor device corresponding to the values of the first and second process variables PV1 and PV 2.

In addition, when a value of the first process variable PV1 that is greater than or equal to the (k-1) th value and less than or equal to the k-th value and a value of the second process variable PV2 that is greater than or equal to the (k-1) th value and less than or equal to the k-th value are received, the model interface 120 may determine model parameters corresponding to the values of the first process variable PV1 and the second process variable PV2 based on the (k-1) th set of model parameters, the k-th set of model parameters, and the (k-1) th model formula. The model interface 120 may output, based on the determined model parameters, characteristic DATA _ C of the semiconductor device, which includes information about predicted electrical and/or physical characteristics of the semiconductor device corresponding to the values of the first and second process variables PV1 and PV 2.

However, the example embodiments are not limited to the above examples. In at least one example embodiment, the range of values of the first process variable PV1 and the range of values of the second process variable PV2 applied to the different model formulas may be continuous with each other.

Fig. 4 is a flowchart illustrating a method of manufacturing an integrated circuit according to at least one example embodiment, and is used to describe operation S210 in fig. 1. In operation S210, a process of performing circuit simulation of electrical characteristics and/or physical characteristics of a semiconductor device included in an integrated circuit based on the model parameter file 200 will be described below.

Referring to fig. 3 and 4, in operation S211, the model interface 120 may receive information regarding at least one process variable. For example, the model interface 120 may receive information about the values of the first process variable PV1 and the second process variable PV 2. In fig. 3, the model interface 120 receives information on the values of two process variables, but the number of process variables may vary according to the characteristics of the semiconductor device.

In operation S212, the model interface 120 may determine model parameters corresponding to values of at least one process variable. For example, the model interface 120 may select a model formula corresponding to the at least one process variable to be applied and/or a set of model parameters corresponding to the at least one process variable to be applied based on a range of values of the first process variable PV1 and/or a range of values of the second process variable PV 2. By using the selected model formula and the set of model parameters, model parameters corresponding to the values of the first process variable PV1 and the second process variable PV2 may be determined. For example, a second model formula may be selected, and the first through nth model parameters P1 through Pn may be determined based on a second model parameter set, a third model parameter set, a second model formula, and the like, but example embodiments are not limited thereto.

In operation S213, the model interface 120 may predict the electrical and/or physical characteristics of the semiconductor device corresponding to the received values of the first and second process variables PV1 and PV2 based on the determined model parameters, and may output the characteristic DATA _ C.

The computing system 10 according to at least one example embodiment may be provided to independently extract respective point model parameters that satisfy respective characteristics of at least one process variable (e.g., the first process variable PV1 and the second process variable PV2) and/or characteristics of a particular region (e.g., a desired region of a semiconductor, a desired component of an integrated circuit, a desired logic cell, a desired logic gate, a desired transistor, etc.), and thereafter output characteristic DATA (DATA _ C) regarding electrical and/or physical characteristics via a plurality of model formulas 121 in the described model interface 120, the characteristic DATA (DATA _ C) being variable while having continuity, according to the at least one process variable. Accordingly, the computing system 10 storing the circuit simulation program 100 does not need to rely on the level of accuracy of a core model module provided in advance to simulate a change in characteristics according to a change in various process variables (e.g., channel length, channel area, temperature, etc.), and thus can accurately predict various electrical and/or physical characteristics of a semiconductor device, and can ensure a continuous electrical characteristic value for at least one process variable.

Fig. 5 is a flowchart illustrating a method of fabricating an integrated circuit according to at least one example embodiment, and is used to describe operation S10 of fig. 1.

Referring to fig. 5, operation S10 may include operation S110, operation S120, and/or operation S130, but is not limited thereto. Each process included in operation S10 may be performed in a separate computing system different from the computing system performing operation S20 in fig. 1, for example, but not limited to, a computing system for extracting model parameters and simulating circuit characteristics. Operation S10 and operation S20 may be performed by the same computing system or the like.

In operation S110, electrical characteristic data and/or physical characteristic data of the semiconductor device corresponding to different internal conditions may be received. The internal condition of the semiconductor device may represent a condition regarding physical/structural characteristics of the semiconductor device. For example, two semiconductor devices may be considered to have different internal conditions when they have at least one process variable (e.g., length of gate line, width of active region, channel length, device width, doping profile, thickness of oxide layer, dielectric constant of oxide layer, modulation index of channel length, etc.) having different values from each other. The electrical characteristic data of the semiconductor device may be obtained by manufacturing a sample semiconductor device having a specific internal condition and by measuring an electrical characteristic and/or a physical characteristic of the sample semiconductor device.

In operation S120, based on the different internal conditions and the electrical characteristic values and/or the physical characteristic values respectively corresponding to the different internal conditions, point model parameters respectively corresponding to the different internal conditions may be extracted. Here, the point model parameter may be a constant having a specific value, and the constant may satisfy a corresponding internal condition, but is not limited thereto.

By selecting various core model modules developed according to desired standards such as international standards, it is possible to connect the internal conditions of the semiconductor device and the electrical characteristic values and/or physical characteristic values corresponding to the internal conditions to each other and extract model parameters. However, the accuracy of simulating the variation of the electrical and/or physical characteristics according to the internal conditions of the semiconductor device may be affected by the accuracy of the selected circuit model formula. Accordingly, when the semiconductor device has a specific electrical characteristic and/or physical characteristic (e.g., a specific magnitude of a threshold voltage, a specific operating temperature, etc.) under a specific internal condition (e.g., a length of a specific gate line and a width of a specific active region, etc.), model parameters independently satisfying a specific electrical characteristic value and/or physical characteristic value with respect to the specific internal condition are extracted, and thus the accuracy of the model parameters under the specific internal condition can be ensured regardless of the accuracy of the model formula.

In addition, various operations of extracting different model parameters respectively corresponding to different internal conditions may be performed in parallel, and thus, in operation S120, even when the number of semiconductor devices having different internal conditions increases because the number of sample semiconductor devices increases, the time taken to perform operation S120 may not increase substantially, but example embodiments are not limited thereto.

In operation S130, interval model parameters corresponding to various intervals between different internal conditions may be calculated. In detail, based on the point model parameters extracted in operation S120, interval model parameters corresponding to intervals between different internal conditions may be calculated. Unlike the point model parameters, the interval model parameters can be calculated as a function of the process variables.

Since there is a limit in increasing the number of sample semiconductor devices and characteristic data actually corresponding to a region between the internal conditions of each sample semiconductor device may not be obtained, the interval model parameters may be extracted based on the point model parameters and an arbitrary regression equation. Here, any regression equation may be stored in the calculation system for extracting the model parameters.

The point model parameters and interval model parameters may be stored in the model parameter file 200, and the core model module 110 of fig. 3 may obtain the point model parameters as a set of model parameters from the model parameter file 200, and the model interface 120 may obtain the interval model parameters as a model formula from the model parameter file 200.

According to a method of manufacturing an integrated circuit of at least one example embodiment, point model parameters respectively corresponding to different internal conditions are extracted (e.g., in parallel or sequentially), and then interval model parameters are calculated according to a region between the different internal conditions. Therefore, the time taken to extract the model parameters and generate the model parameter file can be reduced, and the accuracy of the simulation operation using the model parameters can be improved.

Fig. 6 is a flowchart illustrating a method of manufacturing an integrated circuit according to at least one example embodiment, and is used to describe operation S130 of fig. 5.

Referring to fig. 5 and 6, in operation S130, operation S131 and operation S132 may be sequentially performed, but are not limited thereto. In operation S131, the accuracy of the point model parameters extracted in operation S120 may be determined.

For example, it may be determined whether a target characteristic value (e.g., a desired electrical characteristic value and/or physical characteristic value, etc.) of the semiconductor device corresponding to the internal condition of the semiconductor device can be derived based on the extracted point model parameters and the internal condition of the semiconductor device. When the target characteristic value of the semiconductor device is derived, it can be determined that the point model parameters are accurately extracted.

When the accuracy of the point model parameters is determined in operation S131, the interval model parameters corresponding to the intervals between the different internal conditions may be calculated by using an arbitrary regression equation according to the extracted point model parameters. In at least one example embodiment, the different internal conditions may represent internal conditions that are adjacent to each other, but example embodiments are not limited thereto. For example, one internal condition in the interval between the first internal condition and the second internal condition adjacent to each other may indicate that the electrical characteristic data and/or the physical characteristic data of the semiconductor device corresponding to the internal condition is not received in operation S110.

In the case where the points are distributed according to a specific rule, the regression equation is any equation that can derive an improved and/or optimal equation suitable for the distribution state of the points. The regression equations may be pre-stored in the computing system used to extract the model parameters. The user may select an arbitrary regression equation in consideration of the relationship between the process variables and the characteristics of the semiconductor device, and the calculation system for extracting the interval model parameters may perform operation S132 based on the selected regression equation.

In at least one example embodiment, in operation S132, an interval model parameter corresponding to an interval between different internal conditions may be calculated by using the extracted point model parameter and an arbitrary regression equation. For example, an arbitrary regression equation corresponding to an interval between two adjacent internal conditions different from each other is defined, and an interval model parameter associating two electrical characteristics and/or physical characteristics respectively corresponding to the two different internal conditions may be calculated by using the regression equation. Based on the point model parameters extracted in operation S120, a regression equation for outputting characteristics between different internal conditions in the form of interpolation may be derived. The internal model parameters derived from the regression equation may be obtained as a model formula in the model interface 120 of fig. 3. Each process in fig. 5 and 6 will be described in detail below with reference to fig. 7.

Fig. 7 is a diagram for describing internal conditions of a semiconductor device included in an integrated circuit according to at least one example embodiment. Fig. 8 is a diagram for describing internal conditions of the first semiconductor device and the eighth semiconductor device of fig. 7, according to at least one example embodiment. Fig. 9A to 9C are diagrams for describing a process of extracting point model parameters and a process of extracting interval model parameters in fig. 5 according to at least one example embodiment. In fig. 9A to 9C, extraction of model parameters based on the internal conditions of the first to eighth semiconductor devices of fig. 7 will be described.

Referring to fig. 7 and 8, in operation S110 of fig. 5, electrical characteristic data and/or physical characteristic data of a semiconductor device corresponding to each of internal conditions of a plurality of semiconductor devices may be received, and fig. 7 illustrates the internal conditions of each semiconductor device. Fig. 7 may show a dispersion of a plurality of semiconductor devices each having a length of a gate line as a first process variable PV1 and a width of an active region as a second process variable PV2 (i.e., two process variables PV1 and PV2, at least one of which is different from the other). For example, the internal conditions of the first semiconductor device TA may include a gate line length PV1A of L1 and an active area width PV2A of W1. On the other hand, the internal conditions of the eighth semiconductor device TG may include the gate line length PV1G being L3 and the active area width PV2G being W3.

Referring to fig. 7 and 9A, based on the internal conditions of the first to eighth semiconductor devices TA to TG and the characteristic data (e.g., electrical characteristic data and/or physical characteristic data, etc.) of the semiconductor device corresponding to each internal condition, point model parameters corresponding to each internal condition may be extracted (S120 of fig. 5). The point model parameters corresponding to the internal conditions L1 and W1 of the first semiconductor device TA may configure a first set (Aset), and the point model parameters corresponding to the internal conditions L2 and W1 of the second semiconductor device TB may configure a second set Bset. In addition, the point model parameters corresponding to the internal conditions of each of the third to eighth semiconductor devices TC to TG may configure the third to eighth sets Cset to Gset. Here, the point model parameters included in the first set Aset to the eighth set Gset may be constants having specific values.

The point model parameters included in the first set Aset to the eighth set Gset may be extracted in parallel in units of sets. For example, the point model parameters included in the first set Aset and the point model parameters included in the second set Bset may be extracted in parallel with each other. The above description can also be applied to the point model parameters included in the third set Cset to the eighth set Gset. The first to eighth sets Aset to Gset of fig. 9A may correspond to the set of model parameters of the core model module 110 of fig. 3.

Referring to fig. 7 and 9B, section model parameters corresponding to sections bin.0, bin.1, bin.2, and the like between different internal conditions of the first to eighth semiconductor devices TA to TG may be extracted (S130 of fig. 5). The interval model parameters may be described in the form of expressions as model formulas in the model interface.

For example, an interval in which the length of the gate line as the first process variable PV1 has a value greater than or equal to L1 and less than or equal to L2 and the width of the active region as the second process variable PV2 has a value greater than or equal to W1 and less than or equal to W2 is defined as a first interval bin.0; an interval in which the length (PV1) of the gate line has a value greater than or equal to L2 and less than or equal to L3 and the width (PV2) of the active region has a value greater than or equal to W1 and less than or equal to W2 is defined as a second interval bin.1; an interval in which the length (PV1) of the gate line has a value greater than or equal to L1 and less than or equal to L3 and the width (PV2) of the active region has a value greater than or equal to W2 and less than or equal to W3 is defined as a third interval bin.2. However, example embodiments are not limited thereto.

By using the extracted point model parameters (e.g., the point model parameters included in the first set Aset to the eighth set Gset of fig. 9A), bin model parameters bin.0< P1>, bin.1< P1>, and bin.2< P1> corresponding to the bins between different internal conditions can be extracted by the model parameter extraction equations. For example, the interval model parameters corresponding to the first interval bin.0 may be extracted by using a plurality of point model parameters included in the first set Aset to the fourth set Dset of fig. 9A. The interval model parameters corresponding to the second interval bin.1 may be extracted by using a plurality of point model parameters included in the second set Bset, the third set Cset, the fifth set Eset, and the sixth set Fset of fig. 9A. The interval model parameters corresponding to the third interval bin.2 may be extracted by using a plurality of point model parameters included in the fourth set Dset, the sixth set Fset, the seventh set Gset, and the eighth set Hset of fig. 9A. Therefore, the first interval bin.0 to the third interval bin.2 defined may correspond to different interval model parameters, respectively.

The desired regression equation (and/or any regression equation) for the junction model parameters may be expressed as a function of the process variables, such that the interval model parameters may vary according to changes in internal conditions. For example, in the desired regression equation shown in fig. 9B, the interval model parameter G may be configured to have a value varying according to the length of the gate line (PV1) and the width of the active region (PV2) as process variables. In addition, under the boundary condition, the value of the interval model parameter may be equal to the value of the point model parameter, and thus, the characteristic in the interval may have a continuous output value.

Referring to fig. 7 and 9C, the final model parameter file may be provided as a plurality of model sets bin.0set, bin.1set, and bin.2set including regression equations. For example, the regression equation and the plurality of interval model parameters included in each of the plurality of model sets bin.0set, bin.1set, and bin.2set may be expressed as functions of the length of the gate line (PV1) and the width of the active region (PV 2). Therefore, when at least one of the length of the gate line (PV1) and the width of the active region (PV2) is changed, the values of the finally extracted plurality of model parameters may be changed.

For example, the set of models applied may vary according to the range of gate line lengths (PV1) and the range of active area widths (PV 2). In addition, in the first interval bin.0, model parameters included in the first model set bin.0set may be applied, in the second interval bin.1, model parameters included in the second model set bin.1set may be applied, and in the third interval bin.2, model parameters included in the third model set bin.2set may be applied. The plurality of model sets bin.0set, bin.1set, and bin.2set may respectively correspond to model equations different from each other as shown in fig. 3. For example, a first model set bin.0set may correspond to a first model formula, a second model set bin.1set may correspond to a second model formula, and a third model set bin.2set may correspond to a third model formula.

Fig. 10 is a graph for describing a change in electrical characteristics of a semiconductor device according to a change in internal conditions of the semiconductor device, according to at least one example embodiment. Fig. 10 is a graph illustrating a change in electrical and/or physical characteristics according to internal conditions included in the region a of fig. 7.

Referring to fig. 10, each point in the graph may be obtained by directly measuring a change in an electrical and/or physical characteristic of the semiconductor device (e.g., a threshold voltage of the transistor, an operating temperature of the transistor, a parasitic capacitance value of the transistor, etc.) according to a value of a first process variable PV1 (e.g., a length of the gate line). On the other hand, in each of the first to ninth sections B0 to B8 between the points of the graph, the curve connecting the points shows the characteristic value of the semiconductor device according to the value of the first process variable PV1, wherein the characteristic value is predicted by performing operations S110, S120, and S130 in fig. 5, that is, the extracted section model parameters are provided as a model formula in the model interface (120 in fig. 3).

According to the method of manufacturing an integrated circuit, even when there is no actual measurement data, the characteristics of the semiconductor devices in the first interval B0 to the ninth interval B8 can be simulated by using the interval model parameters extracted using the regression equation. In addition, since the section model parameters corresponding to the sections between the different internal conditions are extracted by a desired and/or arbitrary regression equation based on the point model parameters respectively corresponding to the different internal conditions, the accuracy of prediction of the electrical characteristics and/or physical characteristics of the semiconductor device in the sections between the different internal conditions for the internal conditions can be improved, and the characteristics of the semiconductor device can be simulated throughout all the sections of the internal conditions.

FIG. 11A is a diagram depicting a circuit simulation program stored in a computing system, according to at least one example embodiment. Fig. 11B is a flowchart illustrating a method of manufacturing an integrated circuit according to at least one example embodiment, and is used to describe operation S210 in fig. 1. In fig. 11A, description about the same elements as those in fig. 3 will be omitted.

Referring to fig. 11A, the core model module 110a may obtain a plurality of model parameter sets from the model parameter file 200 a. For example, the plurality of internal model parameter sets may include a first internal model parameter set through a kth internal model parameter set, where k may be an integer greater than or equal to 5. However, the number of model parameter sets included in the core model module 110 according to at least one example embodiment may be less than 5. The plurality of model parameters P1 through Pn included in each of the first through k-th model parameter sets may be represented as constants, but is not limited thereto.

The internal process variables may represent, but are not limited to, physical/structural characteristics of the semiconductor device. On the other hand, the external process variables may represent physical/structural characteristics that may be generated due to the peripheral environment around the semiconductor device, rather than the physical/structural characteristics of the semiconductor device itself. For example, the external process variable may represent a physical/structural characteristic that may be generated by a relationship between the semiconductor device and another semiconductor device adjacent thereto. Thus, the external process variables may include parasitic external factors that cause variations in electrical and/or physical characteristics due to, for example, Local Layout Effects (LLE), statistical effects, etc., which are generated due to the semiconductor devices disposed at the periphery. For example, the external process variable may include a distance of the active region, i.e., a distance from the gate line to an insulating layer for electrical insulation from another adjacent semiconductor device, but is not limited thereto.

The model interface 120a may be an API that helps describe additional equations above each model parameter set. The model interface 120a may obtain a plurality of model formulas 121a from the model parameter file 200a to determine model parameters corresponding to the values of the first internal process variable IPV1, the second internal process variable IPV2, and the external process variable EPV. The plurality of model formulas 121a may include first to (k-1) th internal model formulas and first to (k-1) th external model formulas.

The model interface 120a may obtain the first to (k-1) th internal model formulas from the model parameter file 200a to determine the internal model parameters, and may receive the plurality of model parameter sets from the core model module 110 a. The first to (k-1) th internal model formulas may be formulas regarding internal model parameters that vary depending on the values of the first and second internal process variables IPV1 and IPV 2. The model interface 120a may determine model parameters corresponding to the input values of the first internal process variable IPV1 and the values of the second internal process variable IPV2 based on the first through (k-1) th internal model formulas and the plurality of sets of model parameters.

The model interface 120a may obtain the first to (k-1) th external model formulas from the model parameter file 200a to determine the external model parameters. In at least one example embodiment, the first to (k-1) th external model formulas may be relationships between external model parameters and internal model parameters (e.g., corresponding to, having relationships with, etc.) the external model parameters and the internal model parameters for converting the internal model parameters into the external model parameters, and the first to (k-1) th external model formulas may be expressed as functions with respect to the internal process variables and the external process variables. Accordingly, when the internal model parameters reflect only the values of the internal process variables, the external model parameters may be user-randomized model parameters reflecting both the values of the internal process variables and the values of the external process variables, but example embodiments are not limited thereto.

The applied external model formula may vary depending on, for example, the range of values of the first internal process variable IPV1 and/or the range of values of the second internal process variable IPV2, although example embodiments are not limited thereto. For example, a first external model formula may be applied in the range of values of the first internal process variable IPV1 and/or the range of values of the second internal process variable IPV2 to which the first internal model formula is applied, a second external model formula may be applied in the range of values of the first internal process variable IPV1 and/or the range of values of the second internal process variable IPV2 to which the second internal model formula is applied, a (k-1) th external model formula may be applied in the range of values of the first internal process variable IPV1 and/or the range of values of the second internal process variable IPV2 to which the (k-1) th internal model formula is applied, and so on.

The model interface 120a may convert the internal model parameters into the external model parameters based on the first to (k-1) th external model formulas. The model interface 120a may output the characteristic DATA _ CE of the semiconductor device, in which a change in electrical and/or physical characteristics caused by parasitic external factors is reflected into the characteristic DATA _ CE of the semiconductor device based on external model parameters.

Referring to fig. 11A and 11B, in operation S211', the model interface 120a may receive information about process variables. For example, the model interface 120a may receive information about the value of the first internal process variable IPV1, the value of the second internal process variable IPV2, and the value of the external process variable EPV.

In operation S212', the model interface 120a may determine internal model parameters corresponding to values of at least one process variable. For example, the model interface 120a may select the internal model formula and the set of model parameters to be applied based on the range of values of the first internal process variable IPV1 and/or the range of values of the second internal process variable IPV2, and may determine the internal model parameters corresponding to the values of the first internal process variable IPV1 and/or the values of the second internal process variable IPV2 by using the selected internal model formula and the set of model parameters, and the like. For example, a second internal model formula may be selected and internal model parameters may be determined based on the second internal model formula, although example embodiments are not limited thereto.

In operation S213', the model interface 120a may determine the external model parameters based on the values of the internal process variables (e.g., IPV1, IPV2), the values of the external process variables EPV, and/or the external model formula, etc.

In operation S214', the model interface 120a may output the characteristic DATA _ CE including the predicted electrical and/or physical characteristics of the semiconductor device based on the value of the first internal process variable IPV1, the value of the second internal process variable IPV2, the value of the external process variable EPV, and/or the determined external model parameters, etc.

According to the computing system of at least one example embodiment, the plurality of model parameters corresponding to the electrical and/or physical characteristics of the semiconductor device do not have constant values but have values that vary according to the process variables. Thus, the computing system can accurately predict the electrical and/or physical characteristics of the semiconductor device based on the changes in the values of the process variables.

In addition, the computing system according to at least one example embodiment predicts the electrical and/or physical characteristics of the semiconductor device by reflecting not only the physical/structural characteristics of the semiconductor device but also the relationship with the adjacent semiconductor device, and thus, the electrical and/or physical characteristics of the semiconductor device may be accurately predicted.

Fig. 12A and 12B are diagrams for describing external conditions according to at least one example embodiment. Fig. 13 is a graph for describing a change in electrical characteristics of a semiconductor device according to a difference between external conditions according to at least one example embodiment. Fig. 12A and 12B illustrate only a difference in the distance of the active region, but the method and the computing system of manufacturing an integrated circuit of example embodiments are not limited thereto, and the same description may be applied to external conditions affecting electrical and/or physical characteristics of semiconductor devices included in the integrated circuit.

Referring to fig. 12A and 12B, the first semiconductor device T1 of fig. 12A and the first semiconductor device T1 'of fig. 12B have the same internal conditions (e.g., the length of the gate line IPV11 and the width of the active region IPV 12), but the distances of the active regions (EPV1 or EPV1') are different from each other, wherein the distance of the active regions is a distance from the gate line to an insulating layer formed to be insulated from the second semiconductor device T2. In this case, the first semiconductor device T1 of fig. 12A and the first semiconductor device T1 'of fig. 12B may have electrical characteristics and/or physical characteristics different from each other, and in order to simulate the electrical characteristics and/or physical characteristics of the first semiconductor device T1 of fig. 12A and the first semiconductor device T1' of fig. 12B, external conditions as well as internal conditions may be reflected.

Referring to fig. 12A, 12B, and 13, when the internal conditions are identical to each other and the distance of the active region (i.e., the external condition) is changed from the first value EPV1 of the distance of the active region to the second value EPV1' of the distance of the active region, the threshold voltage, which is the electrical characteristic of the semiconductor device, may increase. However, the amount of change in the threshold voltage of the semiconductor device may vary depending on the value of the internal condition. For example, the threshold voltage increase rate (Δ Vth _1) in the case where the length of the gate line (i.e., the value of the first internal process variable IPV1) is L1 and the width of the active region (i.e., the value of the second internal process variable IPV2) is W1 may be greater than the threshold voltage increase rate (Δ Vth _2) in the case where the length of the gate line as the first internal process variable IPV1 is L3 and the width of the active region as the second internal process variable IPV2 is W1. That is, changes in the electrical and/or physical characteristics of the semiconductor device due to changes in external conditions may be affected by the values of internal process variables. Thus, the first through (k-1) th external model equations shown in FIG. 11A may be expressed as a function of the internal process variables (IPV1 and IPV 2).

Fig. 14 is a graph for describing a variation of electrical characteristics of a semiconductor device predicted from a variation of external factors of the semiconductor device according to at least one example embodiment. Fig. 14 is a graph illustrating a change in electrical and/or physical characteristics according to internal and/or external conditions included in the region a of fig. 7. Referring to fig. 14, each point in the graph may be obtained by sufficiently measuring, for example, a variation in threshold voltage of the semiconductor device according to the length of the gate line (i.e., the first process variable IPV 1). A curve connecting points in the graph shows electrical characteristic values of the semiconductor device obtained by simulation using the extracted section model parameters.

In at least one example embodiment, when the internal condition remains unchanged, the electrical and/or physical characteristics of the semiconductor device may change when the external condition changes from the first value EPV1 to the second value EPV1', but example embodiments are not limited thereto. For example, when the length of the gate line as an internal condition is kept constant, the threshold voltage as an electrical characteristic of the semiconductor device may increase as the length of the active region is changed from the first value to the second value EPV 1'. However, the degree of variation in the electrical and/or physical characteristics of the semiconductor device may vary depending on the value of the length IPV1 (i.e., the internal condition) of the gate line.

The computing system according to at least one example embodiment predicts the electrical and/or physical characteristics of the semiconductor device by reflecting not only the physical/structural characteristics of the semiconductor device but also the relationship with the neighboring semiconductor device, and thus, the electrical and/or physical characteristics of the semiconductor device may be accurately predicted. Therefore, according to the method of manufacturing an integrated circuit, a simulation operation can be efficiently performed.

While various example embodiments of the present inventive concept have been particularly shown and described with reference to the foregoing example embodiments, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.