阅读说明：本技术 半导体装置的形成方法 (Method for forming semiconductor device ) 是由 杨建勋 林立德 于 2019-07-16 设计创作，主要内容包括：形成气隙间隔物于半导体装置中的方法,包括提供装置,其含有栅极堆叠、多个间隔物层位于栅极堆叠的侧壁上、以及源极/漏极结构与栅极堆叠相邻。在一些实施例中,移除间隔物层的第一间隔物层,以形成气隙于栅极堆叠的侧壁上。在多种例子中,接着沉积第一密封层于气隙的顶部上以形成密封的气隙,并沉积第二密封层于第一密封层上。之后采用第一蚀刻制程,自源极/漏极结构上蚀刻第一自对准接点层。在多种实施例中,第一蚀刻制程选择性地蚀刻第一自对准接点层,而第一密封层与第二密封层维持未蚀刻。(A method of forming an air gap spacer in a semiconductor device includes providing a device having a gate stack, a plurality of spacer layers on sidewalls of the gate stack, and a source/drain structure adjacent the gate stack. In some embodiments, a first spacer layer of the spacer layers is removed to form air gaps on sidewalls of the gate stack. In various examples, a first sealing layer is then deposited on top of the air gap to form a sealed air gap, and a second sealing layer is deposited on the first sealing layer. A first etching process is then used to etch the first self-aligned contact layer from the source/drain structure. In various embodiments, the first etch process selectively etches the first self-aligned contact layer while the first encapsulation layer and the second encapsulation layer remain unetched.)

1. A method of forming a semiconductor device, comprising:

providing a device comprising a gate stack, a plurality of spacer layers on a sidewall of the gate stack, and a source/drain structure adjacent the gate stack;

removing a first spacer layer of the spacer layers to form an air gap on the sidewall of the gate stack;

depositing a first sealing layer on top of the air gap to form a sealed air gap; and

a first self-aligned contact layer is etched from the source/drain structure using a first etch process, wherein the first etch process selectively etches the first self-aligned contact layer while the first sealing layer remains unetched.

Technical Field

Embodiments of the present invention relate to methods of forming air gap spacers, and more particularly, to methods of improving etch selectivity of different dielectric materials.

Background

The electronics industry has experienced a growing need for smaller and faster electronic devices that simultaneously support more and more complex functions. In view of the foregoing, there is a continuing trend in the semiconductor industry to form integrated circuits with low cost, high performance, and low power consumption. The primary approach to achieving these goals is to reduce the size of the semiconductor integrated circuit (e.g., the minimum feature size), thereby improving throughput and reducing associated costs. However, the reduction in size also increases the complexity of the semiconductor formation process. Similar advances in the processes and techniques for forming semiconductors are needed to implement the continuing advances in semiconductor integrated circuits and devices.

Recently introduced multi-gate devices have increased gate-to-channel coupling, reduced off-state current, and reduced short channel effects to improve gate control. One of these multi-gate devices is a finfet. Finfet devices are known by the name of fin structures extending from and formed on a substrate, which may be used to form channels for field effect transistors. The finfet is compatible with existing cmos processes and its three-dimensional structure allows for a significant reduction in size while maintaining gate control and mitigating short channel effects. However, even with the introduction of finfets, the significant size reduction of integrated circuits still results in increased parasitic capacitance (e.g., between the gate of the finfet and the source/drain regions or source/drain contacts). The parasitic capacitance increase degrades device performance. The prior art is therefore not fully satisfactory in all respects.

Disclosure of Invention

A method for forming a semiconductor device according to an embodiment of the present invention includes: providing a device comprising a gate stack, a plurality of spacer layers on sidewalls of the gate stack, and a source/drain structure adjacent the gate stack; removing a first spacer layer of the spacer layer to form air gaps on sidewalls of the gate stack; depositing a first sealing layer on top of the air gap to form a sealed air gap; and etching the first self-aligned contact layer from the source/drain structure using a first etching process, wherein the first etching process selectively etches the first self-aligned contact layer while the first sealing layer remains unetched.

A method for forming a semiconductor device according to an embodiment of the present invention includes: removing the spacer layer from the sidewalls of the finfet gate stack to form air gaps on the sidewalls of the finfet gate stack; conformably depositing a plurality of sealing layers on top of the air gap to form a sealed air gap; and performing a first atomic layer etching process to remove the silicon nitride layer from the source/drain adjacent to the finfet gate stack, wherein the first atomic layer etching process selectively etches the silicon nitride layer while the sealing layer remains unetched.

An embodiment of the present invention provides a semiconductor device, including: a gate stack on the first fin region, wherein a spacer layer is on a first sidewall of the gate stack; a source/drain contact metal on a second fin region adjacent to the first fin region, wherein the second fin region includes a source/drain structure, wherein a liner layer is on a second sidewall of the source/drain contact metal, and wherein the first sidewall and the second sidewall are opposite each other; an air gap spacer positioned between the spacer layer and the pad layer; and a plurality of sealing layers incorporated on top of the air gap spacers to seal and protect the air gap spacers.

Drawings

Fig. 1 is a perspective view of a finfet device in accordance with one or more embodiments of the invention.

Figure 2 is a flow chart of a method of fabricating a semiconductor device including air gap spacers in some embodiments.

Fig. 3-13 are cross-sectional views along planes substantially parallel to section AA' of fig. 1 of an exemplary device fabricated according to one or more steps of the method of fig. 2.

Fig. 14A-14D illustrate a first cycle of an exemplary atomic layer etch process flow, in some embodiments.

Fig. 15A-15D illustrate second through nth cycles of an exemplary atomic layer etch process flow, in some embodiments.

Wherein the reference numerals are as follows:

AA' section

Height H1, H2

T1, T2, T3 thickness

Width of W1

100 finfet device

102 substrate

104. 302 fin

105 source region

106 isolation region

107 drain region

108 grid structure

110. 304 gate dielectric layer

112. 306, 502 metal layer

200 method

202. 204, 206, 208, 210, 212, 214, 216, 218, 220

300. 1400 apparatus

308 first spacer layer

310 second spacer layer

310A etched back second spacer layer

312 epitaxial source/drain structures

314 silicide layer

316 metal contact layer

316A etched back metal contact layer

318 liner layer

318A etched back liner layer

320. 1402 first self-aligned contact layer

402 chemical mechanical polishing process

702 air gap

702A air gap spacer

802 first sealing layer

First sealing layer of 802A etch-back

902 second sealing layer

902A etched back second encapsulation layer

1102. 1408 second self-aligned contact layer

1202 source/drain contact opening

1302 gate contact opening

1404. 1406 sealing layer

1410 spacer layer

1412 hydrogen plasma surface modification process

1414. 1514 surface modification layer

1414A, 1414B, 1414C, 1414D region

1416 fluorine plasma process

1420 etching byproduct layer

Detailed Description

The different embodiments or examples provided below may implement different configurations of the present invention. The following embodiments of specific components and arrangements are provided to simplify the present disclosure and not to limit the same. For example, the description of forming a first element on a second element includes embodiments in which the two are in direct contact, or embodiments in which the two are separated by additional elements other than direct contact. On the other hand, the same reference numbers may be repeated for various embodiments of the invention to simplify the description, but elements having the same reference numbers in various embodiments and/or arrangements do not necessarily have the same correspondence.

Furthermore, spatially relative terms such as "below," "lower," "above," "upper," or the like may be used for ease of description to refer to a relationship of one element to another in the figures. Spatially relative terms may be extended to elements used in other orientations than the orientation illustrated. The elements may also be rotated 90 or other angles, and directional terminology is used herein for purposes of illustration only.

It is noted that embodiments of the present invention relate to multi-gate transistors or fin-shaped multi-gate transistors, which may be referred to herein as finfet devices. Such a device may include a p-type metal oxide semiconductor fin field effect transistor device or an n-type metal oxide semiconductor fin field effect transistor device. The finfet device may be a double-gate device, a triple-gate device, a bulk device, a semiconductor-on-insulator device, and/or other arrangements. It should be understood by those skilled in the art that the embodiments of the present invention are also advantageous for other embodiments of semiconductor devices. For example, some embodiments described herein may also be used for fully-wrapped-gate devices, omega-gate devices, or Π -gate devices.

Fig. 1 shows a finfet device 100. Finfet device 100 includes one or more fin-based multi-gate field effect transistors. The finfet device 100 includes a substrate 102, at least one fin 104 extending from the substrate 102, an isolation region 106, and a gate structure 108 on the fin 104 and around the fin 104. The substrate 102 may be a semiconductor substrate such as a silicon substrate. The substrate may comprise a variety of layers including a conductive layer or an insulating layer formed on a semiconductor substrate. The substrate may comprise a variety of doping arrangements depending on design requirements known in the art. The substrate may also comprise other semiconductors such as germanium, silicon carbide, silicon germanium, or diamond. In other embodiments, the substrate may comprise a semiconductor compound and/or a semiconductor alloy. Furthermore, the substrate in some embodiments may comprise an epitaxial layer, may be stressed to enhance performance, may comprise a semiconductor-on-insulator structure, and/or may have other suitable enhancements.

The fin 104, such as the substrate 102, may comprise silicon or another semiconductor element such as germanium, a semiconductor compound (including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide), a semiconductor alloy (including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide phosphide, and/or indium gallium arsenide phosphide), or a combination thereof. The fins 104 may be fabricated by any suitable process, including photolithography and etching. The photolithography process may include forming a photoresist layer on a substrate (e.g., a silicon layer), exposing the photoresist to a pattern, performing a post-exposure baking process, and developing the photoresist to form a mask unit including the photoresist. In some embodiments, the method of patterning the photoresist to form the mask unit may employ an electron beam lithography process. The mask unit may then be used to protect some areas of the substrate while the etch process forms a recess into the silicon layer to leave the extended fins 104. The recess may be etched using dry etching (chemical oxide removal), wet etching, and/or other suitable processes. Other embodiments of the method may be used to form the fin 104 on the substrate 102.

Each of plurality of fins 104 may also include source region 105 and drain region 107, which may be formed in fin 104, on fin 104, and/or around fin 104. Source region 105 and drain 107 may be epitaxially grown on fin 104. The channel region of the transistor is located in fin 104 and under gate structure 108 and along a plane substantially parallel to section AA' of figure 1. In some examples, the channel region of the fin includes a high carrier mobility material such as germanium, one of any of the above semiconductor compounds or semiconductor alloys, and/or combinations thereof. High carrier mobility materials include materials with electron mobility greater than that of silicon. For example, the electron mobility of a high carrier mobility material is greater than the intrinsic electron mobility of silicon (about 1350cm2/V-s) and the hole mobility is greater than the hole mobility of silicon (about 480cm2/V-s) at room temperature (300K).

The isolation region 106 may be a shallow trench isolation structure. In other embodiments, a local silicon oxide structure and/or other suitable isolation structures may be implemented on and/or in the substrate 102. The isolation region 106 may be comprised of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass, a low-k dielectric layer, combinations thereof, and/or other suitable materials known in the art. In one embodiment, the isolation structure is a shallow trench isolation structure and may be formed by etching a trench in the substrate 102. Then, the trench is filled with an isolation material, and a chemical mechanical polishing process is performed. However, other embodiments are possible. In some embodiments, the isolation region 106 may include a multi-layer structure, such as having one or more liner layers.

The gate structure 108 includes a gate stack, which may include a gate dielectric layer 110 and a metal layer 112 formed on the gate dielectric layer 110. In some embodiments, gate dielectric layer 110 may include an interfacial layer formed on the channel region of fin 104 and a high-k dielectric layer on the interfacial layer. The interfacial layer of the gate dielectric layer 110 may comprise a dielectric material such as silicon oxide or silicon oxynitride. The high-k dielectric layer of the gate dielectric layer 110 may include hafnium oxide, titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium silicon oxide, combinations thereof, or other suitable materials. In other embodiments, the gate dielectric layer 110 may comprise silicon oxide or another suitable dielectric material. The gate dielectric layer 110 may be formed by chemical oxidation, thermal oxidation, atomic layer deposition, physical vapor deposition, chemical vapor deposition, and/or other suitable methods. The metal layer 112 may comprise a conductive layer such as tungsten, titanium nitride, tantalum nitride, tungsten nitride, rhenium, iridium, ruthenium, molybdenum, aluminum, copper, cobalt, nickel, combinations thereof, and/or other suitable compositions. In some embodiments, the metal layer 112 may include a first set of metal materials for n-type finfet transistors and a second set of metal materials for p-type finfet transistors. Finfet device 100 may include a dual work function metal gate arrangement. For example, a first metal layer (such as for an n-type device) may comprise a metal having a work function that is substantially aligned with the work function of the substrate conduction band, or at least substantially aligned with the work function of the channel region conduction band of fin 104. Likewise, the second metal material (e.g., for a p-type device) may comprise a metal having a work function substantially aligned with the work function of the substrate valence band, or at least substantially aligned with the work function of the channel region valence band of fin 104. The metal layer 112 may thus provide a gate for the finfet device 100, including both n-type and p-type finfet device 100. In some embodiments, metal layer 112 may instead comprise a polysilicon layer. The metal layer 112 may be formed by physical vapor deposition, chemical vapor deposition, electron beam evaporation, and/or other suitable processes. In some embodiments, sidewall spacers are formed on the sidewalls of the gate structure 108. The sidewall spacers may comprise a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or combinations thereof. As discussed above, significantly reducing the size of integrated circuits increases parasitic capacitance (e.g., between the gate of the finfet and the source/drain regions or source/drain contacts), and thus degrades device performance. In particular, the parasitic capacitance profile of the sidewall spacers has become a large portion of the total parasitic capacitance of the finfet device. To address this issue, air gap sidewall spacers may be introduced, such as replacing one or more dielectric materials used in existing sidewall spacers (e.g., formed on sidewalls of the gate structure 108). For clarity of illustration, these air gap sidewall spacers may be referred to simply as "air gap spacers". In various embodiments, the air gap spacers may provide a lower dielectric constant than dielectric materials used for existing sidewall spacers. Devices employing air gap spacers generally reduce parasitic capacitance and improve performance.

However, forming high quality air gap spacers remains challenging. For example, as part of the process of forming the air gap spacers, one or more sealing layers may be formed over the air gap adjacent to the gate spacers to seal the air gap spacers. In some examples, a porous low dielectric constant material (e.g., silicon oxycarbide) may serve as the sealing layer. In addition, a portion of the self-aligned contact process flow or the dual self-aligned contact etch process flow requires etching of a dielectric layer (e.g., silicon nitride, zirconium oxide, or other dielectric layer) to expose underlying contacts (e.g., source/drain or gate contacts) without damaging the previously formed sealing layer or adjacent air gap spacers. In other words, it is desirable to provide a process for etching a dielectric layer (e.g., silicon nitride, zirconium oxide, or the like) that has a high etch selectivity with respect to an air gap seal (e.g., a low-k material such as voids). For illustrative purposes, high etch selectivity is defined as a selectivity greater than or equal to about 12.

At least some existing dielectric layer etching processes, such as silicon nitride etching processes, do not achieve high etch selectivity of the dielectric layer relative to the low-k material of the via. For example, in some instances with existing chemistries for etching silicon nitride, the rate of etching low dielectric constant materials (e.g., silicon oxycarbide) for the holes may be too fast. For example, at least some existing chemistries for etching silicon nitride include methane fluoride and hydrogen, methane fluoride and oxygen, or methane fluoride and argon. Generally, etching plasmas using these etch chemistries etch low dielectric constant materials (e.g., silicon oxycarbide) that are porous, in addition to silicon nitride. Thus, the control margin for protecting the low dielectric constant material (e.g., silicon oxycarbide) of the via from etching by the silicon nitride etching plasma is narrow. Furthermore, since the sealing layer functions to seal air gaps, any loss of the sealing layer (such as loss of low dielectric constant material from voids) must be limited to within a few nanometers. If the seal layer is lost too much, the seal will be broken and the air gap will be damaged. In some instances, because of the low selectivity of silicon nitride to silicon oxycarbide in some conventional etching processes, the thickness of the dielectric layer (e.g., silicon nitride) and the porous low-k material (e.g., silicon oxycarbide) may need to be increased to ensure a sufficient device gate height. However, increasing the device gate height corresponds to increasing the aspect ratio, making the previous polysilicon etch and cleaning processes more difficult to perform, thereby creating etch residues, bending or collapsing the polysilicon lines, and generally degrading device performance. In addition, the subsequent chemical mechanical polishing process may require additional polishing depth to achieve proper device planarity. In some instances, these additional CMP and associated layer loss may effectively reduce gate height. Generally, as technology continues to advance, smaller critical dimensions and higher aspect ratios do not allow for the existing process tolerances for low etch selectivity (e.g., low etch selectivity for silicon nitride versus silicon oxycarbide) while maintaining the desired gate height. The prior art does not fully meet all of these needs.

Embodiments of the invention provide many more advantages than the prior art, but it is understood that other embodiments may provide different advantages, all of which need not be described herein, and all of which need not have a particular advantage. For example, embodiments described herein include structures and methods for providing air gap spacers (e.g., protected with a multi-layer encapsulant material) that may reduce the dielectric constant of the spacers and improve device performance. In particular, the embodiments described herein provide methods for forming high quality air gap spacers, which may be part of a dual self-contact process flow, as described in more detail below. In some embodiments, a first encapsulation layer and a second encapsulation layer may be formed over the air gaps adjacent to the device gate structure to seal the air gap spacers. A sealing layer may be incorporated over the air gap to provide a sealed air gap spacer. As described above, a porous low dielectric constant material (e.g., silicon oxycarbide) may be used to form the first and/or second sealing layers. In addition, embodiments of the present invention, as part of a dual self-contact process flow, may provide a process for etching a dielectric layer (e.g., silicon nitride, zirconium oxide, or the like) with a high (e.g., greater than 12) etch selectivity of the dielectric layer with respect to a first and second air gap sealing layer (e.g., silicon oxycarbide). Thus, various embodiments avoid exposing and/or damaging the air gap and minimize gate height loss.

In some embodiments, the high etch selectivity etch process employs a hydrogen modified atomic layer etch process to improve etch selectivity. Generally, an atomic layer etch process may be used to accurately remove an atomic layer of material and comprises a series of steps alternating between a self-limiting chemical surface modification step and an etch step that removes a chemically modified surface region. By providing such a self-limiting surface modification and etching step, the atomic layer etching process can provide more accurate etch control and etch selectivity than the reactive ion etching process. In various embodiments described herein, a hydrogen-modified atomic layer etch silicon nitride etch process may be used to improve the etch selectivity of silicon nitride relative to silicon oxycarbide. For example, the etching process of atomic layer etching consists of two steps: (1) modifying the surface of the silicon nitride and silicon oxycarbide surface by hydrogen plasma; and (2) removing the surface modification layer on the silicon nitride by fluorine radical etching and leaving the surface modification layer on the silicon oxycarbide surface (which may be referred to as an etch stop layer). In some examples, the cleaning step may be performed after the surface modification, the etching step, or both. In some examples, the removal process of the atomic layer etch may provide a high etch selectivity of the self-aligned contact material (e.g., silicon nitride) relative to the low-k spacer material of the via (e.g., silicon oxycarbide), thereby providing a wider etch process window in the dual self-aligned contact etch process. In addition, various embodiments may be processed at higher pressures to achieve high etch selectivity (e.g., greater than 25) for the sealing layer of zirconia relative to silicon oxycarbide and silicon nitride. In some instances, the higher pressure facilitates removal of the sidewall step because the additional boron can form volatile zirconium oxychloride and remove the step of the zirconium oxide.

In addition, the silicon nitride etching process (with high etching selectivity) of the present invention is stopped on the zirconia, which can enhance and enlarge the process tolerance of the dual self-aligned contact etching. Thus, some embodiments may reduce the self-aligned contact silicon nitride layer height, thereby reducing the total gate height required for the front-end etch and/or polysilicon cleaning process and providing wider etch process control. In many cases, the etch selectivity of silicon nitride in atomic layer etching makes silicon nitride a good self-aligned contact material in the silicon nitride etch process for dual self-aligned contacts and the breakdown etch process for silicon nitride. In addition, the high etch selectivity of silicon nitride relative to the sealing layer (e.g., silicon oxycarbide) helps to ensure that the sealing layer does not break during the process of etching the self-aligned contact and to ensure that the air gap spacers are not damaged. In addition, the high etch selectivity of silicon nitride to the low dielectric constant silicon oxycarbide sealing layer of the via also reduces the silicon nitride height requirement of the self-aligned contact, resulting in a reduction in the overall gate height and aspect ratio. In some embodiments, an atomic layer etch silicon nitride etch process provides silicon nitride with high etch selectivity relative to the zirconium oxide material of the self-aligned contact and widens the tolerance of the dual self-aligned contact etch process. Various embodiments provide lower gate height requirements, improve process margins for front-end etching and polysilicon cleaning, reduce etch residues, and reduce polysilicon line collapse and bowing problems, thereby providing greater etch process margins during middle-end etching. Therefore, the yield can be effectively improved. Additional embodiments and advantages will be described below and/or will be apparent to those skilled in the art from the description of the embodiments.

Fig. 2 illustrates, in one or more embodiments, a method 200 of fabricating a semiconductor device (e.g., a finfet device) including air gap spacers, such as part of a dual self-aligned contact etch process flow. In some embodiments, the method 200 may be used to fabricate the finfet device 100 described above in conjunction with the description of fig. 1. One or more embodiments of the finfet device 100 described above may also be used in the method 200. In addition, fig. 3-13 provide cross-sectional views along planes substantially parallel to the section AA' of fig. 1 of an exemplary device 300 fabricated according to one or more steps of the method 200 of fig. 2.

It is understood that portions of the method 200 and/or the apparatus 300 for fabricating a semiconductor may be performed by well-known cmos process flows, and therefore only some of the processes are briefly described herein. Also as noted above, the device 300 may share portions of the finfet device 100, and thus only portions of the device 300 and/or the fabrication process are briefly described for clarity. In addition, the device 300 may include various other devices and structures, such as additional transistors, bjts, resistors, capacitors, diodes, fuses, or the like, although the drawings have been simplified to facilitate understanding of the inventive concepts of the present embodiments. In addition, the device 300 in some embodiments includes a plurality of semiconductor devices (e.g., transistors) that may be interconnected with one another.

In various embodiments, the device 300 may be an intermediate device fabricated as an integrated circuit or portion thereof, which may include static random access memory and/or other logic circuitry, passive components (e.g., resistors, capacitors, or inductors), or active components (e.g., p-channel field effect transistors, n-channel field effect transistors, metal oxide semiconductor field effect transistors, high voltage transistors, high frequency transistors, or other memory cells), and/or combinations thereof.

A beginning step 202 of the method 200 provides a finfet device that includes source/drain metal contact layers. As shown in fig. 3, an embodiment of step 202 provides a finfet device 300 that includes a fin 302 extending from a substrate and a gate stack including a gate dielectric layer 304 and a metal layer 306 over the gate dielectric layer 304. In some embodiments, the substrate, fin 302, gate dielectric layer 304, and metal layer 306 may be substantially similar to substrate 102, fin 104, gate dielectric layer 110, and metal layer 112 described above in conjunction with figure 1. In some examples, the height H1 of the metal layer 306 is between about 30nm and 40 nm. The device 300 also includes a first spacer layer 308 and a second spacer layer 310 formed on sidewalls of the gate stack. In some embodiments, the first spacer layer 308 and the second spacer layer 310 may comprise a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, or combinations thereof.

In some embodiments, the device 300 includes an epitaxial source/drain structure 312 formed by one or more epitaxial processes. In some examples, epitaxial source/drain structures 312 may be formed in fin 302, on fin 302, and/or around fin 302. In various examples, a silicide layer 314 may be formed on the epitaxial source/drain structures 312 to reduce contact resistance. In some embodiments, the silicide layer 314 may comprise cobalt silicide, nickel silicide, or titanium silicide. In addition, some embodiments may form a metal contact layer 316 on the silicide layer 314 to provide electrical connection to the epitaxial source/drain structures 312. In at least some examples, metal contact layer 316 comprises a cobalt layer, although other suitable metals may be used without departing from the scope of embodiments of the present invention. In some embodiments, the liner layer 318 is formed on the sidewalls of the metal contact layer 316, such that the liner layer 318 is sandwiched between the second spacer layer 310 and the metal contact layer 316. In some examples, the liner layer 318 may be formed prior to forming the metal contact layer 316. In some embodiments, liner layer 318 comprises a silicon nitride layer. For example, the device 300 may also include a first self-aligned contact layer 320 formed on the gate stack, the first spacer layer 308, and the second spacer layer 310. In some examples, the first self-aligned contact layer 320 includes a dielectric layer such as a zirconium oxide layer.

The method 200 continues with block 204 in which a chemical mechanical polishing process is performed after the formation of the source/drain metal contact layer (block 202). Taking fig. 3 and 4 as an example, one embodiment of step 204 may perform a cmp process 402 to remove portions of the first self-aligned contact layer 320 and the metal contact layer 316 and planarize the top surface of the device 300.

After the CMP process (step 204), step 206 of the method 200 performs an etch back process and a selective deposition process. As shown in fig. 5, an embodiment of step 206 may perform an etch-back metal process to etch back the metal contact layer 316, thereby providing an etched-back metal contact layer 316A. In some embodiments where the metal contact layer 316 comprises cobalt, the process of etching back the metal comprises a process of etching back cobalt. In various examples, the process of etching back the metal includes wet etching, dry etching, or a combination thereof. After the metal etch-back process, other embodiments of step 206 may selectively deposit a metal layer 502 on the etched-back metal contact layer 316A. In some embodiments, metal layer 502 comprises tungsten, although other suitable metals may be used. In various embodiments, the selective deposition of the metal layer 502 may employ chemical vapor deposition, atomic layer deposition, physical vapor deposition, or other suitable methods.

The method 200 continues with step 208 in which the sidewall etch back process is performed. As shown in fig. 5 and 6, an embodiment of step 208 performs a sidewall etch back process. In some embodiments, an etch back sidewall process may be employed to etch back the second sidewall spacer layer 310 and the liner layer 318, thereby providing an etched back second spacer layer 310A and an etched back liner layer 318A. In some examples, the process of etching back the sidewalls may include wet etching, dry etching, or a combination thereof. Additionally, some embodiments of the sidewall etching process may include an isotropic sidewall etching process.

After the process of etching back the sidewalls (step 208), step 210 of the method 200 removes the sidewall spacer layer. As shown in fig. 6 and 7, one embodiment of step 210 may remove the etched-back second spacer layer 310A to form air gaps 702. In some embodiments, the removal method of the etched-back second spacer layer 310A may be dry etching, wet etching, or a combination thereof. As described above, the second spacer layer 310 may comprise an insulating layer (dielectric layer) such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, or combinations thereof. The air gaps 702 of some embodiments may sometimes be referred to as a sacrificial insulating air gap, as the second spacer layer 310 is removed (or discarded) to form the air gaps 702.

Step 212 of method 200 deposits a first sealing layer over the air gaps. One embodiment of step 212 deposits a first sealing layer 802 over the air gaps 702, as shown in fig. 7 and 8. In some embodiments, the first sealing layer 802 is conformably deposited and draped and/or incorporated on top of the air gap 702 to form a sealed and unexposed air gap spacer 702A. The air gap 702 may be formed by removing the second spacer layer 310 (step 210). The air gap spacers 702A protected by the multi-layer encapsulant may therefore reduce the dielectric constant of the spacers and improve the performance of the device 300. In some examples, the height H2 of air gap spacer 702A is between about 25nm to about 35nm and the width W1 is between about 3nm to 4 nm. In some embodiments, the thickness T1 of the first sealing layer 802 is between about 3nm to 20 nm. In various embodiments, the first sealing layer 802 may comprise a porous low dielectric constant material such as silicon oxycarbide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, or combinations thereof. Specifically, the first sealing layer 802 of some embodiments may include silicon oxycarbide or silicon oxycarbonitride with a carbon content between about 2% and 10%. In some embodiments, the first encapsulation layer 802 may be deposited using atomic layer deposition, plasma assisted atomic layer deposition, chemical vapor deposition, plasma assisted chemical vapor deposition, or other suitable methods. For example, the deposition temperature of the first sealing layer 802 may be between about 250 ℃ to 650 ℃.

Step 214 of method 200 deposits a second encapsulation layer over the first encapsulation layer. As shown in fig. 8 and 9, one embodiment of step 214 deposits a second encapsulant layer 902 over the first encapsulant layer 802. In some embodiments, the second sealing layer 902 is conformably deposited over the first sealing layer 802. In some embodiments, the thickness T2 of the second encapsulation layer 902 is between about 8nm to 10 nm. Similar to the first sealing layer 802, the second sealing layer 902 may include a porous low dielectric constant material such as silicon oxycarbide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, or combinations thereof. Specifically, the second sealing layer 902 of some embodiments may include silicon oxycarbide or silicon oxycarbonitride with a carbon content between about 10% and 20%. In various examples, the carbon content of second sealing layer 902 is higher than the carbon content of first sealing layer 802. For example, increasing the carbon content of the sealing layer (e.g., the second sealing layer 902) may increase the sealing layer's resistance to subsequent plasma etching processes. On the other hand, reducing the carbon content in the sealing layer (e.g., first sealing layer 802), the first sealing layer 802 may preferably be controlled to effectively overhang and/or merge on top of the air gap 702 to form a sealed air gap spacer 702A. In some embodiments, the deposition of second encapsulation layer 902 may employ similar atomic layer deposition, plasma assisted atomic layer deposition, chemical vapor deposition, plasma assisted chemical vapor deposition, or other suitable methods. For example, the deposition temperature of the second encapsulant layer 902 may be between about 250 ℃ to 650 ℃. In various embodiments, due to the increased carbon content of the second encapsulant layer 902, good plasma resistance, such as plasma resistance to subsequent self-aligned contact etching, may be provided. In addition, the ratio of the thicknesses of the first sealing layer 802 and the second sealing layer 902 of some embodiments is between about 1 and 3, depending on the surface topography of the device 300.

After depositing the second encapsulant layer (step 214), step 216 of the method 200 performs a process of etching back the encapsulant layer. As shown in fig. 9 and 10, one embodiment of step 216 employs a process of etching back the sealant layer to etch back the first sealant layer 802 and the second sealant layer 902 to provide an etched back first sealant layer 802A and an etched back second sealant layer 902A. In some examples, the process of etching back the sealing layer may include wet etching, dry etching, or a combination thereof. In some embodiments, the process of etching back the sealing layer exposes the upper surfaces of the first self-aligned contact layer 320 and the metal layer 502. It is noted, however, that even after the process of etching back the sealing layer, the air gap spacers 702A remain sealed and unexposed.

The method 200 continues with step 218 in which a dielectric layer is deposited and a chemical mechanical polishing process is performed. As shown in fig. 10 and 11, one embodiment of step 218 may deposit a dielectric layer on the device 300 and may perform a chemical mechanical polishing process to remove excess portions of the dielectric layer and planarize the top surface of the device 300. In some embodiments, the dielectric layer may be referred to as a second self-aligned contact layer 1102. For example, the second self-aligned contact layer 1102 may include a silicon nitride layer. In some examples, the deposition method of the second self-aligned contact layer 1102 may be atomic layer deposition, chemical vapor deposition, physical vapor deposition, or another suitable method.

After the deposition and CMP processes of step 218, step 220 of the method 200 performs a first etch process and a second etch process. In various embodiments, the first etching process and the second etching process may include a first process of etching a self-aligned contact and a second process of etching a self-aligned contact. As shown in fig. 11 and 12, one embodiment of step 220 may perform a first etch self-aligned contact process that targets source/drain regions of device 300 (e.g., a process performed on epitaxial source/drain structure 312). Specifically, a first etch self-aligned contact process may be used to etch a second etch self-aligned contact 1102 previously deposited on the exposed metal layer 502 to form a source/drain contact opening 1202. In various embodiments, the first process for etching the self-aligned contact may comprise an atomic layer etch process that provides a high etch selectivity (e.g., greater than 12) of the second self-aligned contact layer 1102 (e.g., silicon nitride) relative to the etched-back first sealant layer 802A, the etched-back second sealant layer 902A, and the first self-aligned contact layer 320 (e.g., zirconium oxide). The first process of etching the self-aligned contact can thus improve the etch selectivity of silicon nitride to low-k spacer material (e.g., silicon oxycarbide) of the via. Due to the high etch selectivity of silicon nitride relative to the sealing layer (e.g., silicon oxycarbide), the first etch self-aligned contact process does not etch or damage the etched-back first sealing layer 802A and the etched-back second sealing layer 902A, and thus the undamaged air gap spacers 702A remain sealed and unexposed. In addition, the first self-aligned contact etch process does not cause lateral damage, bending, or damage to the etched-back metal contact layer 316A (e.g., cobalt) or the selectively deposited metal layer 502 (e.g., tungsten). Additional details regarding the etching process of the atomic layer etching will be described below in conjunction with fig. 14A-14D and fig. 15A-15D. Various embodiments may deposit a metal layer in the source/drain contact openings 1202 to contact the metal layer 502 after forming the source/drain contact openings 1202, thereby providing electrical connection to the epitaxial source/drain structures 312.

As shown in fig. 11 and 13, other embodiments of step 220 may perform a second process of etching self-aligned contacts to target gate regions of device 300 (e.g., gate regions on a gate stack including a gate dielectric layer 304 and a metal layer 306). Specifically, a second process of etching a self-aligned contact may be used to etch the first self-aligned contact layer 320 (e.g., zirconia) formed on the gate stack prior to forming the gate contact opening 1302. In various embodiments, the second process for etching the self-aligned contact may also include an atomic layer etching process to provide a high etch selectivity (e.g., greater than 12) of the first self-aligned contact layer 320 (e.g., zirconia) relative to the etched-back first sealant layer 802A, the etched-back second sealant layer 902A, and the second self-aligned contact layer 1102 (e.g., silicon nitride). The second process of etching the self-aligned contact can thus improve the etch selectivity of the zirconia relative to the low dielectric constant spacer material (e.g., silicon oxycarbide) of the via. The high etch selectivity of the zirconium oxide relative to the sealing layer (e.g., silicon oxycarbide) results in the second etched self-aligned contact process not damaging the etched-back first sealing layer 802A and the etched-back second sealing layer 902A, and thus the air-gap spacers 702A remain sealed and unexposed without damage. In addition, the second self-aligned contact etching process does not cause lateral damage, bowing, or damage to the metal layer 306 or any adjacent liner layer (e.g., TiN). In various embodiments, after forming the gate contact opening 1302, a metal layer may be deposited in the gate contact opening 1302 to contact the metal layer 306, thereby providing an electrical connection to the gate stack of the device 300. In some embodiments, the process of etching the first self-aligned contact may be performed before the process of etching the second self-aligned contact is performed. However, some examples may include etching the second self-aligned contact before etching the first self-aligned contact.

Subsequent processing of the device 300 may be performed to form various structures and regions as is known in the art. For example, subsequent processing may form various contacts, vias, and/or lines and multilevel interconnect structures (e.g., metal layers and interlevel dielectric layers) on the substrate that are configured to connect various structures to form a functional circuit containing one or more finfet devices. In other examples, the multilevel interconnects may include vertical interconnects such as vias or contacts, and horizontal interconnects such as metal lines. Various interconnect structures may employ various conductive materials including copper, tungsten, and/or silicides. In one example, a damascene process and/or a dual damascene process may be used to form a copper-related multilevel interconnect structure.

FIGS. 14A-14D and 15A-15D illustrate exemplary atomic layer etch process flows. For example, the first process of etching self-aligned contacts and/or the second process of etching self-aligned contacts may be employed at step 220 of method 200. In some embodiments, fig. 14A-14D show a first cycle of an exemplary atomic layer etch process flow, and fig. 15A-15D show second-nth cycles of the exemplary atomic layer etch process flow. In general, repeated cycles of the atomic layer etch process may partially achieve high etch selectivity of silicon nitride or zirconium oxide relative to low dielectric constant spacer materials (e.g., silicon oxycarbide). In addition, although the following example described in conjunction with fig. 14A-14D and fig. 15A-15D is a first self-aligned contact etch process for etching a second self-aligned contact layer (e.g., silicon nitride) over a source/drain region, a similar atomic layer etch process may also be used to etch the first self-aligned contact layer (e.g., zirconium oxide) over a gate stack to form a second self-aligned contact for a gate contact opening (e.g., gate contact opening 1302). However, a hydrogen and fluorine plasma process is used to etch silicon nitride as follows. Different etch chemistries may be used when etching zirconia using an atomic layer etch process. For example, some embodiments may etch zirconia using a boron trichloride and/or chlorine based plasma.

The apparatus 1400 shown in FIG. 14A may be substantially the same as the apparatus 300 described above. Thus, in some embodiments, the device 1400 includes a first self-aligned contact layer 1402, which may be substantially identical to the first self-aligned contact layer 320 of the device 300. As such, the first self-aligned contact layer 1402 may include a dielectric layer such as a zirconium oxide layer. The apparatus 1400 further comprises sealing layers 1404 and 1406 that are substantially identical to the etched-back first sealing layer 802A and the etched-back second sealing layer 902A of the apparatus 300, respectively, such that the sealing layers 1404 and 1406 in various examples may comprise porous low-k materials, such as silicon oxycarbide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, or combinations thereof. In some embodiments, the device 1400 may also include a second self-aligned contact layer 1408, which may be substantially the same as the second self-aligned contact layer 1102 of the device 300. Thus, in various examples, the second self-aligned contact layer 1408 may comprise a silicon nitride layer. Device 1400 may also include a spacer layer 1410, which may be substantially the same as first spacer layer 308 of device 300. Thus, the spacer layer 1410 in various examples may comprise a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, or combinations thereof.

In the first step of the atomic layer etch process flow, a hydrogen plasma surface modification process 1412 (fig. 14A) may be performed, which may employ a hydrogen plasma to form a surface modification 1414 (fig. 14B). As shown, the surface modification layer 1414 may be comprised of different regions 1414A, 1414B, 1414C, and 1414D, defined by the materials of the upper surface of the device 1400 that are exposed to and react with the hydrogen plasma of the hydrogen plasma surface modification process 1412. In this example, region 1414A corresponds to first self-aligned contact layer 1402, region 1414B corresponds to spacer layer 1410, region 1414C corresponds to second self-aligned contact layer 1408, and region 1414D corresponds to sealing layers 1404 and 1406.

In some embodiments, the excited hydrogen gas is exposed to the nitrogen of the silicon nitride layer (e.g., the silicon nitride layer of the second self-aligned contact layer 1408), which may form ammonia by-products in the surface modification layer 1414 and weaken the bonds in the silicon nitride layer. For example, as the attraction of hydrogen-nitrogen bonds pulls nitrogen atoms away from silicon atoms, silicon-nitrogen bond length (such as in a silicon nitride layer) may be increased and silicon-nitrogen bond energy may be decreased to increase the etch rate during a subsequent fluorine plasma process, as described below. In some embodiments, the depth and/or thickness of surface modifying layer 1414 is at least partially dependent on the gas and plasma power used to form the plasma. In the case of a hydrogen plasma, the thickness T3 of surface modifying layer 1414 may be adjusted to be between about 7nm and 20nm, depending on the underlying material layer. In various examples, the hydrogen plasma penetrates to a greater depth than the argon plasma or the helium plasma. In particular, a higher power and lower plasma pressure hydrogen plasma may provide a deeper upgrading depth (compared to an argon plasma or a helium plasma). As described above, the thickness of the surface modified layer 1414 in the different regions 1414A, 1414B, 1414C, and 1414D may be different to correspond to different underlying material layers. In some examples, the thickness of the surface modification layer 1414 in the region 1414C is greater than the thickness of the surface modification layer 1414 in the regions 14144a, 1414B, and 1414D. The thickness of the surface modification layer 1414 in the regions 1414B and 1414D is greater than the thickness of the surface modification layer 1414 in the region 1414A.

In the second step of the atomic layer etch process flow, a fluorine plasma process may be performed to remove the surface modification layer 1414 in the region 1414C (e.g., to remove the surface modification layer 1414 from the silicon nitride layer of the second self-aligned contact layer 1408), and to leave the surface modification layer 1414 on the other regions 1414A, 1414B, and 1414D (e.g., on the zirconia surface of the first self-aligned contact layer 1402 and on the silicon oxycarbide surfaces of the sealing layers 1404 and 1406), as shown in fig. 14C and 14D. In some embodiments, the fluorine plasma process 1416 includes a fluorine radical etch to remove the surface modification layer 1414. For example, fig. 14C shows a fluorine radical reaction, and fig. 14D shows a post etch reaction, wherein the fluorine plasma process 1416 is followed by removal of additional silicon nitride (e.g., silicon nitride of the second self-aligned contact layer 1408). In some embodiments, the fluorine plasma process 1416 facilitates the formation of volatile hydrogen cyanide byproducts that may be used to remove silicon nitride layers. On the other hand, surface modification layer 1414 on silicon oxycarbide (e.g., sealing layers 1404 and 1406) may act as an etch stop layer, in part because of the formation of hydrogen-assisted surface polymers and the strong silicon-oxygen bonds. Generally, the atomic layer etching process flow provides a higher silicon nitride etching rate due to the synergy of the hydrogen plasma surface modification process 1412 and the fluorine plasma process 1416 performed in sequence. In various examples, the higher hydrogen dose in surface modification layer 1414 may help to enhance and/or strengthen the silicon oxycarbide (e.g., silicon oxycarbide of sealing layers 1404 and 1406) and resist etching by fluorine plasma process 1416.

Fig. 14C also shows the etch byproduct layer 1420 formed during the fluorine plasma process 1416. As shown, the etch byproduct layer 1420 formed on the upper surfaces of the first self-aligned contact layer 1402 and the sealing layers 1404 and 1406 may be thicker than the etch byproduct layer 1420 formed on the second self-aligned contact layer 1408, since hydrogen plasma modification (e.g., the hydrogen plasma surface modification process 1412) may form a weaker silicon-nitrogen bond and may remove a silicon nitride layer more easily for the second self-aligned contact layer 1408. In some examples, as shown in fig. 14D, the silicon nitride with lower surface passivation protection (e.g., the silicon nitride of the second self-aligned contact layer 1408) is removed, and the first self-aligned contact layer 1402 and the sealing layers 1404 and 1406 are protected by the thicker etch byproduct layer 1420. As a result, the etch selectivity of second self-aligned contact layer 1408 with respect to first self-aligned contact layer 1402 and sealing layers 1404 and 1406 can be improved. In some embodiments, the etch byproduct layer 1420 may be removed from the surface of the device 1400 during a subsequent wet cleaning process (e.g., a wet cleaning process after removing the silicon nitride layer). It is noted that in some instances where spacer layer 1410 comprises silicon nitride (similar to second self-aligned contact layer 1408), due in part to the small critical dimension of the exposed portions of the spacer layer (as compared to the adjacent layers), spacer layer 1410 remains largely unetched, and adjacent first self-aligned contact layer 1402 and sealing layers 1404 and 1406 substantially protect spacer layer 1410, which may provide a high etch selectivity for second self-aligned contact layer 1408 during an atomic layer etch process.

After the first cycle of the atomic layer etching process flow (as described above with reference to fig. 14A to 14D), the second to nth cycles of the atomic layer etching process flow may be performed, as shown in fig. 15A to 15D. As described above, repeating the etching process cycle of the atomic layer etching partially achieves a high etch selectivity of silicon nitride or zirconium oxide with respect to the low dielectric constant spacer material (e.g., silicon oxycarbide) of the via. As shown in fig. 15A, the hydrogen plasma surface modification process 1412 may be performed once more, such as by treating the surface of the silicon nitride and silicon oxycarbide with hydrogen plasma to form an additional surface modification layer 1514 (see fig. 15B), and/or to enlarge the surface modification layer 1414 that existed before. It is noted that in some embodiments, the surface modification layer 1514 may also be comprised of different regions, which may be similar to the different regions of the surface modification layer 1414 described above. After forming the additional surface modification layer 1514 or expanding the pre-existing surface modification layer 1414, a fluorine plasma process 1416 may be performed to remove the surface modification layer 1514 from the silicon nitride layer (e.g., the silicon nitride layer of the second self-aligned contact layer 1408) and leave the surface modification layer 1514 and/or the surface modification layer 1414 on other regions of the device 1400 (including the silicon oxycarbide surfaces of the sealing layers 1404 and 1406 and the zirconium oxide surface of the first self-aligned contact layer 1402), as shown in fig. 15C and 15D. Specifically, fig. 15C illustrates a fluorine radical reaction, and fig. 15 illustrates a post etch reaction, wherein the fluorine plasma process 1416 may be followed by removal of additional silicon nitride (e.g., silicon nitride of the second self-aligned contact layer 1408). The atomic layer etch process flow illustrated in fig. 15A-15D may then be repeated for N cycles as needed to completely etch the silicon nitride layer (e.g., silicon nitride of the second self-aligned contact layer 1408) and expose the underlying metal layer (e.g., metal layer 502) to form source/drain contact openings (e.g., source/drain contact openings 1202).

In other words, as shown in fig. 15A-15D, the hydrogen plasma surface modification process 1412 and the fluorine plasma process 1416 may be repeated to remove the silicon nitride layer, and the critical process control includes maintaining a thicker surface modification layer (e.g., surface modification layers 1514 and/or 1414) on the first self-aligned contact layer 1402 and the sealing layers 1404 and 1406, and removing the thinner surface modification layer on the second self-aligned contact layer 1408 to etch the second self-aligned contact layer 1408. Optimizing control of the passivation layer (e.g., controlling the surface modification layer) may further improve the etch selectivity of the second self-aligned contact layer 1408 with respect to the first self-aligned contact layer 1402 and the sealing layers 1404 and 1406. As shown in fig. 15A-15D, the etch byproduct layer 1420 may be removed from the surface of the device 1400 during a subsequent wet cleaning process (e.g., a wet cleaning process after removing the silicon nitride layer).

The various embodiments described herein may therefore provide various advantages over the prior art. It is to be understood that not necessarily all advantages will be described herein, that not necessarily all embodiments may have a particular advantage, and that other embodiments may provide different advantages. For example, embodiments described herein include methods and structures for providing air gap spacers with multiple encapsulation layers to protect the air gap spacers, which may reduce the dielectric constant of the spacers and improve device performance. In some embodiments, a first encapsulation layer and a second encapsulation layer may be formed over the air gaps adjacent to the device gate structure to seal the air gap spacers. In some examples, a porous low dielectric constant material (e.g., silicon oxycarbide) may be used to form the plurality of sealing layers. In addition, embodiments of the present invention provide an etch process (e.g., an atomic layer etch process) for a dielectric layer (e.g., silicon nitride, zirconium oxide, or the like) having a high etch selectivity (e.g., greater than 12) relative to a plurality of sealing layers (e.g., silicon oxycarbide) as part of a dual self-aligned contact etch process flow. Thus, various embodiments of the present invention may avoid exposing and/or damaging the air gap and minimize gate height loss. Additional embodiments and advantages will be apparent to those skilled in the art from consideration of the specification.

Thus, one illustrative method of forming a semiconductor device according to embodiments of the present invention includes providing a device including a gate stack, a plurality of spacer layers on sidewalls of the gate stack, and a source/drain structure adjacent the gate stack. In some embodiments, a first spacer layer of the spacer layers is removed to form air gaps on sidewalls of the gate stack. In various embodiments, a first sealing layer is then deposited on top of the air gap to form a sealed air gap. A first etching process is then used to etch the first self-aligned contact layer from the source/drain structure. In various embodiments, the first etch process selectively etches the first self-aligned contact layer while the first sealing layer remains unetched.

In some embodiments, the method further comprises: depositing a second sealing layer on the first sealing layer; and etching the first self-aligned contact layer from the source/drain structure using a first etching process, wherein the first etching process selectively etches the first self-aligned contact layer while the second sealing layer remains unetched.

In some embodiments, the first etch process is an atomic layer etch process comprising (i) a hydrogen plasma process that forms a surface modification layer on and reacts with the first self-aligned contact layer; and (ii) a fluorine plasma process to remove the surface modification layer from the first self-aligned contact layer and to remove at least a portion of the first self-aligned contact layer, wherein the hydrogen plasma process and the fluorine plasma process are repeated for N cycles to remove the first self-aligned contact layer from the source/drain structure.

In some embodiments, the device further comprises a metal contact layer formed on the source/drain structure and providing an electrical contact to the source/drain structure, and the method further comprises: performing an etch-back process on the metal contact layer to form an etched-back metal contact layer; and forming a selectively deposited metal layer on the etched back metal contact layer.

In some embodiments, the metal contact layer comprises cobalt and the selectively deposited metal layer comprises tungsten.

In some embodiments, the method further comprises performing an etch back process on the first spacer layer prior to removing the first spacer layer.

In some embodiments, the method further comprises: performing an etch-back process of the sealing layer to expose an upper surface of the selectively deposited metal layer before etching the first self-aligned contact layer from the source/drain structure; and depositing a first self-aligned contact layer on the source/drain structure.

In some embodiments, the device further comprises a second self-aligned contact layer on the gate stack, and the method further comprises: a second self-aligned contact layer is etched from the gate stack using a second etch process, wherein the second etch process selectively etches the second self-aligned contact layer while the first sealing layer remains unetched.

In some embodiments, the first self-aligned contact layer comprises silicon nitride and the second self-aligned contact layer comprises zirconium oxide.

In some embodiments, the first sealing layer and the second sealing layer comprise a porous low dielectric constant material.

In some embodiments, the low dielectric constant material of the hole comprises silicon oxycarbide.

In some embodiments, the etch selectivity of the first self-aligned contact layer relative to the first encapsulation layer is greater than 12.

In another embodiment, a method of forming a semiconductor device includes: the spacer layer is removed from the sidewalls of the finfet gate stack to form air gaps on the sidewalls of the finfet gate stack. In some embodiments, a plurality of sealing layers are conformably deposited on top of the air gap to form a sealed air gap. In some examples, a first atomic layer etch process is performed to remove a silicon nitride layer from source/drain regions adjacent to a finfet gate stack. The first atomic layer etching process selectively etches the silicon nitride layer while the sealing layer remains unetched.

In some embodiments, the first atomic layer etching process includes (i) a hydrogen plasma process that forms a surface modification layer on and reacts with the silicon nitride layer; and (ii) a fluorine plasma process for removing the surface modified layer from the silicon nitride layer and removing at least a portion of the silicon nitride layer, wherein the hydrogen plasma process and the fluorine plasma process are repeated for N cycles to remove the silicon nitride layer from the source/drain.

In some embodiments, the method further comprises: before forming the air gap, a selectively deposited tungsten layer is formed on the cobalt layer, wherein the cobalt layer is deposited on the source/drain and provides an electrical contact to the source/drain.

In some embodiments, the method further comprises depositing a silicon nitride layer on the selectively deposited tungsten layer prior to performing the first atomic layer etch process.

In some embodiments, the method further comprises: a second atomic layer etching process is performed to remove the zirconium oxide layer from the finfet gate stack, wherein the second atomic layer etching process selectively etches the zirconium oxide layer while the sealing layer remains unetched.

In some embodiments, one or more of the sealing layers comprises silicon oxycarbide.

In yet another embodiment, a semiconductor device includes: a gate stack on the first fin region, wherein a spacer layer is on a first sidewall of the gate stack. In some embodiments, the source/drain contact metal is on a second fin region adjacent to the first fin region, wherein the second fin region includes a source/drain structure, wherein the liner layer is on a second sidewall of the source/drain contact metal, and wherein the first sidewall and the second sidewall are opposite each other. In some examples, an air gap spacer located between the spacer layer and the liner layer; and a plurality of sealing layers incorporated on top of the air gap spacers to seal and protect the air gap spacers.

In some embodiments, the gate stack includes a metal layer having a height between about 30nm and 40nm, the air gap spacer has a height between about 25nm and 35nm, and the sealing layer has a thickness between about 5nm and 10 nm.

The features of the above-described embodiments are helpful to those skilled in the art in understanding the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It should also be understood by those skilled in the art that these equivalent substitutions and alterations can be made without departing from the spirit and scope of the present invention, and that these changes, substitutions and alterations can be made without departing from the spirit and scope of the present invention.