Method for manufacturing semiconductor device
阅读说明:本技术 制造半导体装置的方法 (Method for manufacturing semiconductor device ) 是由 金熙中 李基硕 金根楠 黄有商 于 2019-06-24 设计创作,主要内容包括:公开了制造半导体装置的方法。所述方法包括:在基底上交替地堆叠多个介电层和多个第一半导体层以形成模结构;形成穿透模结构的孔;在基底上形成填充孔的第二半导体层;以及将激光照射到第二半导体层上。(A method of manufacturing a semiconductor device is disclosed. The method comprises the following steps: alternately stacking a plurality of dielectric layers and a plurality of first semiconductor layers on a substrate to form a mold structure; forming a hole penetrating the mold structure; forming a second semiconductor layer filling the hole on the substrate; and irradiating laser light onto the second semiconductor layer.)
1. A method of fabricating a semiconductor device, the method comprising:
alternately stacking a plurality of dielectric layers and a plurality of first semiconductor layers on a substrate to form a mold structure;
forming a hole penetrating the mold structure;
forming a second semiconductor layer filling the hole on the substrate; and
laser light is irradiated onto the second semiconductor layer.
2. The method of claim 1, wherein the step of forming the holes exposes a top surface of the substrate.
3. The method of claim 1, wherein the step of irradiating the laser comprises:
performing single crystallization on the second semiconductor layer along the crystallinity of the substrate; and
the plurality of first semiconductor layers are single-crystallized along the crystallinity of the second semiconductor layer that has been single-crystallized.
4. The method of claim 3, wherein:
the step of single-crystallizing the second semiconductor layer includes converting the second semiconductor layer from amorphous to single-crystalline, and
the step of single-crystallizing the plurality of first semiconductor layers includes converting the plurality of first semiconductor layers from amorphous to single-crystalline.
5. The method of claim 4, wherein the substrate comprises a single crystal semiconductor material.
6. The method of claim 1, wherein the step of irradiating the laser comprises:
the laser raises the temperature of the second semiconductor layer; and
heat is supplied from the second semiconductor layer to the plurality of first semiconductor layers.
7. The method of claim 1, wherein forming the second semiconductor layer comprises covering sidewalls of the mold structure with the second semiconductor layer, the sidewalls being defined by the holes.
8. A method of fabricating a semiconductor device, the method comprising:
forming a mold structure including a dielectric layer and a first semiconductor layer on a substrate;
forming a hole penetrating the mold structure;
forming a second semiconductor layer filling the hole on the substrate; and
a laser is irradiated onto the second semiconductor layer,
wherein the step of forming the hole includes exposing a top surface of the substrate.
9. The method of claim 8, wherein the sidewalls of the mold structure have a slope with respect to the top surface of the substrate, the slope being defined by the aperture.
10. The method of claim 9, wherein forming a second semiconductor layer comprises:
forming a first segment of a second semiconductor layer on a substrate; and
forming a second segment of the second semiconductor layer on the sidewalls of the mold structure,
wherein the second segment has a slope with respect to the top surface of the substrate.
11. The method of claim 8, further comprising removing the second semiconductor layer.
12. The method of claim 11, wherein the removing the second semiconductor layer comprises performing a wet etch process to remove the second semiconductor layer.
13. The method of claim 8, wherein the step of irradiating the laser comprises:
the laser raises the temperature of the second semiconductor layer; and
heat is supplied from the second semiconductor layer to the first semiconductor layer.
14. A method of fabricating a semiconductor device, the method comprising:
stacking a plurality of dielectric layers and a plurality of first semiconductor layers on a substrate to form a mold structure;
forming a hole through the mold structure, wherein the forming the hole comprises: forming sidewalls of a mold structure, the sidewalls being defined by the holes, and forming a semiconductor pattern on each of the plurality of first semiconductor layers, the semiconductor pattern extending in a first direction;
forming a second semiconductor layer filling the hole on the substrate;
irradiating laser onto the second semiconductor layer;
forming a first conductive line on the sidewall of the mold structure;
forming a second conductive line extending in a second direction crossing the first direction on the semiconductor pattern; and
data storage elements connected to the semiconductor pattern are formed.
15. The method of claim 14, wherein the semiconductor pattern comprises:
a first impurity region connected to the second conductive line; and
and a second impurity region connected to the data storage element.
16. The method of claim 14, wherein the step of forming the first conductive line comprises:
forming an initial conductive line on a sidewall of the mold structure;
forming a mask pattern including an opening on the mold structure; and
the original conductive lines exposed to the openings are removed.
17. The method of claim 16, wherein the step of forming the initial conductive line comprises:
conformally forming a barrier layer on sidewalls of the mold structure;
forming a conductive layer conformally on the barrier layer; and
an etch stop layer and a conductive layer.
18. The method of claim 14, further comprising forming a second dielectric layer that completely fills the hole.
19. The method of claim 18, further comprising performing a wet etch process to remove the second semiconductor layer and the second dielectric layer.
20. The method according to claim 18, wherein the step of irradiating laser light includes liquefying the second semiconductor layer.
Technical Field
The present inventive concept relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a three-dimensional semiconductor memory device having an increased integration degree and a method of manufacturing the same.
Background
Semiconductor devices have been highly integrated for higher performance and/or lower manufacturing costs of semiconductor devices required by consumers. Since the degree of integration of semiconductor devices is one factor that determines the price of products, higher integration of semiconductor devices is increasingly required. The degree of integration of a typical two-dimensional or planar semiconductor device is mainly determined by the area occupied by the unit memory cell, so that the degree of integration of the two-dimensional or planar semiconductor device is influenced by the state of the art for forming fine patterns. However, expensive processing equipment required to increase the fineness of the pattern may set practical limits to increasing the integration of two-dimensional or planar semiconductor devices. Therefore, a three-dimensional semiconductor memory device having memory cells arranged three-dimensionally has been proposed.
Disclosure of Invention
Some example embodiments of the inventive concepts provide a three-dimensional semiconductor memory device (or a three-dimensional semiconductor device) having an increased integration degree and a method of manufacturing the same.
According to some example embodiments of the inventive concepts, a method of manufacturing a semiconductor device may include: alternately stacking a plurality of dielectric layers and a plurality of first semiconductor layers on a substrate to form a mold structure; forming a hole penetrating the mold structure; forming a second semiconductor layer filling the hole on the substrate; and irradiating laser light onto the second semiconductor layer.
According to some example embodiments of the inventive concepts, a method of manufacturing a semiconductor device may include: forming a mold structure including a dielectric layer and a first semiconductor layer on a substrate; forming a hole penetrating the mold structure; forming a second semiconductor layer filling the hole on the substrate; and irradiating laser light onto the second semiconductor layer. The step of forming the hole may include exposing a top surface of the substrate.
According to some example embodiments of the inventive concepts, a method of manufacturing a semiconductor device may include: stacking a plurality of dielectric layers and a plurality of first semiconductor layers on a substrate to form a mold structure; forming a hole penetrating the mold structure, wherein the forming the hole may include: forming sidewalls of the mold structure, the sidewalls being defined by the holes, and forming a semiconductor pattern on each of the first semiconductor layers, the semiconductor pattern extending in a first direction; forming a second semiconductor layer filling the hole on the substrate; irradiating laser onto the second semiconductor layer; forming a first conductive line on the sidewall of the mold structure; forming a second conductive line extending in a second direction crossing the first direction on the semiconductor pattern; and forming a data storage element connected to the semiconductor pattern.
Drawings
Fig. 1A to 4A illustrate plan views illustrating a single crystallization method according to some example embodiments of the inventive concept.
Fig. 1B to 4B show sectional views taken along line a-a' of fig. 1A to 4A, respectively.
Fig. 3C shows a cross-sectional view taken along line a-a' of fig. 3A.
Fig. 5 illustrates a simplified circuit diagram showing a cell array of a three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts.
Fig. 6 illustrates a perspective view showing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts.
Fig. 7 shows an enlarged perspective view showing a unit cell of the three-dimensional semiconductor memory device shown in fig. 6.
Fig. 8 illustrates a perspective view showing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts.
Figure 9 shows a plan view showing the three-dimensional semiconductor memory device shown in figure 8.
Fig. 10A, 10B, 10C, 10D and 10E show cross-sectional views taken along lines a-a ', B-B ', C-C ', D-D ' and E-E ' of fig. 9, respectively.
Fig. 11 shows a plan view taken along line N of fig. 8.
Fig. 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 and 32 illustrate plan views showing methods of fabricating a three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts.
Fig. 13, fig. 15, fig. 17, fig. 19, fig. 21A, fig. 23A, fig. 25A, fig. 27A, fig. 29A, fig. 31A and fig. 33A show cross-sectional views taken along line a-a' of fig. 12, fig. 14, fig. 16, fig. 18, fig. 20, fig. 22, fig. 24, fig. 26, fig. 28, fig. 30 and fig. 32, respectively.
Fig. 21B, 23B, 25B, 27B, 29B, 31B and 33B show cross-sectional views taken along line B-B' of fig. 20, 22, 24, 26, 28, 30 and 32, respectively.
Fig. 25C, 27C, 29C, 31C and 33C show cross-sectional views taken along line C-C' of fig. 24, 26, 28, 30 and 32, respectively.
Fig. 25D, 27D, 29D, 31D and 33D show cross-sectional views taken along line D-D' of fig. 24, 26, 28, 30 and 32, respectively.
Fig. 29E, 31E and 33E show cross-sectional views taken along line E-E' of fig. 28, 30 and 32, respectively.
Detailed Description
Fig. 1A to 4A illustrate plan views illustrating a single crystallization method according to some example embodiments of the inventive concept. Fig. 1B to 4B show sectional views taken along line a-a' of fig. 1A to 4A, respectively. Fig. 3C shows a cross-sectional view taken along line a-a' of fig. 3A.
Referring to fig. 1A and 1B, a mold structure MS may be formed on a
The
Referring to fig. 2A and 2B, the mold structure MS may be patterned to form holes HO penetrating the first layer L1 to the fifth layer L5. The hole HO may expose the top surface of the
The hole HO may have a first width W1 in a first direction D1 at the same level as the level of the top surface of the
The holes HO may define sidewalls MSW of the mold structure MS. Each of the sidewalls MSW of the mold structure MS may have a slope with respect to the top surface of the
Referring to fig. 3A and 3B, a second semiconductor layer SL2 may be conformally formed on the entire surface of the
An annealing process may be performed on the first semiconductor layer SL1 and the second
The first semiconductor layer SL1 and the second semiconductor layer SL2 may be monocrystallized due to their temperature increase. The step of single-crystallizing the first semiconductor layer SL1 and the second semiconductor layer SL2 may include: the first segment SL21 of the second semiconductor layer SL2 is mono-crystallized along the crystallinity (crystallinity) of the
Referring to fig. 3A and 3C, in an embodiment different from the embodiment shown in fig. 3B, after the second semiconductor layer SL2 is conformally formed on the entire surface of the
When the laser beam L is irradiated onto the second semiconductor layer SL2, the second semiconductor layer SL2 may be liquefied due to its temperature increase. When the second semiconductor layer SL2 is liquefied, the second semiconductor layer SL2 may be supported by the second dielectric layer IL2 and thus may maintain its shape.
Referring to fig. 4A and 4B, a wet etching process may be performed to remove the second
In the single crystallization method according to some example embodiments of the inventive concept, one irradiation of the laser beam L may simultaneously single-crystallize the plurality of first semiconductor layers
Fig. 5 illustrates a simplified circuit diagram showing a cell array of a three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts.
Referring to fig. 5, a three-dimensional semiconductor memory device (or a three-dimensional semiconductor device) according to some example embodiments of the inventive concepts may include a cell array composed of a plurality of sub cell arrays SCA. The sub cell array SCA may be arranged along the second direction D2.
Each of the sub cell arrays SCA may include a plurality of bit lines BL, a plurality of word lines WL, and a plurality of memory cell transistors MCT. One memory cell transistor MCT may be disposed between one word line WL and one bit line BL.
The bit lines BL may be conductive patterns (e.g., metal lines) spaced apart from and disposed on the substrate. The bit line BL may extend in a first direction D1. The bit lines BL in one sub cell array SCA may be spaced apart from each other in a vertical direction (e.g., the third direction D3).
The word line WL may be a conductive pattern (e.g., a metal line) extending to the substrate in a vertical direction (e.g., the third direction D3). Alternatively, the word lines WL may be conductive patterns extending at an angle other than perpendicular to the top surface of the substrate. Word lines WL in one sub cell array SCA may be spaced apart from each other in the first direction D1.
The gate of memory cell transistor MCT may be connected to a word line WL and the source of memory cell transistor MCT may be connected to a bit line BL. Each memory cell transistor MCT may include a data storage element DS. For example, the data storage element DS may be a capacitor, and the drain of the memory cell transistor MCT may be connected to the capacitor.
Fig. 6 illustrates a perspective view showing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts. Fig. 7 shows an enlarged perspective view showing a unit cell of the three-dimensional semiconductor memory device shown in fig. 6.
Referring to fig. 5, 6 and 7, the
For example, the
Each of the semiconductor patterns SP may have a line shape, a bar shape, or a column shape extending in the second direction D2. For example, the semiconductor pattern SP may include single crystal silicon, single crystal germanium, or single crystal silicon germanium. Each of the semiconductor patterns SP may include a channel region CH, a first impurity region SD1, and a second
The data storage elements DS may be connected to corresponding end portions of the semiconductor patterns SP. The data storage element DS may be connected to the corresponding second impurity region SD2 of the semiconductor pattern SP. The data storage element DS may be a memory element capable of storing data. Each of the data storage elements DS may be a memory element using one of a capacitor, a magnetic tunnel junction pattern, and a variable resistance member including a phase change material. For example, the data storage element DS may be a capacitor.
Each of the first conductive lines CL1 may have a linear or bar shape extending in the first direction D1. The first conductive lines CL1 may be spaced apart and stacked in the third direction D3. First conductive line CL1 may include a conductive material. For example, the conductive material may be one of a doped semiconductor (doped silicon, doped germanium, etc.), a conductive metal nitride (titanium nitride, tantalum nitride, etc.), a metal (tungsten, titanium, tantalum, etc.), and a metal-semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, etc.). The first conductive line CL1 may correspond to the bit line BL discussed with reference to fig. 5.
Among the first layer L1, the second layer L2, and the third layer L3, the first layer L1 will now be representatively described in detail. The semiconductor patterns SP of the first layer L1 may be arranged spaced apart from each other in the first direction D1. The semiconductor patterns SP of the first layer L1 may be located at the same first level. The first conductive line CL1 of the first layer L1 may be disposed on the semiconductor pattern SP of the first layer L1. The first conductive line CL1 may be disposed on the top surface of the semiconductor pattern SP. The first conductive line CL1 may be disposed on the top surface of the first impurity region SD1 of the semiconductor pattern SP. The first conductive line CL1 may be placed at a second level higher than the first level at which the semiconductor pattern SP is located. For example, the first conductive line CL1 may be directly connected to the first
The
For example, one second conductive line CL2 of the second conductive lines CL2 may be adjacent to the first one of the semiconductor patterns SP of the first layer L1, the first one of the semiconductor patterns SP of the second layer L2, and the first one of the semiconductor patterns SP of the third layer L3. Another second conductive line CL2 of the second conductive lines CL2 may be adjacent to the second semiconductor pattern of the semiconductor patterns SP of the first layer L1, the second semiconductor pattern of the semiconductor patterns SP of the second layer L2, and the second semiconductor pattern of the semiconductor patterns SP of the third layer L3.
Second conductive line CL2 may include a conductive material, which may be one of a doped semiconductor, a conductive metal nitride, a metal, and a metal-semiconductor compound. The second conductive line CL2 may correspond to the word line WL discussed with reference to fig. 5.
The
Although not shown, the dielectric material may fill the empty space of the stacked structure SS. For example, the dielectric material may include one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.
One of the memory cell transistors of fig. 6 will now be discussed in detail below with reference back to fig. 7. The first and second impurity regions SD1 and SD2 may be impurity-doped portions of the semiconductor pattern SP. The first impurity region SD1 and the second impurity region SD2 may have n-type conductivity or p-type conductivity. The first impurity region SD1 may be formed on an upper portion of the semiconductor pattern SP. The first impurity region SD1 may have a bottom surface SD1b higher than the bottom surface SPb of the semiconductor pattern SP. The semiconductor pattern SP may have a lower portion located below the first impurity region SD1 and connected to the common source line CSL discussed above with reference to fig. 6. First conductive line CL1 may be disposed on top surface SD1t of first impurity region SD1 and electrically connected to first
The second conductive line CL2 may be adjacent to the channel region CH of the semiconductor pattern SP. The second conductive line CL2 may be disposed on a sidewall of the channel region CH while extending in the third direction D3. Gate dielectric GI may be disposed between second conductive line CL2 and channel region CH. The gate dielectric layer GI may include a high-k dielectric layer, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. For example, the high-k dielectric layer may include one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zincate niobate.
Fig. 8 illustrates a perspective view showing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts. Figure 9 shows a plan view showing the three-dimensional semiconductor memory device shown in figure 8. Fig. 10A, 10B, 10C, 10D and 10E show cross-sectional views taken along lines a-a ', B-B ', C-C ', D-D ' and E-E ' of fig. 9, respectively. Fig. 11 shows a plan view taken along line N of fig. 8. In the following embodiments, detailed descriptions of technical features overlapping with those discussed above with reference to fig. 5, 6, and 7 will be omitted, and their differences will be discussed in detail.
Referring to fig. 8, 9, 10A to 10E, and 11, a plurality of stacked structures SS1 and SS2 may be disposed on the
The common source line CSL may be disposed on opposite sides of each of the first and second stacked structures SS1 and
Each of the first and second stack structures SS1 and SS2 may include a first layer L1, a second layer L2, a third layer L3, and a fourth layer L4 sequentially stacked on the
Each of the first, second, third, and fourth layers L1, L2, L3, and L4 may further include a first conductive line CL1 extending in the first direction D1. For example, each of the first, second, third, and fourth layers L1, L2, L3, and L4 may include two first conductive lines CL1 spaced apart from each other in the second direction D2. The first conductive line CL1 may be located at the same level as the
The first semiconductor layer SL1 may include a semiconductor material. The semiconductor material may be a single crystal semiconductor material. For example, the first semiconductor layer SL1 may include single crystal silicon, single crystal germanium, or single crystal silicon germanium. The first dielectric layer ILD1 and the second dielectric layer ILD2 may comprise dielectric materials that are different from each other. Each of the first dielectric layer ILD1 and the second dielectric layer ILD2 may comprise a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a carbon-containing silicon oxide layer, a carbon-containing silicon nitride layer, or a carbon-containing silicon oxynitride layer. For example, the first dielectric layer ILD1 may be a carbon-containing silicon oxide layer (e.g., SiOC) and the second dielectric layer ILD2 may be a silicon nitride layer (e.g., SiN).
Each of the first and second stack structures SS1 and SS2 may be configured such that one end of each of the second and third layers L2 and L3 may protrude beyond one end of the fourth layer L4 in the first direction D1. One end of the second layer L2 and one end of the third layer L3 may be vertically aligned with each other. One end of the first layer L1 may protrude beyond one end of each of the second layer L2 and the third layer L3 in the first direction D1. The other end portion of each of the first layer L1 and the second layer L2 may protrude beyond the other end portion of each of the third layer L3 and the fourth layer L4 in a direction opposite to the first direction D1. The other end of the first layer L1 and the other end of the second layer L2 may be vertically aligned with each other. The other end of the third layer L3 and the other end of the fourth layer L4 may be vertically aligned with each other.
The hole HO may be provided to penetrate each of the first and second stacked structures SS1 and
Each of the semiconductor patterns SP may include a channel region CH, a first impurity region SD1, and a second
The second conductive line CL2 may be disposed to extend in a vertical direction (e.g., the third direction D3) in a hole HO penetrating the first and second stack structures SS1 and
Each of the second conductive lines CL2 may include a barrier pattern BA and a conductive body CB. The conductive body CB may have a line shape extending in the third direction D3. The barrier pattern BA may cover one sidewall and a bottom surface of the conductive body CB. The conductive body CB may include a metal (tungsten, titanium, tantalum, etc.), and the barrier pattern BA may include a conductive metal nitride (titanium nitride, tantalum nitride, etc.). The barrier pattern BA may reduce or prevent the metal material in the conductive body CB from diffusing into the semiconductor pattern SP.
A gate dielectric layer GI may be disposed on an inner sidewall of each of the first and second stacked structures SS1 and SS2, the inner sidewall being exposed to the hole HO. Accordingly, the gate dielectric layer GI may be interposed between each semiconductor pattern SP and each second
Each hole HO may be provided therein with a vertical dielectric pattern VIP covering the second
Each bore HO may have a data storage element DS disposed therein. The data storage element DS may be disposed in the remaining portion of the hole HO. The remaining portion of the hole HO may indicate a space not occupied by the gate dielectric layer GI, the second conductive line CL2, and the vertical dielectric pattern VIP.
Each data storage element DS may include a first electrode EL1, a dielectric layer DL, and a
The data storage element DS may be connected to the corresponding second impurity region SD2 of the semiconductor pattern SP. For example, the first electrode EL1 may be connected to the corresponding second impurity region SD2 of the semiconductor pattern SP. The second electrode EL2 may have a top surface exposed to the hole HO.
The
At least one first contact CNT1 may be disposed to penetrate the
Fig. 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 and 32 illustrate plan views showing methods of fabricating a three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts. Fig. 13, fig. 15, fig. 17, fig. 19, fig. 21A, fig. 23A, fig. 25A, fig. 27A, fig. 29A, fig. 31A and fig. 33A show vertical sectional views taken along line a-a' of fig. 12, fig. 14, fig. 16, fig. 18, fig. 20, fig. 22, fig. 24, fig. 26, fig. 28, fig. 30 and fig. 32, respectively. Fig. 21B, 23B, 25B, 27B, 29B, 31B and 33B show vertical sectional views taken along line B-B' of fig. 20, 22, 24, 26, 28, 30 and 32, respectively. Fig. 25C, 27C, 29C, 31C and 33C show vertical sectional views taken along line C-C' of fig. 24, 26, 28, 30 and 32, respectively. Fig. 25D, 27D, 29D, 31D and 33D show vertical sectional views taken along line D-D' of fig. 24, 26, 28, 30 and 32, respectively. Fig. 29E, 31E and 33E show vertical sectional views taken along line E-E' of fig. 28, 30 and 32, respectively.
Referring to fig. 12 and 13, a mold structure MS may be formed on a
The
A third dielectric ILD3 and a fourth dielectric ILD4 may be formed on the mold structure MS. One of the third dielectric ILD3 and fourth dielectric ILD4 may have an etch selectivity with respect to the other of the third dielectric ILD3 and
Referring to fig. 14 and 15, the mold structure MS may be patterned to form holes HO penetrating the first, second, third, and fourth layers L1, L2, L3, and L4. The hole HO may expose the top surface of the
The holes HO may define sidewalls MSW of the mold structure MS. The sidewalls MSW of the mold structure MS may have a slope with respect to the top surface of the
Each of the first semiconductor layers SL1 may have a semiconductor pattern SP defined by holes HO. For example, the semiconductor pattern SP may be defined by a pair of holes HO adjacent to each other.
The second semiconductor layer SL2 may be conformally formed on the entire surface of the
An annealing process may be performed on the first semiconductor layer SL1 and the second
The first semiconductor layer SL1 and the second semiconductor layer SL2 may be monocrystallized due to their temperature increase. The step of single-crystallizing the first semiconductor layer SL1 and the second semiconductor layer SL2 may include: the second semiconductor layer SL2 is single-crystallized along the crystallinity of the
Referring to fig. 16 and 17, a wet etching process may be performed to remove the second
Referring to fig. 18 and 19, a gate dielectric layer GI may be conformally formed on sidewalls MSW of the mold structure MS exposed to the hole HO. For example, the gate dielectric layer GI may be conformally formed using a high-k dielectric material.
An initial conductor pCL may be formed to partially fill the hole HO. The initial conductive line pCL may be formed on the sidewall MSW of the mold structure MS exposed to the hole HO. The step of forming the initial conductive line pCL may include conformally forming a barrier layer on the gate dielectric layer GI, conformally forming a conductive layer on the barrier layer, and anisotropically etching the barrier layer and the conductive layer to form a barrier pattern BA and a conductive body CB. The barrier layer may be formed using a conductive metal nitride (titanium nitride, tantalum nitride, or the like), and the conductive layer may be formed using a metal (tungsten, titanium, tantalum, or the like).
After the formation of the initial conductive line pCL, a dielectric material IM may be deposited. A dielectric material IM may be deposited to completely fill the hole HO. The dielectric material IM may comprise one or more of silicon oxide, silicon nitride and silicon oxynitride.
Referring to fig. 20, 21A and 21B, a planarization process may be performed on the dielectric material IM and the gate dielectric layer GI until the top surfaces of the
A first mask pattern MA1 including a first opening OP1 and a second opening OP2 may be formed on the
The first mask pattern MA1 may include a closed region CR. Each enclosed region CR may be a portion between the first opening OP1 and the second opening OP2 adjacent to each other. Each enclosed region CR may extend in a first direction D1. The enclosed region CR may define a location where the second conductive line CL2 is formed as discussed below.
The removal process may be performed on the dielectric material IM exposed to the first and second openings OP1 and
The initial conductive line pCL exposed to the first and second openings OP1 and OP2 may be removed to form a second
Referring to fig. 22, 23A and 23B, the first mask pattern MA1 may be removed. A dielectric material may be additionally deposited in the empty space of each hole HO such that a vertical dielectric pattern VIP may be formed to fill each hole HO. A planarization process may be performed to remove the dielectric material deposited on the
The vertical dielectric pattern VIP may be interposed between a pair of semiconductor patterns SP adjacent to each other. The vertical dielectric pattern VIP may be interposed between a pair of second conductive lines CL2 adjacent to each other.
Referring to fig. 24 and 25A to 25D, a second mask pattern MA2 may be formed on the mold structure MS. The second mask pattern MA2 may include linear openings extending in the first direction D1.
The second mask pattern MA2 may be used as an etch mask to pattern the mold structure MS, which may form a plurality of stacked structures SS1 and
The trench TR may expose sidewalls of the first stack structure SS1 and sidewalls of the second
The second dielectric layer ILD2 exposed to the trench TR may be selectively etched to form a
Referring to fig. 26 and 27A to 27D, the semiconductor pattern SP may have an upper portion exposed to the trench TR and the first groove RS1, and the exposed upper portion of the semiconductor pattern SP may be doped with impurities to form a first
A first conductive line CL1 may be formed in the
A dielectric material may be deposited to completely fill the
The common source line CSL may be formed to fill the trench TR. The common source line CSL may be interposed between the first and second stacked structures SS1 and
Referring to fig. 28 and 29A to 29E, a third mask pattern MA3 including a third opening OP3 may be formed on the first and second stacked structures SS1 and
The third mask pattern MA3 may be used as an etch mask to etch the first and second stacked structures SS1 and
The semiconductor pattern SP exposed to the holes HO may be selectively etched to form the
Sidewalls of the semiconductor pattern SP exposed to the hole HO and the second groove RS2 may be doped with impurities to form a second
Referring to fig. 30 and 31A to 31E, partial etching may be performed on the vertical dielectric pattern VIP and the gate dielectric layer GI exposed to the hole HO and the
The first electrode layer ELL may be conformally formed on the entire surface of the
Referring to fig. 32 and 33A to 33E, the first electrode layer ELL may be patterned to form the first electrode EL1 filling the
An isotropic etching process may be performed on the vertical dielectric pattern VIP and the gate dielectric layer GI exposed to the hole HO, which may form a
Referring back to fig. 8, 9, and 10A to 10E, a dielectric layer DL may be conformally formed on the
According to some example embodiments of the inventive concepts, a three-dimensional semiconductor memory device (or a three-dimensional semiconductor device) may include a memory cell transistor and a data storage element (e.g., a capacitor) three-dimensionally stacked on a substrate. This configuration can increase the integration of the memory device. The three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts may be suitable for low temperature calculations performed at temperatures below about 100K.
Although example embodiments of the inventive concept have been discussed with reference to the accompanying drawings, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept. It will thus be appreciated that some of the example embodiments described above are merely illustrative and not restrictive in all respects.
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