阅读说明：本技术 一种具有内嵌沟道二极管的SiC MOSFET结构 (SiC MOSFET structure with embedded channel diode ) 是由 周新田 庞浩洋 贾云鹏 胡冬青 吴郁 于 2019-10-30 设计创作，主要内容包括：本发明提供一种具有内嵌沟道二极管的SiC MOSFET结构,从下至上依次为漏极金属,衬底层,N-漂移层,JFET区；P-base区位于JFET区两侧,P-base预设区域上表面为N+源区及P-plus区；左侧N+源区、P-base区以及部分JFET区上表面为MOSFET栅氧,右侧为厚度较薄的沟道二极管栅氧；MOSFET多晶硅栅位于MOSFET栅氧的上表面；沟道二极管多晶硅栅位于沟道二极管栅氧的上表面；隔离氧位于MOSFET多晶硅栅、沟道二极管多晶硅栅以及裸露的MOSFET栅氧和沟道二极管栅氧的上表面；源极金属位于N+源区、P-plus区及隔离氧的上表面,且与沟道二极管多晶硅栅相连。(The invention provides a SiC MOSFET structure with an embedded channel diode, which sequentially comprises a drain electrode metal, a substrate layer, an N-drift layer and a JFET (junction field effect transistor) region from bottom to top; the P-base area is positioned at two sides of the JFET area, and the upper surface of the P-base preset area is an N + source area and a P-plus area; the upper surfaces of the left N + source region, the P-base region and part of the JFET region are provided with MOSFET gate oxide, and the right side of the left N + source region, the P-base region and part of the JFET region is provided with thinner trench diode gate oxide; the MOSFET polysilicon gate is positioned on the upper surface of the MOSFET gate oxide; the trench diode polysilicon gate is positioned on the upper surface of the trench diode gate oxide; the isolation oxygen is positioned on the upper surfaces of the MOSFET polysilicon gate, the trench diode polysilicon gate, the exposed MOSFET gate oxide and the exposed trench diode gate oxide; the source metal is located on the upper surfaces of the N + source region, the P-plus region and the isolation oxygen and is connected with the polysilicon gate of the trench diode.)

1. A SiC MOSFET structure with an embedded channel diode, comprising:

an N-drift layer 3;

the substrate layer 2 is positioned on the lower surface of the N-drift layer 3;

the drain electrode metal 1 is positioned on the lower surface of the substrate layer 2;

a JFET region 4 located on the upper surface of the N-drift layer 3;

p-base regions 5 located on both sides of the JFET region 4;

the N + source region 6 is positioned on the upper surfaces of the preset regions of the left and right P-base regions 5;

a P-plus region 7 located on the upper surface of the preset region of the left and right P-base regions 5 and located outside the N + source region 6;

the MOSFET gate oxide 9 is positioned on the upper surfaces of the left N + source region 6, the left P-base region 5 and part of the JFET region 4;

the trench diode gate oxide 12 is positioned on the upper surfaces of the right N + source region 6, the right P-base region 5 and part of the JFET region 4, has the thickness smaller than that of the MOSFET gate oxide and is adjacent to the MOSFET gate oxide 9;

the MOSFET polysilicon gate 8 is positioned on the upper surface of the MOSFET gate oxide 9;

the trench diode polysilicon gate 13 is positioned on the upper surface of the trench diode gate oxide 12 and forms a split gate structure with the MOSFET polysilicon gate 8;

the isolation oxygen 10 is positioned on the upper surfaces of the MOSFET polysilicon gate 8, the trench diode polysilicon gate 13, the exposed MOSFET gate oxide 9 and the exposed trench diode gate oxide 12;

and the source metal 11 is positioned on the upper surfaces of the N + source region 6, the P-plus region 7 and the isolation oxide 10 and is connected with the polysilicon gate 13 of the trench diode through a contact hole.

2. The SiC MOSFET structure of claim 1 in which the MOSFET gate oxide 9 is 50nm to 150nm thick.

3. The SiC MOSFET structure of claim 1 in which the trench diode gate oxide 12 is between 10nm and 50nm thick.

4. The SiC MOSFET structure of claim 1 in which the horizontal spacing between the MOSFET polysilicon gate 8 and the trench diode polysilicon gate 13 is between 0.2 μm and 1 μm.

5. The SiC MOSFET structure with an embedded trench diode of claim 1, wherein the contact hole length of the source metal 11 and the polysilicon gate 13 of the trench diode is 0.2 μm to 1 μm.

6. The SiC MOSFET structure of claim 1 in which the MOSFET polysilicon gate 8 and the trench diode polysilicon gate 13 are made of polysilicon doped N-type with P element as the doping element at a concentration of 1 x 10¹⁹～1×10²⁰cm^-3。

7. The SiC MOSFET structure of claim 1, wherein the JFET region 4 is N-type SiC, the doping element is N, and the doping concentration is 1 x 10¹⁷～5×10¹⁷cm^-3The thickness is 1 to 2 μm.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a SiC MOSFET structure with an embedded channel diode.

Background

Breakthrough of wide bandgap semiconductor materials, represented by SiC, is expected to lead to the development of new generation power electronics. The SiC material has higher breakdown field strength, higher carrier saturation velocity and higher thermal conductivity than the Si material, so that the SiC power electronic device has the characteristics of high related power-off voltage, small on-resistance, high switching frequency, high efficiency and good high-temperature performance compared with the similar device of Si. SiC power electronic devices will become one of the important bases for the development of megawatt electronics and green energy.

As a unipolar power device, because of the advantages of low on-resistance, high input impedance, high switching speed and the like, the SiCSMOSFET becomes an ideal high-voltage power switching device within the range of blocking voltage of 3000-4500V, and is completely possible to replace a Si IGBT device, so that the overall efficiency and the switching frequency of a system are further improved. The SiC MOSFET, as a third-generation semiconductor device, is a strong competitor of Si-based devices in the field of power electronics, and has the potential for application at higher temperature, higher voltage, and higher frequency due to the more excellent performance advantages of SiC materials.

In a rectifier or inverter system, a switching device in a power network often needs to be connected with a freewheeling diode in an anti-parallel mode to relieve the impact of voltage spikes on the switching device. Currently, the following schemes are mainly selected for the freewheeling diode: 1. an external diode is adopted, but extra parasitic capacitance and inductance are brought to the system, and the loss of the system is increased; 2. the diode and the switching device are packaged integrally, but the method can increase the area of a chip additionally, thereby increasing the leakage of the device and degrading the temperature characteristic of the device. 3. The parasitic body diode of the MOSFET device itself is used as a follow current tube in reverse operation, but for the conventional SiC MOSFET, the conduction of the body diode also causes two problems: firstly, the SiC MOSFET body diode is close to 3V of starting voltage to cause extra power loss of the system; and secondly, the conduction of the body diode can induce a bipolar degradation phenomenon, which is because the recombination of electron hole pairs can cause the proliferation of SiC material defects, thereby increasing the electric leakage of the whole device and causing failure.

Disclosure of Invention

In order to solve the problem that the traditional SiC MOSFET structure cannot use body diode freewheeling, the invention provides the SiC MOSFET structure with the embedded channel diode. The technical problem to be solved by the invention is realized by the following technical scheme:

one embodiment of the present invention provides a SiC MOSFET structure with embedded channel diodes, comprising:

an N-drift layer;

the substrate layer is positioned on the lower surface of the N-drift layer;

the drain electrode metal is positioned on the lower surface of the substrate layer;

the JFET region is positioned on the upper surface of the N-drift layer;

p-base regions located on both sides of the JFET region;

the N + source region is positioned on the upper surfaces of the preset regions of the left and right P-base regions;

the P-plus area is positioned on the upper surface of the preset area of the left and right P-base areas and positioned outside the N + source area;

the MOSFET gate oxide is positioned on the upper surfaces of the left N + source region, the left P-base region and part of the JFET region;

the trench diode gate oxide is positioned on the upper surfaces of the right N + source region, the right P-base region and part of the JFET region, has the thickness smaller than that of the MOSFET gate oxide and is adjacent to the MOSFET gate oxide;

the MOSFET polysilicon gate is positioned on the upper surface of the MOSFET gate oxide;

the trench diode polysilicon gate is positioned on the upper surface of the trench diode gate oxide and forms a split gate structure with the MOSFET polysilicon gate;

the isolation oxygen is positioned on the upper surfaces of the MOSFET polysilicon gate, the trench diode polysilicon gate, the exposed MOSFET gate oxide and the exposed trench diode gate oxide;

and the source metal is positioned on the upper surfaces of the N + source region, the P-plus region and the isolation oxygen and is connected with the polycrystalline silicon gate of the trench diode through a contact hole.

Preferably, the MOSFET gate oxide thickness is 50 nm-150 nm.

Preferably, the thickness of the gate oxide of the trench diode is 10 nm-50 nm.

Preferably, the horizontal distance between the MOSFET polysilicon gate and the trench diode polysilicon gate is 0.2-1 μm.

Preferably, the length of the contact hole between the source metal and the polysilicon gate of the trench diode is 0.2-1 μm.

Preferably, the material of the MOSFET polysilicon gate and the trench diode polysilicon gate is polysilicon, the polysilicon is doped in an N-type manner, the doping element is P element, and the doping concentration is 1 × 10¹⁹～1×10²⁰cm^-3。

Preferably, the JFET region is N-type SiC, the doping element is N element, and the doping concentration is 1 x 10¹⁷～5×10¹⁷cm^-3The thickness is 1 to 2 μm.

Advantageous effects

When the SiC MOSFET structure with the embedded channel diode is used as a follow current tube, current can be transported through the channel diode instead of a parasitic body diode, so that the bipolar degradation effect can be completely eliminated, the turn-on voltage is reduced, and the power loss is reduced; in addition, a polysilicon gate of the trench diode is formed by etching partial polysilicon, so that the coupling effect between device electrodes is weakened, and the capacitance characteristic and the gate charge characteristic of the SiC MOSFET are greatly improved.

Drawings

FIG. 1 is a diagram of a conventional SiC MOSFET structure;

FIG. 2 is a block diagram of a SiC MOSFET with embedded channel diodes in accordance with the present invention;

FIG. 3 is a comparison graph of simulation results of conduction curves of a conventional structure and a structure of the present invention when the device is operated in a reverse freewheeling state;

FIG. 4 shows the current I in the reverse direction_SD＝100A/cm²Comparing the hole concentration distribution situation in the device of the traditional structure and the structure of the invention;

FIG. 5 shows the current I in the reverse direction_SD＝100A/cm²Meanwhile, the longitudinal distribution diagram of the hole concentration in the traditional structure and the structure device of the invention is shown;

FIG. 6 is a graph comparing the forward conduction characteristic and the reverse breakdown characteristic of the device of the conventional structure and the structure of the present invention;

FIG. 7 shows the current I in the forward direction_DS＝100A/cm²Comparing the current density distribution inside the device with the traditional structure and the structure of the invention;

FIG. 8 shows the input capacitance characteristics (C) of the device with the conventional structure and the structure of the present invention_ISS) Output capacitance characteristic (C)_OSS) And transfer capacitance characteristics (C)_RSS) Comparing the simulation results with a graph;

FIG. 9(a) is a circuit diagram showing simulation of gate charge characteristics, and FIG. 9(b) is a comparison graph of simulation results of gate charge characteristics of a conventional structure and a structure of the present invention;

table 1 is a summary comparison of the performance parameters of the conventional structure and the structure of the present invention;

fig. 10-21 are flow charts of methods for fabricating device structures of the present invention.

Detailed Description

The principles and features of this invention are described in connection with the drawings, which are set forth as examples only and not intended to limit the scope of the invention.

In this embodiment, the terms "upper", "lower", "left" and "right" refer to the positional relationship when the MOSFET device structure is in the illustrated state, "long" refers to the lateral dimension when the MOSFET device structure is in the illustrated state, and "thick" refers to the longitudinal dimension when the MOSFET device structure is in the illustrated state.