阅读说明：本技术 薄膜晶体管及其制造方法 (Thin film transistor and method of manufacturing the same ) 是由 刘方梅 于 2019-10-22 设计创作，主要内容包括：本发明公开一种薄膜晶体管及其制造方法,所述薄膜晶体管包括一基板、一遮光层、一中间缓冲层及一缓冲层；其中所述遮光层形成在所述基板上,所述缓冲层位于所述基板及所述遮光层上方,所述中间缓冲层形成在所述缓冲层及所述遮光层之间,而且所述中间缓冲层为陶瓷材料。(The invention discloses a thin film transistor and a manufacturing method thereof, wherein the thin film transistor comprises a substrate, a shading layer, an intermediate buffer layer and a buffer layer; the light shielding layer is formed on the substrate, the buffer layer is positioned above the substrate and the light shielding layer, the intermediate buffer layer is formed between the buffer layer and the light shielding layer, and the intermediate buffer layer is made of ceramic materials.)

1. A thin film transistor, characterized by:

the thin film transistor comprises a substrate, a shading layer, an intermediate buffer layer and a buffer layer;

the light shielding layer is formed on the substrate, the buffer layer is positioned above the substrate and the light shielding layer, the intermediate buffer layer is formed between the buffer layer and the light shielding layer, and the intermediate buffer layer is made of ceramic materials.

2. The thin film transistor of claim 1, wherein: the thin film transistor further comprises an oxide semiconductor layer, a grid electrode insulating layer, a grid electrode metal layer, a doped semiconductor layer, an interlayer insulating layer and a source drain metal layer, wherein the source drain metal layer extends to the doped semiconductor layer through two first channels, and the source drain metal layer extends to the shading layer through a second channel.

3. The thin film transistor of claim 1, wherein: the ceramic material of the middle buffer layer is silicon nitride, and the thickness of the middle buffer layer is 500-2000 angstroms.

4. The thin film transistor of claim 1, wherein: the buffer layer is made of silicon oxide, and the thickness of the buffer layer is 1000-3000 angstroms.

5. The thin film transistor of claim 2, wherein: the two first channels penetrate through the interlayer insulating layer, and are respectively positioned on two opposite sides of the gate metal layer.

6. The thin film transistor of claim 2, wherein: the second channel penetrates the interlayer insulating layer, the buffer layer, and the intermediate buffer layer.

7. A method of manufacturing a thin film transistor, characterized by: the manufacturing method of the thin film transistor comprises the following steps:

a light-shielding layer forming step of depositing a light-shielding layer on a substrate;

a step of forming an intermediate buffer layer, which is formed on the substrate and the light-shielding layer, wherein the intermediate buffer layer is made of a ceramic material; and

and a buffer layer forming step of forming a buffer layer on the intermediate buffer layer such that the intermediate buffer layer is positioned between the buffer layer and the light-shielding layer.

8. The manufacturing method of the thin film transistor according to claim 7, wherein: in the intermediate buffer layer forming step, the ceramic material of the intermediate buffer layer is silicon nitride, and a thickness of the intermediate buffer layer is 500 to 2000 angstroms.

9. The manufacturing method of the thin film transistor according to claim 7, wherein: in the buffer layer forming step, the buffer layer is made of silicon oxide, and a thickness of the buffer layer is 1000 to 3000 angstroms.

10. The manufacturing method of the thin film transistor according to claim 7, wherein: in the light shielding layer forming step, the light shielding layer is a two-layer structure, wherein an upper layer of the two-layer structure is copper.

Technical Field

The present invention relates to a thin film transistor and a method for fabricating the same, and more particularly, to a thin film transistor using indium gallium zinc oxide and a method for fabricating the same.

Background

Currently, Oxide Thin Film transistors (Oxide TFTs) are widely used in Integrated Circuits (ICs) and image display device driving circuits due to their excellent performance. As a channel for realizing charge transmission between a source electrode and a drain electrode of a TFT (thin film transistor), a channel layer of a field effect transistor is an important structure of the TFT, and the structure and the performance of the channel layer directly influence the electrical performance of a finished product of the device. Semiconductor thin film materials, known as silicon-based semiconductor materials and oxide semiconductor materials, may be used for the channel layer. An example of an Oxide semiconductor material is Indium Gallium Zinc Oxide (IGZO).

Generally, in the process of fabricating a top gate IGZO TFT, a Light Shield (LS) is usually a two-layer structure of molybdenum (Mo) and copper (Cu), wherein an upper layer of the two-layer structure is copper and a lower layer thereof is molybdenum. However, there are products, such as: in a gate driver on array (GOA), a light-shielding layer is required to be used as a wiring, and in order to reduce the series resistance Rs, molybdenum and copper are required to be used as the light-shielding layer. An intermediate buffer layer (buffer layer) of a conventional top gate IGZO TFT is formed of silicon oxide (SiOx), SiOx is deposited on a copper film by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, and a generated reaction gas, namely nitrous oxide (N2O), oxidizes the surface of the copper film on the upper layer of the two-layer structure, and the SiOx has poor coverage and is prone to generate an undercut (undercut).

Therefore, there is a need for an improved thin film transistor and a method for fabricating the same to solve the above-mentioned problems of the prior art.

Disclosure of Invention

The invention aims to provide a thin film transistor and a manufacturing method thereof, wherein the intermediate buffer layer is made of ceramic materials, the intermediate buffer layer is made of ceramic materials instead of silicon oxide, and the phenomenon that a single intermediate buffer layer is made of silicon oxide to generate chamfers can be avoided.

In order to achieve the above objective, an embodiment of the present invention provides a thin film transistor, which includes a substrate, a light-shielding layer, an intermediate buffer layer, and a buffer layer; the light shielding layer is formed on the substrate, the buffer layer is positioned above the substrate and the light shielding layer, the intermediate buffer layer is formed between the buffer layer and the light shielding layer, and the intermediate buffer layer is made of ceramic materials.

In an embodiment of the present invention, the thin film transistor further includes an oxide semiconductor layer, a gate insulating layer, a gate metal layer, a doped semiconductor layer, an interlayer insulating layer, and a source/drain metal layer, where the source/drain metal layer extends to the doped semiconductor layer through two first channels, and the source/drain metal layer extends to the light shielding layer through one second channel.

In an embodiment of the invention, the ceramic material of the intermediate buffer layer is silicon nitride, and a thickness of the intermediate buffer layer is 500 a to 2000 a.

In an embodiment of the invention, the buffer layer is made of silicon oxide, and a thickness of the buffer layer is 1000 to 3000 angstroms.

In an embodiment of the invention, the two first channels penetrate through the interlayer insulating layer, and the two first channels are respectively located on two opposite sides of the gate metal layer.

In an embodiment of the present invention, the second trench penetrates the interlayer insulating layer, the buffer layer, and the intermediate buffer layer.

In order to achieve the above object, an embodiment of the present invention provides a method for manufacturing a thin film transistor, which includes a light-shielding layer forming step, an intermediate buffer layer forming step, and a buffer layer forming step; in the step of forming the light shielding layer, depositing a light shielding layer on a substrate; in the intermediate buffer layer forming step, forming an intermediate buffer layer on the substrate and the light shielding layer, wherein the intermediate buffer layer is made of a ceramic material; in the buffer layer forming step, a buffer layer is formed on the intermediate buffer layer such that the intermediate buffer layer is located between the buffer layer and the light-shielding layer.

In an embodiment of the invention, in the step of forming the intermediate buffer layer, the ceramic material of the intermediate buffer layer is silicon nitride, and a thickness of the intermediate buffer layer is 500 a to 2000 a.

In an embodiment of the invention, in the buffer layer forming step, a material of the buffer layer is silicon oxide, and a thickness of the buffer layer is 1000 angstroms to 3000 angstroms.

In an embodiment of the invention, in the step of forming the light-shielding layer, the light-shielding layer has a two-layer structure, wherein an upper layer of the two-layer structure is copper.

As described above, by using different materials for the intermediate buffer layer and the buffer layer, and using a ceramic material to replace silicon oxide, such as silicon nitride, the intermediate buffer layer can avoid the occurrence of undercuts (undercuts) caused by the fact that a single intermediate buffer layer is made of silicon oxide, and improve the coverage of the intermediate buffer layer, and at the same time, can reduce the diffusion of copper ions, so as to reduce the chance of oxidation.

Drawings

Fig. 1 is a schematic diagram of a preferred embodiment of a thin film transistor according to the present invention.

Fig. 2 is a flow chart of a preferred embodiment of a method of manufacturing a thin film transistor according to the present invention.

Detailed Description

The following description of the embodiments refers to the accompanying drawings for illustrating the specific embodiments in which the invention may be practiced. Furthermore, directional phrases used herein, such as, for example, upper, lower, top, bottom, front, rear, left, right, inner, outer, lateral, peripheral, central, horizontal, lateral, vertical, longitudinal, axial, radial, uppermost or lowermost, etc., refer only to the orientation of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention.

Fig. 1 is a schematic diagram of a thin film transistor according to a preferred embodiment of the present invention. The thin film transistor is a top gate Indium Gallium Zinc Oxide (IGZO) thin film transistor, and includes a substrate 21, a light shielding layer 22, an intermediate buffer layer 23, a buffer layer 24, an Oxide semiconductor layer 25, a gate insulating layer 26, a gate metal layer 27, a doped semiconductor layer 28, an intermediate insulating layer 29, a source/drain metal layer 30, and a passivation layer 31. The detailed construction, assembly relationship and operation principle of the above components of the embodiments of the present invention will be described in detail below.

Referring to fig. 1, the light-shielding layer 22 is formed on the substrate 21, wherein the light-shielding layer 22 is a two-layer structure (not shown), an upper layer of the two-layer structure is copper, and a lower layer thereof is molybdenum. The intermediate buffer layer 23 is formed on the substrate 21 and the light-shielding layer 22, the buffer layer 24 is formed on the intermediate buffer layer 23, the intermediate buffer layer 23 and the buffer layer 24 are made of different materials, and the intermediate buffer layer 23 is made of a ceramic material; the oxide semiconductor layer 25 is formed on the buffer layer 24, wherein the oxide semiconductor layer 25 is patterned by light irradiation, and the material of the oxide semiconductor layer 25 is indium gallium zinc oxide.

In this embodiment, the ceramic material of the intermediate buffer layer 23 is silicon nitride, the material of the buffer layer 24 is silicon oxide, a thickness of the intermediate buffer layer 23 is 500 angstroms to 2000 angstroms, and a thickness of the buffer layer 24 is 1000 angstroms to 3000 angstroms.

Referring to fig. 1, the gate insulating layer 26 is formed on the oxide semiconductor layer 25, and the gate metal layer 27 is formed on the gate insulating layer 26, wherein the gate metal layer 27 and the gate insulating layer 26 are patterned by etching to expose a portion of the oxide semiconductor layer 25; the exposed portion of the oxide semiconductor layer 25 is subjected to plasma treatment to form the doped semiconductor layer 28.

Referring to fig. 1, the interlayer insulating layer 29 is formed on the buffer layer 24, the doped semiconductor layer 28 and the gate metal layer 27; the source and drain metal layers 30 are formed on the interlayer insulating layer 29, wherein the source and drain metal layers 30 are connected to the doped semiconductor layer 28 and the light shielding layer 22, and the passivation layer 31 is formed on the interlayer insulating layer 29 and the source and drain metal layers 30. In this embodiment, the source/drain metal layer 30 extends 301 to the doped semiconductor layer 28 through two first channels, the source/drain metal layer 30 extends to the light shielding layer 22 through one second channel 302, and the first channels 301 penetrate the interlayer insulating layer 29 and are respectively located on two opposite sides of the gate metal layer 27.

Referring to fig. 1, a planarization layer 32 is formed on the passivation layer 31, a pixel defining layer 33 is formed on the planarization layer 32, an anode layer 34 and a light emitting layer 35 are formed on the pixel defining layer 33, and a cathode layer 36 is formed on the pixel defining layer 33 and the light emitting layer 35. In the present embodiment, the light emitting layer 35 is an Organic Light Emitting Diode (OLED) light emitting layer.

As described above, by using different materials for the intermediate buffer layer 23 and the buffer layer 24, and using a ceramic material for the intermediate buffer layer 23 instead of silicon oxide, such as silicon nitride, the occurrence of rounding (undercut) caused by using silicon oxide as a single intermediate buffer layer can be avoided, the coverage of the intermediate buffer layer can be improved, and the diffusion of copper ions can be reduced, so as to reduce the chance of oxidation.

Fig. 2 is a flowchart of a method for manufacturing a thin film transistor according to a preferred embodiment of the present invention with reference to fig. 1. The method for manufacturing the thin film transistor includes a light-shielding layer forming step S201, an intermediate buffer layer forming step S202, a buffer layer forming step S203, an oxide semiconductor layer forming step S204, a gate insulating layer forming step S205, a gate metal layer forming step S206, a doped semiconductor layer forming step S207, an intermediate insulating layer forming step S208, a source-drain metal layer forming step S209, and a passivation layer forming step S210. The present invention will be described in detail with reference to the following drawings.

Referring to fig. 2 and fig. 1, in the light-shielding layer forming step S201, a light-shielding layer 22 is deposited on a substrate 21, wherein the light-shielding layer 22 is a two-layer structure (not shown), an upper layer of the two-layer structure is copper, and a lower layer thereof is molybdenum.

Referring to fig. 2 and fig. 1, in the intermediate buffer layer forming step S202, an intermediate buffer layer 23 is formed on the substrate 21 and the light-shielding layer 22, and the intermediate buffer layer 23 is a ceramic material, in this embodiment, the ceramic material of the intermediate buffer layer 23 is silicon nitride, and a thickness of the intermediate buffer layer 23 is 500 angstroms to 2000 angstroms.

Referring to fig. 2 in conjunction with fig. 1, in the buffer layer forming step S203, a buffer layer 24 is formed on the intermediate buffer layer 23, such that the intermediate buffer layer 23 is located between the buffer layer 24 and the light-shielding layer 22. In this embodiment, the buffer layer 24 is made of silicon oxide, and a thickness of the buffer layer 24 is 1000 angstroms to 3000 angstroms.

Referring to fig. 2 in conjunction with fig. 1, in the step S204, an oxide semiconductor layer 25 is formed on the buffer layer 24, wherein the oxide semiconductor layer 25 is patterned by light irradiation, and the material of the oxide semiconductor layer 25 is indium gallium zinc oxide.

Referring to fig. 2 in conjunction with fig. 1, in the gate insulating layer forming step S205, a gate insulating layer 26 is formed on the oxide semiconductor layer 25.

Referring to fig. 2 in conjunction with fig. 1, in the gate metal layer forming step S206, a gate metal layer 27 is formed on the gate insulating layer 26, wherein the gate metal layer 27 and the gate insulating layer 26 are patterned by etching to expose a portion of the oxide semiconductor layer 25.

Referring to fig. 2 in conjunction with fig. 1, in the doped semiconductor layer forming step S207, a plasma treatment is performed on the exposed portion of the oxide semiconductor layer 25 to form a doped semiconductor layer 28.

Referring to fig. 1 in addition to fig. 2, in the interlayer insulating layer forming step S208, an interlayer insulating layer 29 is formed on the buffer layer 24, the doped semiconductor layer 28 and the gate metal layer 27. In this embodiment, the material of the interlayer insulating layer 29 is silicon oxide or silicon nitride.

Referring to fig. 2 in conjunction with fig. 1, in the source/drain metal layer forming step S209, a source/drain metal layer 30 is formed on the interlayer insulating layer 29, the source/drain metal layer 30 extends to the doped semiconductor layer 28 through two first channels 301, the source/drain metal layer 30 extends to the light shielding layer 22 through a second channel 302, wherein the first channels 301 penetrate through the interlayer insulating layer 29 and are respectively located at two opposite sides of the gate metal layer 27, and the second channel 302 penetrates through the interlayer insulating layer 29, the intermediate buffer layer 23, and the buffer layer 24.

Referring to fig. 2 in conjunction with fig. 1, in the passivation layer forming step S210, a passivation layer 31 is formed on the interlayer insulating layer 29 and the source/drain metal layer 30.

As described above, by using different materials for the intermediate buffer layer 23 and the buffer layer 24, and using a ceramic material for the intermediate buffer layer 23 instead of silicon oxide, such as silicon nitride, the occurrence of rounding (undercut) caused by using silicon oxide as a single intermediate buffer layer can be avoided, the coverage of the intermediate buffer layer can be improved, and the diffusion of copper ions can be reduced, so as to reduce the chance of oxidation.

The present invention has been described in relation to the above embodiments, which are only exemplary of the implementation of the present invention. It must be noted that the disclosed embodiments do not limit the scope of the invention. Rather, modifications and equivalent arrangements included within the spirit and scope of the claims are included within the scope of the invention.