阅读说明：本技术 一种薄膜晶体管、显示面板及薄膜晶体管的制作方法 (Thin film transistor, display panel and manufacturing method of thin film transistor ) 是由 谢华飞 于 2019-10-25 设计创作，主要内容包括：本发明公开了一种薄膜晶体管、显示面板及薄膜晶体管的制作方法。薄膜晶体管包括从下至上依次层叠设置的基板、栅极层、介电层、有源层、源漏极层；所述栅极层上表面设有复数个加强部；其中,所述加强部用于增大栅极层上表面的面积,使所述栅极层与所述有源层的有效对接面积增大,减小所述薄膜晶体管的宽度和长度,减小所述薄膜晶体管的寄生电容。本发明通过设置所述加强部与所述有源层的有效对接面积增大,使得所述栅极层所占面积减少同时又不影响有源层的通电性,提高了显示面板的穿透率,减少了显示面板的寄生电容,提高了薄膜晶体管和显示面板的性能。(The invention discloses a thin film transistor, a display panel and a manufacturing method of the thin film transistor. The thin film transistor comprises a substrate, a grid layer, a dielectric layer, an active layer and a source drain layer which are sequentially stacked from bottom to top; the upper surface of the grid layer is provided with a plurality of strengthening parts; the reinforcing part is used for increasing the area of the upper surface of the grid layer, so that the effective butt joint area of the grid layer and the active layer is increased, the width and the length of the thin film transistor are reduced, and the parasitic capacitance of the thin film transistor is reduced. According to the invention, the effective butt joint area of the reinforcing part and the active layer is increased, so that the occupied area of the grid layer is reduced, the electrification performance of the active layer is not influenced, the penetration rate of the display panel is improved, the parasitic capacitance of the display panel is reduced, and the performances of the thin film transistor and the display panel are improved.)

1. A thin film transistor, comprising:

a substrate;

the grid layer is arranged on the substrate; the upper surface of the grid layer is provided with a plurality of strengthening parts;

the dielectric layer is arranged on the grid layer and completely covers the grid layer;

the active layer is arranged on the dielectric layer and completely covers the dielectric layer; and

the source drain layer is arranged on the active layer and is electrically connected with the active layer; the source drain layer comprises a source electrode and a drain electrode, the source electrode is arranged at one end of the active layer, and the drain electrode is arranged at the other end of the active layer;

the reinforcing part is used for increasing the area of the upper surface of the grid layer, so that the effective butt joint area of the grid layer and the active layer is increased, the width and the length of the thin film transistor are reduced, and the parasitic capacitance of the thin film transistor is reduced.

2. The thin film transistor of claim 1, wherein the reinforcement portions are arranged in an array on the gate layer.

3. The thin film transistor according to claim 1, wherein the reinforcement portion has any one of a columnar shape, a stripe shape, and a lattice shape.

4. The thin film transistor according to claim 1, further comprising

A barrier layer disposed on the active layer;

the source electrode is arranged at one end of the active layer and one end of the barrier layer, and the drain electrode is arranged at the other end of the active layer and the other end of the barrier layer.

5. The thin film transistor according to claim 1, further comprising

The passivation layer is arranged on the source drain layer and completely coats the passivation layer and the active layer; and

and the pixel electrode is arranged on the passivation layer and is electrically connected with the drain electrode.

6. A method for manufacturing a thin film transistor is characterized by comprising the following steps:

providing a substrate;

manufacturing a metal film on the substrate and patterning to form a gate layer; forming a plurality of reinforcement portions on the upper surface of the gate layer;

manufacturing a dielectric layer on the gate layer, wherein the dielectric layer completely wraps the gate layer;

manufacturing an active layer on the dielectric layer, wherein the active layer completely wraps the dielectric layer; and

manufacturing a metal film on the active layer and patterning the metal film to form a source drain layer, wherein the source drain layer is electrically connected with the active layer; the source drain layer comprises a source electrode and a drain electrode, the source electrode is arranged at one end of the active layer, and the drain electrode is arranged at the other end of the active layer.

7. The method of claim 6, wherein the step of forming a plurality of enhancement portions on the top surface of the gate layer comprises:

and arranging a through hole ultrathin aluminum oxide film template on one side of the gate layer, manufacturing the reinforcing part through the ultrathin aluminum oxide film template in an electron beam evaporation or physical vapor deposition mode, and then etching and removing the ultrathin aluminum oxide film template by using a sodium hydroxide solution.

8. The method of claim 6, wherein the step of forming a plurality of enhancement portions on the top surface of the gate layer comprises:

coating a photoresist layer on the gate layer, forming a through hole on the photoresist layer by exposure and development, manufacturing the reinforced part in the through hole by electron beam evaporation or physical vapor deposition, and cleaning and removing the photoresist layer.

9. The method according to claim 6, further comprising, after the step of forming the active layer and before the step of forming the source/drain layer:

manufacturing a barrier layer on the active layer;

in the step of manufacturing the source and drain electrode layers, the source electrode is arranged at one end of the active layer and one end of the barrier layer, and the drain electrode is arranged at the other end of the active layer and the other end of the barrier layer.

10. A display panel comprising the thin film transistor according to any one of claims 1 to 5.

Technical Field

The invention relates to the technical field of display, in particular to a thin film transistor of a top gate thin film transistor, a display panel and a manufacturing method of the thin film transistor.

Background

Currently, in a Thin Film Transistor (TFT) device, an active layer performs on or off of a source and a drain by gate voltage adjustment. The gate can be considered as a switch for controlling a physical gate, the gate is arranged corresponding to the active layer of the semiconductor material, the application of voltage on the gate attracts electrons in the doped semiconductor of the active layer, the electrons in the semiconductor are increased suddenly as the voltage of the gate increases, a channel is formed in the active layer, and thus the source and the drain at two ends of the active layer are conducted; the channel is controlled or eliminated by applying a voltage to the gate, thereby allowing or blocking the flow of electrons. In display applications, the gate electrode also has the effect of blocking light from the active layer to reduce the effect of light on the active layer. However, at the same time, too wide a gate electrode may decrease the transmittance of the thin film transistor device and may increase the parasitic capacitance of the display panel, thereby decreasing the display performance.

Therefore, there is a need to develop a new thin film transistor, a display panel and a method for fabricating the thin film transistor to overcome the drawbacks of the prior art.

Disclosure of Invention

The invention provides a thin film transistor, a display panel and a manufacturing method of the thin film transistor.

In order to achieve the above object, the present invention provides a thin film transistor, which includes a substrate, a gate layer, a dielectric layer, an active layer, and a source/drain layer stacked in sequence from bottom to top. Specifically, the gate layer is arranged on the substrate; the upper surface of the grid layer is provided with a plurality of strengthening parts; the dielectric layer is arranged on the gate layer and completely covers the gate layer; the active layer is arranged on the dielectric layer and completely covers the dielectric layer; the source drain layer is arranged on the active layer and is electrically connected with the active layer; the source drain layer comprises a source electrode and a drain electrode, the source electrode is arranged at one end of the active layer, and the drain electrode is arranged at the other end of the active layer; the reinforcing part is used for increasing the area of the upper surface of the grid layer, so that the effective butt joint area of the grid layer and the active layer is increased, the width and the length of the thin film transistor are reduced, and the parasitic capacitance of the thin film transistor is reduced.

Further, the reinforced parts are arranged on the grid layer in an array mode.

Further, the reinforcing part is in any one of a column shape, a bar shape, and a mesh shape.

Furthermore, the thin film transistor also comprises a barrier layer, and the barrier layer is arranged on the active layer; the source electrode is arranged at one end of the active layer and one end of the barrier layer, and the drain electrode is arranged at the other end of the active layer and the other end of the barrier layer.

Further, the reinforced parts are arranged on the grid layer in an array mode.

Furthermore, the thin film transistor also comprises a passivation layer and a pixel electrode, wherein the passivation layer is arranged on the source drain layer and completely covers the passivation layer and the active layer; the pixel electrode is arranged on the passivation layer and electrically connected with the drain electrode.

The invention also provides a manufacturing method of the thin film transistor, which comprises the following steps:

providing a substrate;

manufacturing a metal film on the substrate and patterning to form a gate layer;

forming a plurality of reinforcement portions on the upper surface of the gate layer;

manufacturing a dielectric layer on the gate layer, wherein the dielectric layer completely wraps the gate layer;

manufacturing an active layer on the dielectric layer, wherein the active layer completely wraps the dielectric layer; and

manufacturing a metal film on the active layer and patterning the metal film to form a source drain layer, wherein the source drain layer is electrically connected with the active layer; the source drain layer comprises a source electrode and a drain electrode, the source electrode is arranged at one end of the active layer, and the drain electrode is arranged at the other end of the active layer.

Further, the step of fabricating a plurality of reinforcement portions on the upper surface of the gate layer includes: and arranging a through hole ultrathin aluminum oxide film template on one side of the gate layer, manufacturing the reinforcing part through the ultrathin aluminum oxide film template in an electron beam evaporation or physical vapor deposition mode, and then etching and removing the ultrathin aluminum oxide film template by using a sodium hydroxide solution.

Further, the step of fabricating a plurality of reinforcement portions on the upper surface of the gate layer includes: coating a photoresist layer on the gate layer, forming a through hole on the photoresist layer by exposure and development, manufacturing the reinforced part in the through hole by electron beam evaporation or physical vapor deposition, and cleaning and removing the photoresist layer.

Further, after the step of fabricating the active layer and before the step of fabricating the source drain layer, the method further includes: manufacturing a barrier layer on the active layer; in the step of manufacturing the source and drain electrode layers, the source electrode is arranged at one end of the active layer and one end of the barrier layer, and the drain electrode is arranged at the other end of the active layer and the other end of the barrier layer.

The invention also provides a display panel which is characterized by comprising the thin film transistor.

The thin film transistor, the display panel and the manufacturing method of the thin film transistor have the advantages that the effective butt joint area of the reinforcing part and the active layer is increased, so that the occupied area of the grid layer is reduced, the electrification performance of the active layer is not affected, the penetration rate of the display panel is improved, the parasitic capacitance of the display panel is reduced, and the performances of the thin film transistor and the display panel are improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.

Fig. 1 is a schematic structural diagram of an array substrate according to a first embodiment of the invention;

FIG. 2 is a flow chart of a method for fabricating an array substrate according to a first embodiment of the present invention;

FIG. 3 is a schematic diagram of a semi-finished structure of FIG. 2 illustrating a plurality of reinforcement steps on the top surface of the gate layer;

FIG. 4 is a schematic structural diagram of an array substrate according to a second embodiment of the present invention;

fig. 5 is a flowchart illustrating a method for fabricating an array substrate according to a second embodiment of the invention.

The components in the figure are identified as follows:

1. a substrate, 2, a gate layer, 3, a dielectric layer, 4, an active layer, 5, a source drain layer,

6. a passivation layer 7, a pixel electrode 8, an ultrathin alumina membrane template 9, a barrier layer,

21. a reinforcement part 51, a source electrode 52, a drain electrode 81, a first via hole,

100. and a thin film transistor.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.