阅读说明：本技术 一种芯片结构及其制作与测试方法 (chip structure and its making and testing method ) 是由 任远 刘宁炀 李祈昕 李成果 陈志涛 于 2019-11-26 设计创作，主要内容包括：本申请提供了一种芯片结构及其制作与测试方法,涉及半导体技术领域。该芯片结构包括衬底与衬底逐层连接的多个功能层与功能电极；功能电极设置于功能层远离衬底的一侧；其中,多个功能层中的任意一层设置有通孔；该芯片结构还包括检测电极,检测电极安装于通孔。本申请提供的芯片结构及其制作与测试方法具有能够区分出不同功能层的缺陷性质、物理机制和对芯片特性影响的效果。(The chip structure comprises a substrate, a plurality of functional layers and functional electrodes, wherein the functional layers and the functional electrodes are connected with the substrate layer by layer, the functional electrodes are arranged on a side, far away from the substrate, of the functional layers, through holes are formed in any layer of the functional layers, the chip structure further comprises detection electrodes, and the detection electrodes are arranged in the through holes.)

1, kinds of chip structures, characterized in that, the chip structure includes:

a substrate;

the functional electrode is arranged on the side of the functional layer far away from the substrate, wherein any layers of the functional layers are provided with through holes;

and the detection electrode is arranged on the through hole.

2. The chip structure according to claim 1, wherein any layers of the functional layers are provided with through holes on the periphery, and the detection electrodes are laid on the surfaces of the through holes.

3. The chip structure of claim 1, wherein the plurality of functional layers comprise a buffer layer, a stress relief layer, a high resistance layer, a channel layer, a barrier layer, and a cap layer, the substrate, the buffer layer, the stress relief layer, the high resistance layer, the channel layer, the barrier layer, and the cap layer being stacked layer-by-layer.

4. The chip structure according to claim 3, wherein the plurality of functional layers are all nitride functional layers.

5. The chip structure according to claim 4, wherein the buffer layer is made of AlN, the stress relieving layer is made of AlGaN, the high-resistance layer is made of GaN, the channel layer is made of GaN, the barrier layer is made of AlGaN, and the cap layer is made of GaN.

6, kinds of chip structure manufacturing method, characterized by, the method includes:

providing a substrate;

sequentially extending a plurality of functional layers along the substrate;

fabricating vias in any layers of the plurality of functional layers;

a sensing electrode is fabricated over the via and a function electrode is fabricated at of the plurality of functional layers remote from the substrate.

7. The method of fabricating a chip structure according to claim 6, wherein the step of fabricating vias in any layers of the plurality of functional layers comprises:

and etching the functional layers around the chip structure to a target functional layer.

8, chip performance testing method, wherein the method is applied to the chip structure of any of claims 1 to 5, the method comprises:

controlling the chip structure to be in different working states;

and applying a detection voltage on the detection electrode to test the working characteristics of the chip structure.

9. The chip performance testing method of claim 8, wherein the step of applying a test voltage to the test electrodes to test the operating characteristics of the chip structure comprises:

and applying detection voltage to the detection electrode and the substrate to test the working characteristics of the chip structure.

Technical Field

The invention relates to the technical field of semiconductors, in particular to an chip structure and a manufacturing and testing method thereof.

Background

An epitaxial structure of a High Electron Mobility Transistor (HEMT) includes a plurality of functional layers, and properties such as an energy band structure, a doping characteristic, and defect distribution of each layer are different, and an electrical mechanism of the HEMT is very complex. HEMT device characteristics such as threshold stability, dynamic resistance, reverse leakage and breakdown characteristics, etc. are also affected.

Therefore, it is necessary to perform a test analysis on the HEMT device to analyze the influence of each functional layer on the device parameters.

Currently, uses applied back potential to analyze the effect of bulk material defects on the device, i.e. tests are performed by applying test voltages to the substrate, but such tests have difficulty in distinguishing the defect nature and the influence mechanism of different positions of the epitaxial layer.

Disclosure of Invention

The invention aims to provide chip structures and a manufacturing and testing method thereof, so as to solve the problem that the defect property and the influence mechanism of different functional layers are difficult to distinguish in the prior art.

In order to achieve the above purpose, the embodiments of the present application employ the following technical solutions:

, the present application provides a chip structure comprising:

a substrate;

the functional electrode is arranged on the side of the functional layer far away from the substrate, wherein any layers of the functional layers are provided with through holes;

and the detection electrode is arranged on the through hole.

, through holes are formed in the periphery of any of the functional layers, and the detection electrodes are paved on the surfaces of the through holes.

, the functional layers include a buffer layer, a stress relief layer, a high resistance layer, a channel layer, a barrier layer, and a cap layer, the substrate, the buffer layer, the stress relief layer, the high resistance layer, the channel layer, the barrier layer, and the cap layer being stacked layer-by-layer.

Further , the functional layers are all nitride functional layers.

, the buffer layer is made of AlN, the stress release layer is made of AlGaN, the high resistance layer is made of GaN, the channel layer is made of GaN, the barrier layer is made of AlGaN, and the cap layer is made of GaN.

In a second aspect, the present application further provides methods for manufacturing a chip structure, the method including:

providing a substrate;

sequentially extending a plurality of functional layers along the substrate;

fabricating vias in any layers of the plurality of functional layers;

a sensing electrode is fabricated over the via and a function electrode is fabricated at of the plurality of functional layers remote from the substrate.

, the step of forming vias in any of the plurality of functional layers includes:

and etching the functional layers around the chip structure to a target functional layer.

In a third aspect, the present application further provides chip performance testing methods, where the method is applied to the chip structure described above, and the method includes:

controlling the chip structure to be in different working states;

and applying a detection voltage on the detection electrode to test the working characteristics of the chip structure.

, the step of applying a test voltage to the test electrode to test the operating characteristics of the chip structure includes:

and applying detection voltage to the detection electrode and the substrate to test the working characteristics of the chip structure.

Compared with the prior art, the method has the following beneficial effects:

the application provides a chip structure and a manufacturing and testing method thereof, wherein the chip structure comprises a substrate, a plurality of functional layers and functional electrodes, the functional electrodes are connected with the substrate layer by layer, the functional electrodes are arranged on a side, far away from the substrate, of the functional layers, through holes are formed in any layer of the functional layers, and detection electrodes are arranged in the through holes.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other related drawings can be obtained from the drawings without inventive effort.

Fig. 1 is a cross-sectional view of a chip structure according to an embodiment of the present disclosure.

Fig. 2 is schematic flowcharts of a chip structure manufacturing method according to an embodiment of the present disclosure.

Fig. 3 is another schematic flowcharts of a chip structure manufacturing method according to an embodiment of the present disclosure.

Fig. 4 is schematic flowcharts of a chip performance testing method provided in an embodiment of the present application.

Fig. 5 is another schematic flowcharts of the chip performance testing method according to the embodiment of the present application.

In the figure: 100-chip architecture; 110-a substrate; 120-a buffer layer; 130-a stress release layer; 140-a high resistance layer; 150-a channel layer; 160-barrier layer; 170-a cap layer; 180-functional electrodes; 190-a detection electrode; 200-through hole.

Detailed Description

To further clarify the objects, aspects and advantages of the embodiments of the present application, reference will now be made in detail to the present embodiments of the application illustrated in the accompanying drawings, which form a part hereof, and to show by way of illustration, and not by way of limitation, some embodiments of the application .

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that like reference numerals and letters refer to like items in the following figures, and thus once a item is defined in figures, it need not be further defined and explained by in subsequent figures.

It should be noted that, in this document, relational terms such as , second and the like are only used to distinguish entities or operations from another entities or operations, and no necessarily requires or implies that any such actual relationship or order exists between the entities or operations.

In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships conventionally found in use of products of the application, and are used only for convenience in describing the present application and for simplification of description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application.

In the description of the present application, it should also be noted that unless otherwise expressly stated or limited, the terms "disposed" and "connected" shall be construed , and for example, may be a fixed connection, a removable connection, or a physical connection, a mechanical connection, an electrical connection, a direct connection, an indirect connection via intermediary media, and communication between two elements.

The embodiments of the present application are described in detail below with reference to the drawings, and features of the following examples and embodiments may be combined without conflict.

th embodiment

As described in the background, current analysis of chip structures, , generally uses an applied back potential to analyze the effect of bulk material defects on the device, i.e. tests are performed by applying test voltages to the substrate, but such tests have difficulty in distinguishing the defect properties and the influence mechanism of different positions of the epitaxial layer.

When the device is in a reverse turn-off state, a high electric field can also extend into the whole epitaxial layer along the vertical direction, and charge and discharge of charges can be caused by the dislocation, the defect, the heterojunction structure and other factors of the material, so that the performance of the device is influenced.

It can be understood that the crystal quality, defect distribution, doping concentration, energy band width, surface roughness, polarization degree and other factors of different epitaxial layers are different, and the superposition effect is very complicated to reflect on the working characteristics of the HEMT device. Thus, applying voltages to different functional layers can affect device performance to varying degrees.

In view of this, the present application provides chip structures, which implement applying voltages on different electrodes by providing through holes and detection electrodes on different functional layers, and further analyze defect distributions and physical mechanisms of different epitaxial layers by detecting changes in device characteristics.

Referring to fig. 1, as possible implementation manners of the present application, the chip structure 100 includes a substrate 110, a plurality of functional layers, a functional electrode 180, and a detection electrode 190, wherein the substrate 110 is connected to the functional layers layer by layer, the functional electrode 180 is disposed on a side of the functional layers away from the substrate 110, a through hole 200 is disposed on any layer of the functional layers, and the detection electrode 190 is mounted on the through hole 200.

That is, when the chip structure 100 is fabricated, functional layers are first epitaxially grown on the substrate 110, and the through holes 200 are fabricated, and corresponding electrodes are fabricated at the same time. By applying voltage on different functional layers, the defect properties and influence mechanisms of different positions of the epitaxial layer are researched, and the operation of workers is facilitated.

It should be noted that, as a possible implementation manner of the present application, the substrate 110 described in the present application may be any types of sapphire substrate, silicon carbide substrate, diamond substrate, and gallium nitride homogeneous substrate, and each functional layer is epitaxially formed on the substrate 110, which is not limited in this application.

Moreover, the chip structure 100 provided by the present application may be a HEMT structure, that is, the buffer layer 120, the stress release layer 130, the high resistance layer 140, the channel layer 150, the barrier layer 160, and the cap layer 170 are included in the plurality of functional layers described in the present application, and the substrate 110, the buffer layer 120, the stress release layer 130, the high resistance layer 140, the channel layer 150, the barrier layer 160, and the cap layer 170 are stacked layer by layer, and a gate electrode, a source electrode, and a drain electrode are disposed on the cap layer 170.

As a possible implementation manner of , the functional layers provided In the present application are all nitride functional layers, for example, the material for fabricating the buffer layer 120 is AlN, the material for fabricating the stress relief layer 130 is AlGaN, the material for fabricating the high resistance layer 140 is GaN, the material for fabricating the channel layer 150 is GaN, the material for fabricating the barrier layer 160 is AlGaN, and the material for fabricating the cap layer 170 is GaN.

Moreover, when the via 200 is fabricated, etching is actually performed along the direction from the cap layer 170 to the substrate 110 to expose the target layer, for example, when it is required to determine the influence of voltage applied to the channel layer 150 on the device performance, a portion of the cap layer 170 and the barrier layer 160 may be etched away to expose the channel layer 150, and the detection electrode 190 may be fabricated on the channel layer 150. However, when the chip is turned on or off, a voltage is applied to the detection electrode 190, thereby detecting the influence of the voltage applied to the channel layer 150 on the device performance.

As possible implementation manners of the present application, after testing the influence of different functional layers on the device performance after applying voltage, a plurality of chip structures 100 may be fabricated at the same time, and the through hole 200 of each chip structure 100 is disposed on different functional layers, for example, the through hole 200 is disposed on any layer of the buffer layer 120, the stress release layer 130, the high resistance layer 140, the channel layer 150, and the barrier layer 160.

In addition, as implementation manners of the present application, in order to make the voltage application more uniform, when the through holes 200 are fabricated, the through holes 200 are disposed around any layer of the plurality of functional layers, and the detection electrodes 190 are disposed on the surfaces of the through holes 200. that is, the through holes 200 are disposed around of the chip structure 100, and when the voltage is applied, the voltage can be applied around of the chip, so that the obtained result is more accurate.

Further , applying voltages across the different functional layers as described herein studies the leakage mechanism of the layers and the effect on the device, including but not limited to:

1. and adding high voltage to the detection electrode of the through hole so as to test the working characteristics of the device.

2. And adding high voltage to the detection electrode of the through hole so as to test the electric leakage of the substrate.

3. And adding scanning voltage to the detection electrode of the through hole, changing conditions such as scanning speed, polarity and the like, and testing the working characteristics of the device.

4. And testing capacitance-voltage (C-V) curves between the detection electrode of the through hole and the device electrode, and analyzing the device characteristics.

5. And testing a capacitance-voltage (C-V) curve between the detection electrode of the through hole and the substrate, and analyzing the material characteristics.

6. Various tests are carried out under the condition of variable temperature.

Second embodiment

Referring to fig. 2, the present application further provides a method for manufacturing chip structures, the method includes:

s101, providing substrates.

And S102, sequentially extending a plurality of functional layers along the substrate.

S103, a via hole is made in any layers of the plurality of functional layers.

S104, a detection electrode is manufactured on the through hole, and a function electrode is manufactured on layers far away from the substrate in the plurality of functional layers.

Referring to fig. 3, S103 may include:

and S1031, etching the plurality of functional layers around the chip structure to a target functional layer.

Of course, when the function electrode and the detection electrode are formed, they may be:

depositing source-drain metal and alloy to form ohmic contact, depositing a gate dielectric layer, depositing a gate metal layer, depositing through hole metal and forming contact.

And, the method further comprises depositing a passivation layer, which is not limited in any way in this application.

It should be noted that, in other embodiments, steps of the method for manufacturing the chip structure may be exchanged, for which, this embodiment does not limit the steps of the method for manufacturing the chip structure, and any exchange of steps in other embodiments is included in the scope of the present invention.

Third embodiment

Referring to fig. 4, the present application further provides chip performance testing methods, which are applied to the chip structure described in embodiment , and the methods include:

s201, controlling the chip structure to be in different working states.

S202, applying a detection voltage on the detection electrode to test the working characteristics of the chip structure.

When the chip structure is in different working states, voltages can be applied to different functional layers or substrates so as to test the influence on the performance of the device. The operating characteristics of the chip structure include, but are not limited to, leakage, threshold voltage, turn-on current, etc. of the test chip.

In addition, after a voltage is applied to the function, the current can flow to the cap layer or the substrate, and when the voltage is analyzed to influence the device, the current only needs to flow to the cap layer.

In view of the above, in order to reduce the influence of the current flowing to the substrate, in the present application, referring to fig. 5, S202 may be:

and applying detection voltage to the detection electrode and the substrate to test the working characteristics of the chip structure.

By applying the detection voltage on the detection electrode and the substrate simultaneously, an equipotential can be formed between the functional layer provided with the detection electrode and the substrate, and then after the voltage is applied on the detection electrode, the direction of the current is only towards the capping layer, so that the effect is better.

In summary, the present application provides a chip structure and a method for manufacturing and testing the same, where the chip structure includes a substrate, and a plurality of functional layers and functional electrodes connected to the substrate layer by layer, the functional electrodes are disposed on a side of the functional layers away from the substrate, where any layers of the plurality of functional layers are provided with through holes, and detection electrodes are mounted in the through holes.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

It will thus be seen that the embodiments are illustrative and non-limiting in all respects , the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.