阅读说明：本技术 低压降电压稳压器 (Low dropout voltage regulator ) 是由 何仪修 于 2018-06-28 设计创作，主要内容包括：一种低压降电压稳压器,包含一主要误差放大器、一辅助误差放大器、一第一缓冲电路、一第二缓冲电路、一控制电路以及一N通道功率晶体管。该辅助误差放大器比该主要误差放大器消耗较少的电流。该控制电路用以比较比例于一输出电压的一反馈电压的电压值和一偏压电压的电压值以控制该N通道功率晶体管的导通状况。该参考电压的电压值大于该偏压电压的电压值。(A low dropout voltage regulator includes a main error amplifier, an auxiliary error amplifier, a first buffer circuit, a second buffer circuit, a control circuit and an N-channel power transistor. The auxiliary error amplifier consumes less current than the main error amplifier. The control circuit is used for comparing a voltage value of a feedback voltage which is proportional to an output voltage with a voltage value of a bias voltage so as to control the conduction state of the N-channel power transistor. The voltage value of the reference voltage is greater than the voltage value of the bias voltage.)

1. A low dropout voltage regulator comprising:

an N-channel power transistor having a drain for receiving a power supply voltage and a source for generating an output voltage;

a main error amplifier having a positive input for receiving a feedback voltage proportional to the output voltage, a negative input for receiving a reference voltage, and an amplified output;

a first buffer circuit coupled between the amplified output of the main error amplifier and a gate of the N-channel power transistor;

an auxiliary error amplifier having a first positive input terminal for receiving the feedback voltage proportional to the output voltage, a second positive input terminal for receiving a negative input terminal of the reference voltage, and an amplified output terminal;

a second buffer circuit coupled between the amplified output of the auxiliary error amplifier and the gate of the N-channel power transistor; and

a control circuit for comparing a voltage value of the feedback voltage proportional to the output voltage with a voltage value of a bias voltage to control the gate of the N-channel power transistor;

wherein the auxiliary error amplifier consumes less current than the main error amplifier; and

wherein the voltage value of the reference voltage is greater than the voltage value of the bias voltage.

2. The low dropout voltage regulator of claim 1, wherein the first buffer circuit comprises:

a P-channel transistor having a source coupled to the gate of the N-channel power transistor, a gate coupled to the amplified output of the main error amplifier, and a drain coupled to a ground; and

a current source coupled to the source of the P-channel transistor.

3. The low dropout voltage regulator of claim 1, wherein the second buffer circuit comprises:

a first output stage having an input coupled to the amplified output of the auxiliary error amplifier and an output coupled to the amplified output of the main error amplifier; and

a second output stage having an input coupled to the amplified output of the auxiliary error amplifier and an output coupled to the gate of the N-channel power transistor.

4. The low dropout voltage regulator of claim 3, wherein the first output stage comprises:

a first N-channel transistor having a gate coupled to the amplified output of the auxiliary error amplifier, a drain coupled to the amplified output of the main error amplifier, and a source coupled to the ground.

5. The low dropout voltage regulator of claim 3, wherein the second output stage comprises:

a second N-channel transistor having a gate coupled to the amplified output of the auxiliary error amplifier, a drain coupled to the gate of the N-channel power transistor, and a source coupled to the ground; and

a first capacitor coupled between the gate of the N-channel power transistor and the gate of the second N-channel transistor.

6. The low dropout voltage regulator of claim 1, wherein the control circuit comprises:

a comparator for comparing a voltage value of the feedback voltage proportional to the output voltage with a voltage value of the bias voltage to generate a comparison signal; and

an output stage having an input for receiving the comparison signal and an output coupled to the second positive input of the auxiliary error amplifier.

7. The low dropout voltage regulator of claim 6, wherein the output stage of the control circuit comprises:

a third N-channel transistor having a gate for receiving the comparison signal and a drain coupled to the second positive input of the auxiliary error amplifier;

a capacitor coupled to the drain of the third N-channel power transistor; and

a current source coupled to a source of the third N-channel transistor.

8. The LDO of claim 1, wherein during soft start, the reference voltage is first reset to 0V and then begins to rise with a first constant slope; when the voltage value of the feedback voltage proportional to the output voltage is smaller than the voltage value of the bias voltage, the auxiliary error amplifier, the second buffer circuit and the N-channel power transistor form a first negative feedback path, so that the voltage value of the feedback voltage proportional to the output voltage is the same as the voltage value of the reference voltage.

9. The low dropout voltage regulator of claim 8, wherein the main error amplifier, the first buffer circuit and the N-channel power transistor form a second negative feedback path that makes the voltage value of the feedback voltage proportional to the output voltage and the voltage value of the reference voltage the same when the voltage value of the feedback voltage proportional to the output voltage is greater than the voltage value of the bias voltage.

10. The low dropout voltage regulator of claim 8, wherein the control circuit sends a control signal falling with a second constant slope to the second positive input of the auxiliary error amplifier when the voltage value of the feedback voltage proportional to the output voltage rises to the voltage value of the bias voltage, and the second negative feedback path is enabled and the first negative feedback path is disabled when the voltage value of the control signal is less than the voltage value of the feedback voltage proportional to the output voltage.

Technical Field

The present invention relates to a low dropout voltage regulator (low drop out voltage regulator), and more particularly, to a low dropout voltage regulator having a controllable slow start mechanism.

Background

The low dropout voltage regulator is a direct current linear voltage regulator (DC linear voltage regulator) having a small difference between input and output voltages. Advantages of the LDO include lower supply voltage, high operating efficiency, and low heat dissipation. The components of a typical low dropout voltage regulator include a power transistor and an error amplifier. The low dropout voltage regulator can maintain a stable output voltage value through a negative feedback loop formed by the power transistor and the error amplifier.

However, the LDO may damage internal components or cause damage to the load if it is not well controlled when the supply voltage is initially supplied. For example, during the soft start, if the error amplifier detects that the output voltage has not reached the expected voltage value, the power transistor will be overdriven to generate an inrush current (inrush), or a voltage overshoot (overshot) occurs after the end of the soft start. Both inrush current and voltage overshoot may cause damage to internal components of the low dropout voltage regulator or to the load. Therefore, it is desirable to provide a low dropout voltage regulator having a controllable slow start mechanism to solve the above problems.

Disclosure of Invention

According to an embodiment of the present invention, a low dropout voltage regulator includes a main error amplifier, an auxiliary error amplifier, a first buffer circuit, a second buffer circuit, a control circuit, and an N-channel power transistor. The N-channel power transistor has a drain for receiving a power supply voltage and a source for generating an output voltage. The main error amplifier has a positive input terminal for receiving a feedback voltage proportional to the output voltage, a negative input terminal for receiving a reference voltage, and an amplified output terminal. The first buffer circuit is coupled between the amplified output of the main error amplifier and a gate of the N-channel power transistor. The auxiliary error amplifier has a first positive input terminal for receiving the feedback voltage proportional to the output voltage, a second positive input terminal for receiving the reference voltage, and an amplified output terminal. The second buffer circuit is coupled between the amplified output of the auxiliary error amplifier and the gate of the N-channel power transistor. The control circuit is used for comparing the voltage value of the feedback voltage which is proportional to the output voltage with the voltage value of a bias voltage so as to control the grid electrode of the N-channel power transistor. The auxiliary error amplifier consumes less current than the main error amplifier. The voltage value of the reference voltage is greater than the voltage value of the bias voltage.

Drawings

FIG. 1 is a block diagram of a LDO incorporating an embodiment of the present invention.

FIG. 2 shows a circuit diagram of a low dropout voltage regulator incorporating another embodiment of the present invention.

FIG. 3 shows a circuit diagram of a control circuit incorporating an embodiment of the invention.

Detailed Description

Certain terms are used throughout the description and following claims to refer to particular components. As one of ordinary skill in the art will appreciate, manufacturers may refer to a component by different names. This specification and the claims that follow do not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Also, the term "coupled" is intended to include any direct or indirect electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

Fig. 1 shows a block diagram of a low dropout voltage regulator 100 incorporating an embodiment of the present invention. Referring to fig. 1, the low dropout voltage regulator 100 includes a main error amplifier OP1, a first buffer circuit 12, an N-channel power transistor MN, and a voltage divider circuit 18.

Referring to fig. 1, the N-channel power transistor MN has a drain coupled to a power supply voltage VDD and a source coupled to the voltage divider 18 and an output capacitor CL.

A negative input terminal of the main error amplifier OP1 is used for receiving a reference voltage VREF. In one embodiment, the reference voltage VREF is generated by a bandgap circuit (not shown), and has a voltage value of about 1.2V. The voltage divider circuit 18 includes resistors R1 and R2. The resistors R1 and R2 divide an output voltage OUT of the low dropout voltage regulator 100 to generate a feedback voltage FB proportional to the output voltage OUT. The feedback voltage FB is transmitted to a positive input terminal of the main error amplifier OP 1. The main error amplifier OP1 is used for comparing the voltage values of the reference voltage VREF and the feedback voltage FB to generate an error signal N1. The first buffer circuit 12 is coupled to an output terminal of the main error amplifier OP1, and is used for shifting the voltage value of the error signal N1 to drive the N-channel power transistor MN.

In normal operation, i.e., after the soft start ends, the main error amplifier OP1 drives a gate terminal of the N-channel power transistor MN through the first buffer circuit 12 to provide a stable output voltage OUT. In this case, the main error amplifier OP1, the first buffer circuit 12 and the N-channel power transistor MN form a first negative feedback path. The first negative feedback path makes the voltage value of the feedback voltage FB and the voltage value of the reference voltage VREF substantially the same. Therefore, the voltage value of the output voltage OUT is proportional to the voltage value of the reference voltage VREF according to the resistance values of the resistors R1 and R2.

However, during the soft start, when the power voltage VDD starts to be supplied, the first buffer circuit 12 raises the voltage level of the node N2 from the ground potential to a voltage level, such as a gate-source voltage difference VGS of a transistor. Therefore, the N-channel power transistor MN is turned on to generate a surge current, thereby causing damage to the components. To solve this problem, the LDO 100 needs another feedback path to control the conduction of the N-channel power transistor MN.

Referring to fig. 1, to add another feedback path, the low dropout voltage regulator 100 further includes an auxiliary error amplifier OP2, a second buffer circuit 14 and a control circuit 16. The auxiliary error amplifier OP2 consumes less current than the main error amplifier OP1 requiring a complicated design because it does not additionally perform temperature compensation or process differentiation or operate at high speed. In one embodiment of the present invention, the current consumed by the auxiliary error amplifier OP2 is less than 10 μ a.

Referring to fig. 1, the control circuit 16 is used for comparing the voltage value of the feedback voltage FB with the voltage value of a bias voltage VB to generate a control signal FBX. A first positive input terminal of the auxiliary error amplifier OP2 is configured to receive the feedback voltage FB, a second positive input terminal is configured to receive the control signal FBX, and a negative input terminal is configured to receive the reference voltage VREF. An input terminal of the second buffer circuit 14 is coupled to the output terminal of the auxiliary error amplifier OP2, and is used for shifting a voltage value of an error signal N3. An output terminal of the second buffer circuit 14 is coupled to the gate of the N-channel power transistor MN.

FIG. 2 shows a circuit diagram of a low dropout voltage regulator 100' incorporating another embodiment of the present invention. Referring to fig. 2, the first buffer circuit 12 includes a P-channel transistor M2 and a current source I1, wherein the P-channel transistor M2 has a drain terminal coupled to a ground terminal, a gate terminal coupled to the output terminal of the main error amplifier OP1, and a source terminal coupled to the current source I1.

The second buffer circuit 14 includes a first output stage 144 and a second output stage 146. The first output stage 144 has an input coupled to the output of the auxiliary error amplifier OP2 and an output coupled to the second output stage 146. The second output stage 146 has an output terminal coupled to the gate terminal of the N-channel power transistor MN.

In one embodiment, the first output stage 144 includes an N-channel transistor M4. The N-channel transistor M4 has a drain coupled to the output of the main error amplifier OP1, a gate for receiving the error signal N3, and a source coupled to the ground.

In one embodiment, the second output stage 146 includes an N-channel transistor M3 and a capacitor C1. The N-channel transistor M3 has a gate for receiving the error signal N3, a drain coupled to the gate of the N-channel power transistor MN, and a source coupled to the ground. The capacitor C1 is coupled between the gate of the N-channel power transistor MN and the gate of the N-channel transistor M3.

Referring to fig. 2, the control circuit 16 includes a comparator CMP and an output stage 162. The comparator CMP is used for comparing the voltage value of the feedback voltage FB with the voltage value of the bias voltage VB to generate a comparison signal CMPX. An output terminal of the comparator CMP is coupled to an input terminal of the output stage 162.

In one embodiment, the output stage 162 includes an N-channel transistor M7, an enabling element X2, a current source I3, and a capacitor C2. The N-channel transistor M7 has a gate for receiving the comparison signal CMPX, a drain coupled to the enable element X2, and a source coupled to the current source I3. In one embodiment, the enabling element X2 is comprised of a P-channel transistor M6, as shown in FIG. 3. The P-channel transistor M6 has a source for receiving the power voltage VDD, a gate for receiving an enable signal EN, and a drain coupled to the drain of the N-channel transistor M7.

Referring to fig. 2, during a soft start, when the power voltage VDD starts to be supplied, the voltage value of the reference voltage VREF in the low dropout voltage regulator 100' is first reset to 0V (ground voltage value). At this time, the voltage value of the feedback voltage FB is smaller than the voltage value of the bias voltage VB (about 0.3V), so the comparator CMP outputs a signal CMPX of logic 0, and the N-channel transistor M7 is turned off. When the N-channel transistor M7 is turned off, the enabling element X2 pulls the control signal FBX up to the voltage level of the power voltage VDD so that the voltage level of the control signal FBX is greater than the voltage level of the feedback signal FB. At this time, the voltage value of the reference voltage VREF is small, so the auxiliary error amplifier OP2 outputs an error signal N3 of logic 1.

When the auxiliary error amplifier OP2 outputs the logic 1 error signal N3, the transistor M4 is turned on, so that the voltage at the node N1 is pulled down to ground. At the same time, the transistor M3 is turned on, so that the voltage at the node N2 is pulled down to ground. Therefore, the N-channel power transistor MN is turned off. Since the N-channel power transistor MN is turned off, the output voltage OUT is kept pulled down to the ground potential when the power voltage VDD starts to be supplied.

Then, the reference voltage VREF starts to rise with a constant slope. When the voltage of the feedback signal FB is less than the voltage of the bias voltage VB, the auxiliary error amplifier OP2, the N-channel transistor M3, the capacitor C1 and the N-channel power transistor MN form a second negative feedback path in the second buffer circuit 14. The second negative feedback path makes the voltage value of the feedback voltage FB and the voltage value of the reference voltage VREF substantially the same.

When the voltage level of the feedback signal FB rises to a level close to the bias voltage VB, the comparator CMP outputs a signal CMPX of logic 1, turning on the N-channel transistor M7. When the N-channel transistor M7 is turned on, the current source I3 discharges the capacitor C2, so that the voltage of the control signal FBX starts to decrease with a constant slope. When the voltage value of the control signal FBX is smaller than the voltage value of the feedback signal FB, the auxiliary error amplifier OP2 outputs an error signal N3 of logic 0, turning off the transistors M3 and M4. Therefore, the N-channel power transistor MN is instead driven by the first negative feedback path, while the second negative feedback path is not enabled.

In summary, by alternately starting the first negative feedback path and the second negative feedback path, the low dropout voltage regulator disclosed by the invention can avoid damage caused by inrush current and voltage overshoot because of the controllable slow start mechanism.

While the foregoing has been with reference to the disclosure of the present invention, it will be appreciated by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims. Accordingly, the scope of the present invention should not be limited to the embodiments disclosed, but should include various alternatives and modifications without departing from the invention, which are encompassed by the following claims.

[ notation ] to show

100. 100' low dropout voltage regulator

12 first buffer circuit

14 second buffer circuit

144 first output stage

146 second output stage

16. 16' control circuit

162 output stage

18 voltage divider circuit

CMP comparator

C1, C2 capacitor

CL capacitor

I1 and I3 current sources

M2, M6P channel transistor

M3, M4 and M7N channel transistor

MN N-channel power transistor

OP1 main error amplifier

OP2 auxiliary error amplifier

R1, R2 resistance

X2 enabling assembly