阅读说明：本技术 结合工艺、封装工艺及制造方法 (Bonding process, packaging process and manufacturing method ) 是由 陈俊廷 吴志伟 卢思维 施应庆 于 2018-12-07 设计创作，主要内容包括：提供一种封装工艺、结合工艺与制造方法。提供具有第一管芯及第二管芯的封装。提供具有第一翘曲水平的电路衬底。将封装安装到电路衬底上,且然后在高温下进行加热以将封装结合到电路衬底。在所述高温下被加热的所述封装以第二翘曲水平而翘曲,且第一翘曲水平与第二翘曲水平实质上相符。(A packaging process, a bonding process and a manufacturing method are provided. A package having a first die and a second die is provided. A circuit substrate having a first warpage level is provided. The package is mounted to the circuit substrate and then heated at an elevated temperature to bond the package to the circuit substrate. The package heated at the elevated temperature is warped at a second warpage level, and the first warpage level and the second warpage level substantially coincide.)

1. A bonding process, comprising:

disposing a circuit substrate on a jig, wherein the circuit substrate has a mounting surface and a mounting portion formed on the mounting surface;

performing a substrate padding process;

mounting a package onto the mounting surface of the circuit substrate, wherein the package has a bottom surface and connections formed on the bottom surface of the package; and

performing a reflow process and bonding the connector of the package to the mounting part of the circuit substrate.

Technical Field

Embodiments of the invention relate to bonding processes, packaging processes, and methods of manufacture.

Background

In advanced assembly designs, semiconductor packages and multi-chip packages are further connected to circuit substrates by surface mount or flip-chip bonding techniques. Since the package is surface mounted to the substrate by conductive bumps or balls, the reliability of the contact connections is critical.

Disclosure of Invention

According to an embodiment of the present invention, a bonding process is provided. A circuit substrate is disposed on a jig, and the circuit substrate has a mounting surface and a mounting portion formed on the mounting surface. And executing a substrate padding process. Mounting a package onto the mounting surface of the circuit substrate. The package has a bottom surface and a connector formed on the bottom surface of the package. Performing a reflow process and bonding the connector of the package to the mounting part of the circuit substrate.

Drawings

The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 through 10 are schematic cross-sectional views of various stages in a method of manufacturing a package structure according to some example embodiments of the invention.

Fig. 11 is a schematic cross-sectional view illustrating a package and a circuit substrate disposed on a platform and reflowed in accordance with an embodiment of the present invention.

Fig. 12-15 are schematic diagrams illustrating the location and size of spacers according to some embodiments of the invention.

Fig. 16 is a schematic top view illustrating a substrate holder according to an embodiment of the present invention.

Fig. 17 is a schematic cross-sectional view illustrating a package and a circuit substrate disposed on a platform and reflowed in accordance with an embodiment of the present invention.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and configurations are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of description, spatially relative terms such as "under.," (below), "(lower)," (above), "(upper)," or the like, may be used herein to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as such.

The present invention may also include other features and processes. For example, test structures may be included to facilitate verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit (3 DIC) devices. The test structure may, for example, include test pads formed in a redistribution layer or on a substrate that allows for testing of 3D packages or 3 DICs, for use of probes and/or probe cards, and the like. Verification tests may be performed on the intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used with test methods that include intermediate verification of known good dies to improve yield and reduce cost.

For the embodiments provided herein, the techniques may be discussed in a specific context, namely, disposing spacers under a package substrate or circuit substrate during a heating process for bonding the package structure and the package substrate or circuit substrate together. By the arrangement and layout design of the spacers, the circuit substrate is bowed, arched, or bent with one or more curvatures corresponding to the warpage of the package structure during the heating process. This enables a more reliable package structure by reducing the likelihood of cold junction or bump bridging between the package and the circuit substrate or package substrate. In some embodiments, the spacer may be positioned in a region under the primary chip that is packaged within the package structure. In some embodiments, the spacer may be positioned in a region under a companion chip (trim chip) that is packaged within the package structure. The spacers may allow for better control of the bonding of the contacts between the package and the circuit substrate and achieve superior reliability of the bonded contacts. The spacers control the warpage level of the circuit substrate to match the warpage level of the package structure, thereby reducing the effects of warpage due to Coefficient of Thermal Expansion (CTE) mismatch. In some embodiments, the active die is a stack formed by one or more dies (e.g., a logic die stack or a memory die stack). In these embodiments, the material, amount, size, and/or location of the spacers may not be limited to the descriptions provided in the embodiments, as long as the spacers can provide spacing and support for the package substrate or the circuit substrate.

The packaging process may include forming a multi-Chip package structure using a Chip-on-Wafer-on-Substrate (CoWOS) packaging process. Other embodiments may also include other processes including integrated fan-out (InFO) encapsulation processes. The embodiments described herein are intended to provide examples to enable making or using the subject matter of this disclosure, and one of ordinary skill in the art will readily appreciate modifications that may be made while remaining within the intended scope of different embodiments. Like reference numbers and characters in the following figures refer to like components. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

Fig. 1 through 10 are schematic cross-sectional views of various stages in a method of manufacturing a package structure according to some example embodiments of the invention.

In fig. 1, an interposer 200 is provided. In some embodiments, interposer 200 includes substrate 202, through holes 204 in substrate 202, and conductive pads 206. In some embodiments, the substrate 202 may include a bulk semiconductor substrate, a Silicon On Insulator (SOI) substrate, or a multi-layer semiconductor material substrate. The semiconductor material of the substrate 202 may be silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof. In some embodiments, the substrate 202 may be doped or undoped. In some embodiments, the conductive pads 206 are formed on the first surface 202a of the interposer 200. In some embodiments, the through-holes 204 are formed in the substrate 202 and connected to the conductive pads 206. In some embodiments, the perforations 204 extend into the substrate 202 at a particular depth. In some embodiments, the through-holes 204 are substrate through-holes. In some embodiments, when the substrate 202 is a silicon substrate, the through-holes 204 are through-silicon-vias. In some embodiments, the perforations 204 may be formed by forming holes or grooves in the substrate 202 and then filling the grooves with a conductive material. In some embodiments, the grooves may be formed by, for example, etching, milling, laser drilling, and the like. In some embodiments, the conductive material may be formed by an electrochemical plating process, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD), and may include copper, tungsten, aluminum, silver, gold, or a combination thereof. In some embodiments, the conductive pads 206 connected to the vias 204 may be formed as conductive portions of a redistribution layer formed on the interposer 200. In some embodiments, the conductive pads 206 include Under Bump Metallurgy (UBM).

In some embodiments, interposer 200 may further include active or passive devices, such as transistors, capacitors, resistors, or diodes, formed in substrate 202.

In fig. 1, a first die 12 and a second die 14 are provided. In some embodiments, the first die 12 and the second die 14 are separate dies singulated from the wafer. In some embodiments, each first die 12 includes the same circuitry, e.g., devices and metallization patterns, or each first die 12 is the same type of die. In some embodiments, each second die 14 contains the same circuitry, or each second die 14 is the same type of die. In some embodiments, the first die 12 and the second die 14 have different circuitry or are different types of dies. In an alternative embodiment, the first die 12 and the second die 12 may have the same circuitry.

In some embodiments, the first die 12 may be a primary die while the second die 14 is a secondary die. From the perspective of the packaging unit PKU defined between the Scribe Lanes (SL), the primary die is arranged on the interposer 200 in a central location of the packaging unit PKU, while the secondary die is arranged side-by-side and spaced apart from the primary die. In some embodiments, the secondary die is alongside and arranged around or surrounding the primary die. In one embodiment, four or six secondary dies are arranged around one primary die in each package unit PKU. In some embodiments, the first die 12 has a surface area that is greater than a surface area of the second die 14. Furthermore, in some embodiments, the first die 12 and the second die 14 may be different sizes, including different surface areas and/or different thicknesses. In some embodiments, the first die 12 may be a logic die including a Central Processing Unit (CPU) die, a Graphics Processing Unit (GPU) die, a system-on-a-chip (SoC) die, a microcontroller, or the like. In some embodiments, the first die 12 is a power management die, such as a Power Management Integrated Circuit (PMIC) die. In some embodiments, the second die 14 may be a memory die, including a Dynamic Random Access Memory (DRAM) die, a Static Random Access Memory (SRAM) die, or a High Bandwidth Memory (HBM) die. In some embodiments, the first die 12 includes a body 120 and connection pads 122 formed on an active surface 121 of the body 120. In some embodiments, the connection pads 122 may further include post structures for bonding the die 12 to other structures. In some embodiments, the second die 14 includes a body 140 and connection pads 142 formed on an active surface 141 of the body 140. In other embodiments, the connection pads 142 may further include post structures for bonding the die 14 to other structures.

In fig. 1, first die 12 and second die 14 are attached to first surface 202a of interposer 200 via conductive contacts 230, for example, by flip-chip bonding. Conductive contacts 230 are formed between the connection pads 122, 142 and the conductive pads 206 by a reflow process to electrically and physically connect the dies 12, 14 and the interposer 200. In some embodiments, the conductive contacts 230 are micro-bumps, such as micro-bumps with copper metal pillars. In another embodiment, the conductive contacts 230 are solder bumps or micro-bumps, lead-free solder bumps or micro-bumps, such as controlled collapse chip connection (C4) bumps or micro-bumps. The conductive contacts 230 electrically connect the first and second dies 12, 14 to the vias 204 of the interposer 200 through the connection pads 122, 142 and the conductive pads 206.

In some embodiments, the bond between the dies 12, 14 and the interposer 200 may be a solder bond. In some embodiments, the bond between the dies 12, 14 and the interposer 200 may be a direct intermetallic bond, such as an inter-copper bond. In some embodiments, an underfill material (not shown) may be applied to the gap between the die 12, 14 and the interposer 200 around the conductive contacts 230.

In fig. 2, an encapsulant 240 is formed over the interposer 200 covering the first and second dies 12, 14 and the conductive contacts 230. In some embodiments, the encapsulant 240 may be a molding compound. In some embodiments, the encapsulant 240 comprises an epoxy and may be formed by compression molding or transfer molding. In one embodiment, a curing process is performed to cure the encapsulant 240. In some embodiments, the first and second dies 12, 14 and the conductive contacts 230 are encapsulated by an encapsulant 240. In some embodiments, a planarization process including grinding or polishing may be performed to partially remove the encapsulant 240, exposing the backside surfaces 12s, 14s of the first and second dies 12, 14. Thus, the backside surfaces 12s, 14s of the first die 12 and the second die 14 are flush with the top surface 204a of the encapsulation 240.

In fig. 3, the structure shown in fig. 2 is inverted or flipped and placed on the carrier C such that the carrier C directly contacts the backside surfaces 12s, 14s of the first and second dies 12, 14 and the top surface 204a of the encapsulant 240. As shown in fig. 3, at this processing stage, interposer 200 has not been thinned and has a thickness T1.

In fig. 4, a thinning process is performed on the interposer 200 to partially remove or thin the substrate 202 of the interposer 200 until the through-holes 204 are exposed and the second surface 202b of the interposer is formed. In some embodiments, the thinning process may include a back grinding process, a polishing process, or an etching process. In some embodiments, after the thinning process, interposer 200 is thinned to thickness T2. In some embodiments, the ratio of thickness T2 to thickness T1 is in the range of about 0.1 to about 0.5.

In fig. 5, a redistribution structure 300 is formed on the second surface 202b of the substrate 202 (interposer 200). In some embodiments, the redistribution structure 300 is electrically connected with the through-hole 204 and/or electrically connects the through-hole 204 with an external device. In some embodiments, the redistribution structure 300 includes at least one dielectric layer 302 and a metallization pattern 304 in the dielectric layer 302. In some embodiments, the metallization pattern 304 may include pads, vias and/or traces to interconnect with the vias 204 and further connect the vias 204 to one or more external devices. Although one dielectric layer is shown in fig. 5 and the following figures, more than one dielectric layer may be included within the redistribution structure. In some embodiments, the material of the dielectric layer 302 includes silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or a low dielectric constant (low-K) dielectric material (e.g., a phosphosilicate glass material, a fluorosilicate glass material, a borophosphosilicate glass material, SiOC, a spin-on-glass material, a spin-on-polymer, or a silicon-carbon material). In some embodiments, the dielectric layer 302 may be formed by spin-on coating or deposition (including Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), high density plasma-chemical vapor deposition (HDP-CVD)), or the like. In some embodiments, metallization pattern 304 includes metal Under Bump Metallurgy (UBM). In some embodiments, the formation of the metallization pattern 304 may include patterning the dielectric layer and filling metallic material into openings of the patterned dielectric layer using photolithography techniques and one or more etching processes. Any excess conductive material on the dielectric layer may be removed, for example, by using a chemical mechanical polishing process. In some embodiments, the material of metallization pattern 304 includes copper, aluminum, tungsten, silver, and combinations thereof.

In fig. 6, electrical connections 350 are disposed on metallization pattern 304 and electrical connections 350 are electrically coupled to vias 204. In some embodiments, electrical connections 350 are placed on top surface 300s of rerouting structure 300 and positioned on metallization pattern 304. In some embodiments, electrical connections 350 include lead-free solder balls, Ball Grid Array (BGA) balls, bumps, C4 bumps, or micro bumps. In some embodiments, electrical connections 350 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof. In some embodiments, electrical connection 350 is formed by: a solder paste is formed on the re-wiring structure 300 by, for example, evaporation, plating, printing, or solder transfer, and then reflowed into a desired bump shape. In some embodiments, electrical connections 350 are placed on rerouting structure 300 by ball bonding or the like. In other embodiments, electrical connection 350 is formed by: a non-solder metal pillar (e.g., a copper pillar) is formed by sputtering, printing, electroless plating or electroplating, or chemical vapor deposition, and then a lead-free cap layer is formed by plating on the metal pillar.

Electrical connection 350 may be used to join to an external device or additional electrical components. In some embodiments, electrical connections 350 are for bonding to a circuit substrate, a semiconductor substrate, or a package substrate.

In fig. 7, a singulation process is performed to cut the package structure shown in fig. 6 into a plurality of packages 70 along the cutting lines SL around the package units PKU. Each package 70 includes at least one first die 12, more than one second die 14, an encapsulation 240 surrounding the first die 12 and the second die 14, conductive contacts 230, through-holes 204, a redistribution structure 300 including a dielectric layer 302 and a metallization pattern 304 (in fig. 7, the singulated redistribution structure is also referred to as a redistribution structure), and electrical connections 350 disposed on a surface 300s of the redistribution structure 300. In some embodiments, the singulation process may include a sawing process (sawing process) or a dicing process (dicing process).

After the singulation process, the package 70 is detached from the carrier C, and the carrier C is removed. In a subsequent process, the package 70 may be flipped over and further mounted on a circuit substrate or a package substrate.

In fig. 8, a circuit substrate 80 having a mounting portion 802 thereon is set to a substrate holder SF mounted on a stage PT. In some embodiments, the substrate holder SF may be a plate holder having more than one holder unit SFU (as seen in fig. 16). In some embodiments, the circuit substrate 80 may be placed onto the substrate holder SF and assembled into one holder unit SFU. In some embodiments, the circuit substrate 80 may include build-up substrates (build-up substrates), circuit boards (e.g., Printed Circuit Boards (PCBs)), and the like. In some embodiments, the mounting portion 802 may include a pre-solder formed on the pads of the circuit substrate. Additionally, the circuit substrate 80 may further include electrical contacts or other electrical components therein. In addition, at least one package 70 is provided. In fig. 8, the package 70 is disposed with its bottom surface 70BS facing the circuit substrate 80. In fig. 8, although one package 70 and one circuit substrate 80 are illustrated, a plurality of packages and a plurality of circuit substrates may be used. In some embodiments, the package 70 (and the dies 12, 14) may become slightly warped prior to the reflow process, but the degree of warpage of the package 70 is less than the degree of warpage of the package 70 when subjected to the reflow process (see fig. 9) as shown in fig. 8 (i.e., prior to the reflow process). In some embodiments, a substrate padding process is performed to adjust the geometry, topology, or curvature of circuit substrate 80 prior to placing package 70 onto circuit substrate 80 and prior to placing circuit substrate 80 onto substrate holder SF. During the substrate shimming process, one or more spacers 85 may be placed on the gripper unit SFU of the substrate gripper SF. After circuit substrate 80 is placed onto substrate holder SF, spacers 85 are positioned below circuit substrate 80 and between circuit substrate 80 and substrate holder SF to form at least one space or gap G between circuit substrate 80 and substrate holder SF. In some other embodiments, spacer 85 may be inserted between circuit substrate 80 and substrate holder SF after placing circuit substrate 80 onto substrate holder SF. By performing the substrate padding process, the spacers 85 elevate the vertical position of a specific portion of the circuit substrate 80, and change the substantially flat circuit substrate (substantially flat or flat with respect to the mounting surface of the stage PT) into the bent circuit substrate 80. That is, the circuit substrate 80 is a warped circuit substrate. In some embodiments, the warped circuit substrate has a curved surface CV1, and the mounting portions on the curved surface CV1 are arranged along the curved surface CV 1. From the cross-sectional view of fig. 8 (a cross-section taken as a normal plane cut through the curved surface), the curve C1 (shown as a dashed line) of curved surface CV1 is seen, and the curvature of such curve of curved surface CV1 can be expressed as a radius of curvature. In some embodiments, the curved surface CV1 (i.e., the bent portion or warp of the circuit substrate 80) may be expressed as a combination of curvatures in a normal cross-section. In some embodiments, the curved surface CV1 (warp) of the warped circuit substrate 80 is expressed as a deviation distance measured from the deformation plane with respect to the reference plane (mounting plane of the SFU). In fig. 8, the spacer 85 is arranged at the center position of the chuck unit SFU, and the circuit substrate 80 bows and becomes convex (so-called crying shape) by shimming of the spacer 85. In one embodiment, since one circuit substrate is assembled to one jig unit, the spacer arranged at the center position of the jig unit is also located at the center position of the circuit substrate.

In fig. 9, the package 70 is placed on a circuit substrate 80 and a reflow process RFL is performed. In some embodiments, package 70 is picked and placed over the top surface of circuit substrate 80, and electrical connections 350 on bottom surface 70BS of package 70 are aligned with and disposed on mounting portions 802 of circuit substrate 80. A reflow process is performed as part of the bonding process for the package 70 and the circuit substrate 80 to bond the electrical connectors 350 to the mounting portions 802. In some embodiments, the reflow process includes performing a heating process on the electrical connector 350 and the mounting portion 802 at the reflow temperature such that the electrical connector 350 becomes a molten or semi-molten state to be integral and bonded with the mounting portion 802 of the circuit substrate 80. The reflow temperature of the electrical connector 350 needs to be higher than the melting point of the electrical connector 350. In one embodiment, the electrical connections are C4 bumps, and the reflow temperature is in a range from 210 degrees celsius to 250 degrees celsius. In one embodiment, the electrical connections are solder balls or lead-free solder balls and the reflow temperature is in a range of 200 degrees Celsius to 260 degrees Celsius.

In some embodiments, the package 70 has a first die 12 and a second die 14 surrounding the first die 12. During the reflow process, under thermal shock, the package 70 (and the dies 12, 14) become warped due to CTE mismatch, and the warpage of the package 70 coincides with the warpage prearranged for the circuit substrate 80. In some embodiments, the geometry of warped package 70 corresponds and conforms to the geometry of warped circuit substrate 80. In some embodiments, the package 70 bows and becomes convex (crying shape). In some embodiments, as package 70 becomes warped, bottom surface 70BS of package 70 with electrical connectors thereon becomes curved surface CV2 and electrical connectors 350 are arranged along curved surface CV 2. From the cross-sectional view of fig. 9 (a cross-section taken as a normal plane cut through the curved surface), the curve C2 (shown as a dashed line) of curved surface CV2 is seen, and the curvature of such curve of curved surface CV1 can be expressed as a radius of curvature. In some embodiments, the curvature of curve C1 is substantially the same as the curvature of curve C2, and curve C1 is the same type of parallel curve as curve C2. In some embodiments, curved surface CV1 is parallel to curved surface CV 2. That is, the curved surface CV1 of the circuit substrate 80 and the curved surface CV2 of the package 70 are parallel to each other and spaced apart with a constant interval (distance) therebetween. Thus, the electrical connectors 350 may be precisely aligned and bonded together with the corresponding mounting portions 802. After the bonding process, an intermetallic compound (not shown) may be formed in the joint 380.

In some embodiments, the spacers 85 located on the clip unit SFU are located under the circuit substrate 80 at a location corresponding to the location of the first die 12 of the package 70. In one embodiment, along the vertical direction (in fig. 9, the vertical direction), the location of the spacer is directly below the location of the first die 12.

By virtue of the circuit substrate being prearranged for warping being bent or bowed by the spacer 85 placed thereunder, the electrical connectors 350 of the package 70 fully contact the mounting portions 802 of the circuit substrate 80 during reflow, and the problem of cold junction or bump bridging can be significantly solved. Therefore, the connection reliability of the contact is greatly improved, and the production yield is greatly improved.

The yield of package assemblies produced using the substrate shimming process is greatly improved compared to the yield of package assemblies produced without performing the substrate shimming process (without using spacers during reflow), with a pass rate of 90% or even 99% for reliability qualification.

In fig. 10, after the reflow process, contacts 380 are formed between the package 70 and the circuit substrate 80. The electrical connectors 350 and corresponding mounting portions 802 are reflowed (fig. 9) and bonded together to form contacts 380. In some embodiments, the contacts 380 physically connect the package 70 and the circuit substrate 80 and electrically connect the package 70 and the circuit substrate 80 together. After the reflow process, the plate jig SF and the spacer 85 placed on the plate jig SF are detached and removed. In some embodiments, the assembled structure 90 is a substantially flat or planar structure that includes the circuit substrate 80, the package 70 connected with the circuit substrate 80, and the contacts 380 between the circuit substrate 80 and the package 70. That is, without thermal stress caused by the reflow process and the absence of the spacers 85, the package 70 and the circuit substrate 80 are not warped, and the stably bonded assembled structure 90 becomes a non-warped or substantially flat structure. An underfill process may be performed to dispense underfill material 390 between the package 70 and the circuit substrate 80 and around the contacts 380. The underfill material may be a polymer, an epoxy material, a molded underfill, or the like.

In various embodiments, by performing a substrate shimming process, the complex problem of thermal stress induced warpage is greatly alleviated, and the connection reliability of the contacts is significantly improved. Therefore, the production yield and the production efficiency are improved. The spacers used in the shimming process are eventually removed and can be reused or recycled. Little or no additional equipment is required because the shimming process is compatible with existing manufacturing processes.

Fig. 11 is a schematic cross-sectional view illustrating a package and a circuit substrate disposed on a platform and reflowed in accordance with an embodiment of the present invention.

In fig. 11, two spacers 85A are arranged on the chuck unit SFU of the substrate chuck SF by the substrate shimming process. After the circuit substrate 80A is placed onto the substrate holder SF, the spacer 85A is located below the circuit substrate 80A and between the circuit substrate 80A and the substrate holder unit SFU, thereby forming a gap G between the circuit substrate 80A and the substrate holder unit SFU. The spacer 85A raises the vertical position of a specific portion of the circuit substrate 80A. In some embodiments, the warped circuit substrate 80A has a deformed surface CV 3. In some embodiments, the warpage of the circuit substrate 80A may be expressed as a deviation distance measured from the deformed surface with respect to a reference plane (the mounting plane of the SFU). In certain embodiments, from the cross-sectional view of fig. 11 (a cross-section taken as a normal plane cut through the deformed surface CV 3), at least two curves C3, C4 (shown as dashed lines) of the deformed surface CV3 are shown, and the curvature of these curves C3, C4 can be expressed as a radius of curvature. In fig. 11, the two spacers 85A are arranged below the main die MD of the package 70A and below both sides of the main die MD, and the circuit substrate 80A is bowed and warped into an M-shape by shimming of the spacers 85A. In some embodiments, along the vertical direction (thickness direction) in fig. 11, the positions of the two spacers 85A are located directly below the position of the primary die MD, and the outer sides of the two spacers 85A are substantially aligned with the opposite sides of the primary die MD. That is, the underlying spacers 85A are located within the span of the primary die MD of the package 70A.

In some embodiments, the spacer may be disposed below the location or span of the primary die of the package. In alternative embodiments, the spacer may be disposed below the location or span of the secondary die of the package. Depending on the warpage behavior of the package above during the bonding process of the contacts, the spacers disposed below the circuit substrate may be adjusted accordingly to ensure that the warpage level of the circuit substrate corresponds to the warpage level of the package.

In fig. 11, a package 70A is placed on a circuit substrate 80A and a reflow process RFL is performed. In some embodiments, package 70A is a CoWoS package having a larger sized primary die MD and several small secondary dies TD arranged around the primary die MD. During the reflow process, under thermal shock, package 70A becomes warped due to CTE mismatch, and the warpage of package 70A matches and conforms to the warpage prearranged for circuit substrate 80A. In one embodiment, package 70A is a warped structure having an M-shaped cross-section (M-shaped structure) with a deformed surface CV 4. In some embodiments, the geometry of warped package 70A corresponds and conforms to the geometry of warped circuit substrate 80A. From the cross-sectional view of fig. 11 (a cross-section taken as a normal plane cut through the deformed surface CV 4), at least two curves C5, C6 (shown as dashed lines) of the deformed surface CV4 are shown, and the curvature of these curves of the deformed surface CV4 can be expressed as a radius of curvature. In some embodiments, the curvature of curve C3 is substantially the same as the curvature of curve C5, and curve C3 is the same type of parallel curve as curve C5. In some embodiments, the curvature of curve C4 is substantially the same as the curvature of curve C6, and curve C4 is the same type of parallel curve as curve C6. In some embodiments, the deformed surface CV3 of circuit substrate 80A and the deformed surface CV4 of package 70A are conformal to each other, substantially parallel, and spaced apart with a constant spacing therebetween. Thus, the electrical connectors 350A may be precisely aligned and bonded together with the corresponding mounting portions 802A.

In various embodiments, the deforming surface may comprise one or more curved surfaces, flat surfaces, and/or combinations thereof. In certain embodiments, the curved surface may comprise an elliptic paraboloid, a parabolic cylinder, a hyperbolic paraboloid, or a combination thereof.

Fig. 17 is a schematic cross-sectional view illustrating a package and a circuit substrate disposed on a platform and reflowed in accordance with an embodiment of the present invention.

In fig. 17, a package 170 is placed on a circuit substrate 180 arranged in advance to warp, and a reflow process RFL is performed. In some embodiments, the package 170 is an integrated fan out (InFO) package with one or more dies DD. In some embodiments, the circuit substrate 180 prearranged for warpage is provided by the placement of the spacers 185 and the substrate shimming process. During the reflow process, under thermal shock, the package 170 becomes warped due to CTE mismatch, and the warpage of the package 170 matches and conforms to the warpage prearranged for the circuit substrate 180. In some embodiments, the geometry of warped package 170 corresponds and conforms to the geometry of warped circuit substrate 180. In some embodiments, the package 170 bows and becomes concave (smile-shaped or U-shaped). In some embodiments, as package 170 becomes warped, bottom surface 170BS of package 170 with electrical connections 750 thereon becomes curved surface CV7, and electrical connections 750 are arranged along curved surface CV 7. From the cross-sectional view of FIG. 17 (a cross-section taken as a normal plane cut through the curved surface), a curve C7 (shown as a dashed line) of curved surface CV7 is seen. In fig. 17, the curved surface CV8 of the warped circuit substrate 180 has a curve C8. In some embodiments, the curvature of the curve may be expressed as a radius of curvature. In some embodiments, the curvature of curve C7 is substantially the same as the curvature of curve C8, and curve C7 is the same type of parallel curve as curve C8. In some embodiments, curved surface CV7 is parallel to curved surface CV 8. That is, the curved surface CV8 of the circuit substrate 180 and the curved surface CV7 of the package 170 are parallel to each other and spaced apart with a constant interval (distance) therebetween. Thus, the electrical connectors 750 may be precisely aligned and bonded together with the corresponding mounting portions 802 of the warped circuit substrate 180.

For the substrate shimming process, the spacers arranged below the circuit substrate should be arranged in such a way that the warpage level of the circuit substrate corresponds to the warpage level of the package during the reflow process. A warpage evaluation process is used to identify a warpage level of a package structure that is subjected to a thermal treatment (e.g., reflow process) at a high temperature. The warp evaluation process includes, for example, several steps as follows. Information of the surface condition of the warped surface of the package at high temperature (e.g., reflow temperature) is measured and calculated from the simulation to determine the level of warpage of the package under thermal stress during reflow. In some embodiments, the topography includes a topography or surface profile of the warped surface of the package. Experimental methods may be performed instead of using simulation methods. Based on the determined warpage level for the package, a shape fitting step is performed to determine a suitable matching warpage level for the corresponding substrate. The shape fitting (or curve fitting) step may include numerical calculations and correlation of the digital images. The matched warp level determined for the circuit substrate may be used as the prearranged warp (level) of the circuit substrate. Ideally, the prearranged warpage level coincides with the actual warpage level of the package at elevated temperatures. That is, the surface profile or geometry of the warped surface of the substrate matches the surface profile or geometry of the warped surface of the package at high temperature. Subsequently, the arrangement of the spacers (including the layout, number, and size of the spacers used in the shimming process) is carefully designed to achieve the warpage prearranged for the circuit substrate based on the warpage determined for the package.

In some embodiments, the package is a cogos package. Under thermal processes, the warpage of the CoWoS package may include convex warpage (a warped portion with a crying shape cross section). In other embodiments, the packages are InFO packages. Under the thermal process, the warpage of the InFO package may include concave warpage (warpage portion with smile-shaped cross section). Depending on the type and design of the package mounted on the circuit substrate, the level of warpage or warpage of the circuit substrate may become to include convex warpage, concave warpage, or even a combination thereof.

Fig. 12 to 15 are schematic views illustrating positions and sizes of spacers according to an embodiment of the present invention.

In fig. 12 and 13, the middle portion is a schematic top view of the spacer SP on the substrate holder SF, and the lower portion is a schematic cross-sectional view of the spacer SP on the substrate holder SF. The arrangement of the primary die MD and the secondary die TD within the package PG is schematically illustrated in the upper part of fig. 12 and 13.

From the middle and lower portions of fig. 12, one spacer SP is disposed within one chuck unit SFU on the substrate chuck SF, and the spacer SP is a bar-shaped block having a length L1, a width W1, and a constant thickness T3. From the middle and lower portions of fig. 13, two spacers SP are arranged within one chuck unit SFU on the substrate chuck SF, and each spacer SP is a strip-shaped block having a length L2, a width W2, and a constant thickness T4. In some embodiments, the spacers SP are located below the primary die MD, and the location of the spacers SP corresponds to the location of the primary die MD. In some embodiments, the perpendicular projection of the spacer SP (onto the reference plane of the SFU) partially overlaps the perpendicular projection of the primary die MD (onto the reference plane of the SFU) of the overlying package PG. In some embodiments, in fig. 12, the perpendicular projection of the spacer SP (onto the reference plane of the SFU) completely overlaps the perpendicular projection (shown as a dashed rectangle) of the primary die MD (onto the reference plane of the SFU) of the upper package PG. In some embodiments, in fig. 13, the perpendicular projection of the spacer SP (onto the reference plane of the SFU) partially overlaps the perpendicular projection (shown as a dashed rectangle) of the primary die MD (onto the reference plane of the SFU) of the upper package PG. In some embodiments, the material of the spacer includes a metallic material (e.g., iron, steel, or aluminum) or a metallic material (e.g., tungsten carbide). In some embodiments, the material of the spacer includes a polymeric material, such as polyimide, polytetrafluoroethylene, epoxy, and the like.

In fig. 14 and 15, the upper part is a schematic top view of the spacer SP on the substrate holder SF, and the lower part is a schematic top view of the spacer SP on the substrate holder SF. The spacer shown in fig. 14 or 15 has a thickness that varies along different directions. In fig. 14, one spacer SP is disposed within one chuck unit SFU on the substrate chuck SF, and the spacer SP is a rectangular block having a length L3, a width W3, and a thickness of the spacer SP varies along the width direction, wherein a minimum thickness T6 is at a central portion or inner portion and a maximum thickness T5 is at an outer edge portion. In fig. 15, the spacer SP is a rectangular block having a length L4, a width W4, and the thickness of the spacer SP varies along the width direction with a maximum thickness T7 decreasing to a minimum at a central or inner portion and at an outer edge portion. In some embodiments, the thickness of the spacer varies continuously along the direction of stretch. In other embodiments, the thickness of the spacer varies stepwise along the direction of stretch. It is understood that the thickness of the spacer may vary along the length direction or the width direction, or both. It should also be understood that the size, location, and layout of the spacers may be varied to achieve a desired surface profile of the circuit substrate.

Fig. 16 is a schematic top view illustrating a substrate holder according to an embodiment of the present invention. Referring to fig. 16, in some embodiments, the substrate holder SF is a plate-type holder having several holder units SFU arranged in an array form. In some embodiments, to perform the substrate shimming process, the circuit substrate 80 will be assembled to a fixture unit. The size (surface area) of the holder unit SFU is substantially equal to (or slightly larger than) the size (surface area) of the circuit substrate to fit the circuit substrate tightly into the holder unit SFU. In the lower left gripper unit, a spacer SP is placed to show an exemplary position of the spacer within the gripper unit and relative to a circuit substrate subsequently placed on said spacer. In fig. 16, the size and position of the subsequently placed packages are shown in dashed lines.

According to various embodiments, the packaging process of the present application is highly compatible with current manufacturing processes. In addition, by simply performing the substrate pad-up process, a larger process window is realized for the bonding process, and the connection reliability of the package is greatly improved, thereby solving the problems of poor reliability qualification pass rate and low production yield. In addition, the packaging structure has reliable contact connection and higher production yield.

According to some embodiments of the invention, a bonding process is provided. A circuit substrate is disposed on a jig, and the circuit substrate has a mounting surface and a mounting portion formed on the mounting surface. And executing a substrate padding process. Mounting a package onto the mounting surface of the circuit substrate. The package has a bottom surface and a connector formed on the bottom surface of the package. Performing a reflow process and bonding the connector of the package to the mounting part of the circuit substrate.

According to some embodiments of the present invention, performing a substrate shimming process includes placing a spacer under the circuit substrate and between the circuit substrate and the clamp to bend the circuit substrate and make the mounting surface a first warped surface.

According to some embodiments of the invention, the package comprises at least one first die and a plurality of second dies, and placing spacers comprises placing at least one spacer under the circuit substrate at a location corresponding to a location of the at least one first die of the package.

According to some embodiments of the invention, a vertical projection of the at least one spacer partially overlaps a vertical projection of the at least one first die. According to some embodiments of the invention, a vertical projection of the at least one spacer completely overlaps a vertical projection of the at least one first die. According to some embodiments of the invention, the at least one first die comprises at least one logic die and the plurality of second dies comprises memory dies.

According to some embodiments of the invention, placing a spacer comprises inserting one spacer of varying thickness under the circuit substrate and at a central location of the clamp to lift a portion of the circuit substrate.

According to some embodiments of the present invention, performing the reflow process changes the bottom surface of the package into a second warpage surface, and the first and second warpage surfaces are substantially parallel to each other and spaced apart by a constant distance, the connector and the mounting portion being located between the first and second warpage surfaces. According to some embodiments of the invention, the bonding process further comprises removing the jig and the spacer after bonding the connector of the package to the mounting portion of the circuit substrate.

According to some alternative embodiments of the present invention, a packaging process includes the following steps. A package having a first die and a second die is provided. A circuit substrate having a first warpage level is provided. The package is mounted to the circuit substrate and then heated at an elevated temperature to bond the package to the circuit substrate. The package heated at the elevated temperature is warped at a second warpage level, and the first warpage level substantially coincides with the second warpage level.

According to some embodiments of the invention, a packaging process includes the following steps. Providing a package having a first die and a second die, wherein the first die and the second die are different types of die. A warp evaluation process is performed. A circuit substrate having a first warpage level is provided. Mounting the package to the circuit substrate. Heating the package at an elevated temperature and bonding the package to the circuit substrate at the elevated temperature, wherein the package heated at the elevated temperature is warped at a second warpage level, and the first warpage level substantially conforms to the second warpage level.

According to some embodiments of the invention, performing a warpage evaluation process includes performing a simulation on the package at an elevated temperature to measure and calculate a surface condition of a warpage surface of the package facing the circuit substrate to determine a third warpage level of the package at the elevated temperature, the third warpage level substantially coinciding with the first warpage level or the second warpage level.

According to some embodiments of the invention, the surface condition comprises a topography of the warped surface of the package.

According to some embodiments of the present invention, providing a circuit substrate having a first warpage level includes disposing the circuit substrate to a fixture and inserting a spacer between the circuit substrate and the fixture and beneath the circuit substrate to form a first warpage surface of the circuit substrate for mounting the package.

According to some embodiments of the invention, the package heated at the high temperature is warped to form a second warped surface facing the circuit substrate, a geometry of the second warped surface of the package being substantially the same as a geometry of the first warped surface of the circuit substrate.

According to some embodiments of the invention, a method of manufacturing includes the following steps. A jig is provided and at least one spacer is disposed on the jig. A circuit substrate is disposed on the at least one spacer, the circuit substrate being positioned over the fixture and covering the at least one spacer. The circuit substrate has a mounting surface and a mounting portion formed on the mounting surface, and the mounting surface includes a curved surface. Mounting a package onto the mounting surface of the circuit substrate. The package has a lower surface and a connector formed on the lower surface of the package. Performing a reflow process and bonding the connector of the package to the mounting part of the circuit substrate.

According to some embodiments of the invention, the package comprises at least one first die and a plurality of second dies, and the disposing the at least one spacer comprises placing the at least one spacer on the jig at a location corresponding to a location of the at least one first die of the package after mounting the package.

According to some embodiments of the invention, a vertical projection of the at least one spacer partially overlaps a vertical projection of the at least one first die. According to some embodiments of the invention, a vertical projection of the at least one spacer completely overlaps a vertical projection of the at least one first die.

According to some embodiments of the invention, providing the at least one spacer comprises inserting at least one spacer of varying thickness beneath the circuit substrate and at a central location of the clamp to lift a portion of the circuit substrate.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.