阅读说明：本技术 半导体装置的制造方法 (Method for manufacturing semiconductor device ) 是由 林志昌 吴伟豪 余佳霓 苏焕杰 徐廷鋐 王志豪 于 2019-02-20 设计创作，主要内容包括：一种半导体装置的制造方法,包括在半导体元件上方形成遮罩层,其中半导体元件包含：栅极结构；第一层,设置于栅极结构上方；以及层间介电质,设置于第一层的侧壁上,且其中遮罩层定义开口暴露出第一层的一部分和层间介电质的一部分；进行第一蚀刻工艺,以通过开口蚀刻第一层的一部分和层间介电质的一部分；在进行第一蚀刻工艺之后,在开口中形成一衬垫层；在形成衬垫层之后,进行第二蚀刻工艺,其中第二蚀刻工艺使开口向下延伸而穿过第一层和穿过栅极结构；以及在进行第二蚀刻工艺之后,以第二层填充开口。(A method of fabricating a semiconductor device comprising forming a mask layer over a semiconductor device, wherein the semiconductor device comprises: a gate structure; a first layer disposed over the gate structure; and an interlayer dielectric disposed on the sidewall of the first layer, wherein the mask layer defines an opening exposing a portion of the first layer and a portion of the interlayer dielectric; performing a first etching process to etch a portion of the first layer and a portion of the interlayer dielectric through the opening; forming a liner layer in the opening after the first etching process; after forming the liner layer, performing a second etch process, wherein the second etch process extends the opening down through the first layer and through the gate structure; and filling the opening with a second layer after performing the second etching process.)

1. A method of manufacturing a semiconductor device, comprising:

forming a mask layer over a semiconductor device, wherein the semiconductor device comprises:

a gate structure;

a first layer disposed over the gate structure; and

an interlayer dielectric disposed on the sidewalls of the first layer, wherein the mask layer defines an opening exposing a portion of the first layer and a portion of the interlayer dielectric;

performing a first etching process to etch a portion of the first layer and a portion of the interlayer dielectric through the opening;

forming a liner layer in the opening after the first etching process;

after forming the liner layer, performing a second etching process, wherein the second etching process extends the opening down through the first layer and through the gate structure; and

after the second etching process is performed, the opening is filled with a second layer.

Technical Field

Embodiments of the present disclosure relate to semiconductor technology, and more particularly, to methods of manufacturing semiconductor devices.

Background

The semiconductor Integrated Circuit (IC) industry has experienced rapid growth. Technological advances in integrated circuit materials and design have resulted in generations of integrated circuits, each with smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing integrated circuits, and to achieve these advances, similar developments in the processing and manufacturing of integrated circuits are needed. In the history of integrated circuits, the functional density (i.e., the number of devices interconnected per chip area) has increased while the geometry size (i.e., the smallest component created during the fabrication process) has decreased.

The shrinking geometries lead to semiconductor manufacturing challenges. For example, as geometries continue to shrink, smaller Critical Dimensions (CDs) and higher aspect ratios may cause difficulties in performing the etching process. In some cases, the etching process may inadvertently or unintentionally etch excess layers that should not be etched. When this occurs, the result is reduced device performance or even device failure.

Thus, while existing semiconductor devices and methods of making the same have generally been adequate for their intended purposes, they have not been entirely satisfactory in every aspect.

Disclosure of Invention

In some embodiments, a method of fabricating a semiconductor device is provided, the method comprising forming a mask layer over a semiconductor device, wherein the semiconductor device comprises: a gate structure; a first layer disposed over the gate structure; and an interlayer dielectric disposed on the sidewall of the first layer, wherein the mask layer defines an opening exposing a portion of the first layer and a portion of the interlayer dielectric; performing a first etching process to etch a portion of the first layer and a portion of the interlayer dielectric through the opening; forming a liner layer in the opening after the first etching process; after forming the liner layer, performing a second etch process, wherein the second etch process extends the opening down through the first layer and through the gate structure; and filling the opening with a second layer after performing the second etching process.

In some other embodiments, a method of manufacturing a semiconductor device is provided, the method comprising forming a semiconductor device, the semiconductor device comprising a gate structure, a spacer on a sidewall of the gate structure, a first layer having a T-shaped profile over the gate structure, and an interlayer dielectric on the sidewall of the first layer and on the sidewall of the spacer, wherein an upper surface of the spacer is over an upper surface of the gate structure; forming a patterned masking layer over the semiconductor device, the patterned masking layer defining an opening exposing a portion of the first layer and a portion of the interlayer dielectric; performing a first etching process on the semiconductor element to make the opening extend downwards, wherein the first etching process removes a part of the first layer above the upper surface of the gap wall; forming a liner layer in the opening after performing the first etching process; after forming the liner layer, performing a second etching process to further extend the opening down through the first layer and through the gate structure, thereby separating the gate structure into two sections; and forming an electrically insulating material in the opening after performing the second etching process.

In other embodiments, a semiconductor device is provided, the semiconductor device comprising a layer comprising a fin structure or a dielectric trench isolation feature; a first gate structure and a second gate structure disposed over the layer; a spacer disposed on a sidewall of the layer, wherein an upper surface of the spacer is above an upper surface of the layer; a spacer disposed above an upper surface of the spacer; and an electrically insulating material disposed over the layer and between the first gate structure and the second gate structure, between the spacers, and between the spacers, wherein the electrically insulating material provides electrical isolation between the first gate structure and the second gate structure.

Drawings

The embodiments of the present disclosure can be understood more readily by reference to the following detailed description and accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components (features) in the drawings are not necessarily drawn to scale. In fact, the dimensions of the various elements may be arbitrarily expanded or reduced for clarity of illustration.

Fig. 1 is a perspective view of an exemplary Fin-Field-Effect Transistors (FinFET) device.

Fig. 2A-6A are top views of various stages in the manufacture of a semiconductor device according to various embodiments of the present disclosure.

Fig. 2B-6B are schematic cross-sectional views of various stages in the manufacture of a semiconductor device according to various embodiments of the present disclosure.

Fig. 2C-6C are schematic cross-sectional views of various stages in the manufacture of a semiconductor device according to various embodiments of the present disclosure.

Fig. 7 is a flow chart of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

Description of reference numerals:

10. 200 finfet device

12 epitaxial growth material

15N-type finfet device structure

25P-type finfet device structure

102 substrate

104 fin structure

105. 230 spacer

108 isolation structure

110 gate electrode

112. 114 hard mask

115 dielectric layer

210. 250 layers of

220 grid structure

225. 240, 620, 625, 627, 628 height

235. 275, 535 thickness

270 interlayer dielectric layer

300. 520 opening

310 patterned hard mask layer

320 patterned photoresist layer

330. 340, 530 size

400. 600 etching process

410. 610 etch depth

500 deposition process

510 liner layer

700 process

710 refill material

900 method

910. 920, 930, 940, 950

Detailed Description

It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements thereof are described below to simplify the description of the disclosure. These are, of course, merely examples and are not intended to limit the disclosure. For example, the following disclosure describes forming a first feature over or on a second feature, including embodiments in which the first feature and the second feature are formed in direct contact, and also including embodiments in which additional features may be formed between the first feature and the second feature, such that the first feature and the second feature may not be in direct contact. Moreover, various examples in the disclosure may use repeated reference characters and/or wording. These repeated symbols or words are used for simplicity and clarity and are not intended to limit the relationship between the various embodiments and/or the appearance structure.

Furthermore, spatially relative terms, such as "under," "below," "lower," "above," "upper," and the like, may be used herein for convenience in describing the relationship of one element or component to another element(s) or component(s) in the figures. Spatially relative terms may also encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Further, when a number or range of numbers is described using "about," "approximately," and similar terms, such terms are intended to encompass numbers within a reasonable range, such as within +/-10% of the number described, or other numerical value as would be understood by one of skill in the art. For example, the term "about 5 nm" encompasses a size range of 4.5nm to 5.5 nm.

Embodiments of the present disclosure relate to a method of performing an etching process in the case of a small critical dimension and/or a high aspect ratio without etching an excessive layer that should not be etched, but are not limited thereto. To illustrate various aspects of embodiments of the present disclosure, the fabrication of finfet transistors is discussed as an example below. In this regard, finfet devices are fin-shaped field effect transistor devices that are becoming increasingly popular in the semiconductor industry. The finfet device may be a complementary metal-oxide-semiconductor (CMOS) device including a P-type metal-oxide-semiconductor (PMOS) finfet device and an N-type metal-oxide-semiconductor (NMOS) finfet device. The following disclosure will continue with one or more finfet transistor examples to illustrate various embodiments of the disclosure, but it will be understood that the disclosed embodiments are not limited to finfet devices, except as specifically claimed.

Referring to fig. 1, a perspective view of an exemplary finfet device 10 is shown. The finfet device 10 includes an N-type finfet device (NMOS) structure 15 and a P-type finfet device (PMOS) structure 25. The finfet device 10 includes a substrate 102, and the substrate 102 may be made of silicon or other semiconductor material. Alternatively or additionally, the substrate 102 may comprise other elemental semiconductor materials, such as germanium. In some embodiments, substrate 12 is made of a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 102 may be made of an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or indium gallium phosphide. In some embodiments, the substrate 102 includes an epitaxial layer. For example, the substrate 102 may include an epitaxial layer overlying a bulk (bulk) semiconductor.

The finfet device 10 also includes one or more fin structures 104 (e.g., Si fins) extending from the substrate 102 in the Z-direction, and spacers 105 surrounding the fin structures 104 in the Y-direction. The fin structure 104 is elongated in the X-direction and may optionally include germanium (Ge). The fin structure 104 may be formed using a suitable process, such as photolithography and etching processes. In some embodiments, the fin structure 104 is etched from the substrate 102 using a dry etch or plasma etch process. In some other embodiments, the fin structure 104 may be formed by a double-patterning lithography (DPL) process. Double patterning lithography is a method of building a pattern on a substrate by dividing the pattern into two interleaved patterns. The fin structure 104 also includes an epitaxially grown material 12, and the epitaxially grown material 12 (and a portion of the fin structure 104) may serve as a source/drain of the finfet device 10.

An isolation structure 108, such as a Shallow Trench Isolation (STI) structure, is formed to surround the fin structure 104. In some embodiments, the isolation structure 108 surrounds a lower portion of the fin structure 104, while an upper portion of the fin structure 104 protrudes from the isolation structure 108, as shown in fig. 1. In other words, a portion of the fin structure 104 is embedded in the isolation structure 108. The isolation structures 108 prevent electrical interference or cross-talk.

Finfet device 10 also includes a gate stack structure including a gate electrode 110 and a gate dielectric layer (not shown) under gate electrode 110. The gate electrode 110 may include polysilicon or metal. The metal includes tantalum nitride (TaN), nickel silicon (NiSi), cobalt silicon (CoSi), molybdenum (Mo), copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), zirconium (Zr), platinum (Pt), or other applicable materials. The gate electrode 110 may be formed in a gate post-process (or gate replacement process). Hard masks 112 and 114 may be used to define gate electrode 110. A dielectric layer 115 may also be formed on the sidewalls of the gate electrode 110 and over the hard masks 112 and 114.

The gate dielectric layer (not shown) may comprise a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a dielectric material having a high dielectric constant (high-k), or a combination thereof. Examples of high-k dielectric materials include hafnium oxide, zirconium oxide, aluminum oxide, hafnium oxide-aluminum oxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, the like, or combinations of the foregoing.

In some embodiments, the gate stack structure includes additional layers, such as interfacial layers, capping layers, diffusion/barrier layers, or other applicable layers. In some embodiments, the gate stack structure is formed over a central portion of the fin structure 104. In some other embodiments, a plurality of gate stack structures are formed over fin structure 104. In some other embodiments, the gate stack structure includes a dummy gate stack, and a Metal Gate (MG) replaces the dummy gate stack after the high thermal budget process.

The gate stack structure is formed through a deposition process, a photolithography process, and an etching process. The etching process includes Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), High Density Plasma Chemical Vapor Deposition (HDPCVD), Metal Organic Chemical Vapor Deposition (MOCVD), Remote Plasma Chemical Vapor Deposition (RPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), electroplating, other suitable methods, and/or combinations thereof. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying (e.g., hard baking). The etching process includes a dry etching process or a wet etching process. Alternatively, the photolithography process may be implemented or replaced by other suitable methods, such as maskless photolithography, electron beam writing, and ion beam writing.

Finfet devices offer many advantages over conventional Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) devices, also known as planar Transistor devices. These advantages may include preferred chip area efficiency, improved carrier mobility, and a fabrication process that is compatible with the fabrication process of the planar device. Accordingly, it may be desirable to design the use of finfet devices for a portion of an integrated circuit chip or for the entire integrated circuit chip.

However, fabricating finfet transistors may still be challenging. For example, to provide electrical isolation between gate structures of adjacent finfet devices, fabricating a finfet also involves forming isolation structures between the gate structures. The fabrication process to form these isolation structures may be referred to as a cut-metal-gate (CMG) process. As part of the process of cutting the metal gate, an etching process is performed to etch trenches between adjacent finfet transistors. As semiconductor feature sizes continue to shrink, resulting in smaller critical dimensions and higher aspect ratios, the cut metal gate etch process may need to have a high etch bias (etching bias), which may result in excessive loss of interlayer dielectric (ILD) in other approaches. Excessive loss of interlayer dielectric can reduce device performance or even lead to device failure.

In order to reduce the excessive loss of the interlayer dielectric, the embodiments of the present disclosure decompose the etching process into a plurality of etching processes and form an additional liner layer between the plurality of etching processes. In at least one embodiment, the plurality of etching processes includes two etching processes. During the first etch process, the critical dimension of the cut metal gate is initially defined as large and the aspect ratio is initially low, meaning that a high etch bias is not required during the first etch process. Therefore, excessive interlayer dielectric loss does not occur during the first etching process. Thereafter, the formation of the liner layer helps to reduce the critical dimension of the cut metal gate to a desired size compared to other methods, and the second etching process may be performed with a smaller critical dimension of the cut metal gate. The second etch process may need to have a high etch bias due to the smaller critical dimension and higher aspect ratio, but any interlayer dielectric loss due to the high etch bias is acceptable since the second etch process only needs to etch a small amount of material. It will be appreciated that the conditions considered to be high etch bias may vary from one condition to another, which may depend on factors such as the composition of the etch gas, the type of etch tool used, the structure or material being etched, the type of ions being introduced, the isotropic or anisotropic profile, etc. In some embodiments, an etch bias greater than about 200V may be considered a high etch bias.

Various aspects of embodiments of the present disclosure will be discussed in more detail below with reference to fig. 2A-6A, 2B-6B, 2C-6C, and 7. In this regard, fig. 2A-6A show partial top views of a portion of the finfet device 200 at various stages of fabrication, fig. 2B-6B show partial cross-sectional side views (in the Y-direction) of a portion of the finfet device 200 at various stages of fabrication, and fig. 2C-6C show partial cross-sectional side views (in the X-direction, perpendicular to the Y-direction) of a portion of the finfet device 200 at various stages of fabrication. In more detail, the cross-sectional side views of fig. 2B-6B are obtained from a cross-section taken along Y-direction tangent line M-M '(shown in fig. 2A-6A) on finfet device 200, while the cross-sectional side views of fig. 2C-6C are obtained from a cross-section taken along X-direction tangent line N-N' (shown in fig. 2A-6A) on finfet device 200.

Referring to fig. 2A, 2B, and 2C, finfet device 200 includes a layer 210. In some embodiments, layer 210 includes a dielectric isolation structure, such as a Shallow Trench Isolation (STI). In some other embodiments, layer 210 includes a fin structure, also referred to as a hybrid fin. In embodiments where layer 210 includes fin structures, it will be appreciated that the fin structures are formed over dielectric isolation structures (e.g., shallow trench isolation).

Finfet device 200 includes a gate structure 220 (sometimes referred to simply as a gate), with gate structure 220 being formed over layer 210. The gate structure 220 measures a height 225 vertically in the Z-direction. In some embodiments, the gate structure 220 includes a high-k metal gate (HKMG). The high-k metal gate may be formed in a gate replacement process in which the high-k gate dielectric and the metal gate electrode replace the dummy gate dielectric and the dummy gate electrode. The high-k dielectric material has a dielectric constant greater than that of SiO₂Dielectric constant of (2), SiO₂Has a dielectric constant of about 4. In one embodiment, the high-k gate dielectric comprises hafnium oxide (HfO)₂) Hafnium oxide has a dielectric constant in the range of about 18 to about 40. In other embodiments, the high-k gate dielectric may comprise ZrO₂、Y₂O₃、La₂O₅、Gd₂O₅、TiO₂、Ta₂O₅HfErO, HfLaO, HfYO, HfGdO, HfAlO, HfZrO, HfTiO, HfTaO or SrTiO.

A metal gate electrode is formed over the high-k dielectric, and the metal gate electrode may include a workfunction metal component and a fill metal component. The work function metal elements are configured to adjust the work function of their corresponding finfet transistors to achieve a desired threshold voltage Vt. In various embodiments, the work function metal component may include: TiAl, TiAlN, TaCN, TiN, WN, or W, or a combination of the foregoing. The fill metal component is configured to act as a primary conductive portion of the workfunction gate structure. In various embodiments, the fill metal component may contain aluminum (Al), tungsten (W), copper (Cu), or combinations of the foregoing.

Finfet device 200 also includes spacers 230. As shown in fig. 2C, some sections of spacers 230 are formed on the sidewalls of gate structure 220, while other sections of spacers 230 are formed over the upper surface of layer 210. The spacers 230 comprise a dielectric material, such as silicon nitride (SiN)_x) Silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or combinations thereof. In thatIn some embodiments, the spacers 230 may be formed by a deposition process followed by one or more etching and grinding processes. Each spacer 230 has a thickness 235. In some embodiments, thickness 235 is in a range between about 3nm and about 15 nm. Each spacer 230 also has a height 240, the height 240 being measured in the Z-direction from the uppermost surface of the spacer 230 to the lowermost surface of the spacer 230. The height 240 is greater than the height 225 of the gate structure 220 such that the upper surface of the spacer 230 is vertically above the upper surface of the gate structure 220. In some embodiments, the height 240 of the spacers 230 is in a range between about 20nm and about 100 nm. As described below, the height 240 of the spacers effectively defines the etch depth of the first etch process, since the first etch process will stop when the upper surface of the spacers 230 is reached.

Finfet device 200 includes a layer 250, layer 250 formed over gate structure 220 and over a portion of spacer 230. Layer 250 may also be referred to as a self-aligned contact (SAC) layer. In some embodiments, the layer 250 comprises SiN, a carbon based (SiC), SiOCN, or a metal oxide material. It can be seen from fig. 2C that layer 250 has a T-shape. In other words, the bottom middle portion of layer 250 extends further downward than the other portions of layer 250. Another way to describe the T-shape of layer 250 is for spacers 230 to have a greater height than gate structure 220 such that the interface between layer 250 and spacers 230 is above the interface between layer 250 and gate structure 220.

In some embodiments, the T-shape of layer 250 is achieved by performing the following process: a dummy gate structure is formed, and gate spacers are formed on sidewalls of the dummy gate structure. Then, a gate replacement process is performed, wherein the dummy gate structure is replaced by the high-k metal gate structure. And carrying out an etch-back process on the high-dielectric-constant metal gate structure and the gate spacer. The etching of the gate spacers is stopped when the gate spacers are lowered to the height 240. Thereafter, the high-k metal gate structure continues to be etched after the gate spacers are no longer etched until the high-k metal gate structure is etched into gate structure 220. Layer 250 is formed to replace the removed high-k metal gate structure and the removed gate spacers. In another embodiment, the gate spacers may be etched prior to etching the high-k metal gate structure. In any case, both embodiments result in the height of the spacers 230 exceeding the height of the gate structure 220. Since the layer 250 is formed on the upper surfaces of the gate structure 220 and the spacers 230, the layer 250 is formed to have a T-shaped profile.

Finfet device 200 includes an interlayer dielectric (ILD) layer 270. Interlayer dielectric 270 is the bottom most interlayer dielectric and may be referred to as an ILD0 layer. An interlevel dielectric layer 270 is located on the sidewalls of layer 250 and on the sidewalls of spacers 230. An interlevel dielectric layer 270 is also located over a portion of the spacers 230. The interlayer dielectric layer 270 comprises a dielectric material, such as a low-k dielectric material in some embodiments, or silicon oxide in some other embodiments. The interlevel dielectric layer 270 has a height or thickness 275. In some embodiments, the thickness 275 is in a range between about 30nm and about 200 nm. Embodiments of the present disclosure help prevent overetching of the ild layer 270 compared to other methods, as discussed in more detail below.

Fig. 2A-2C show stages in the fabrication of defining a cut metal gate. Fig. 2A shows a top view outline or profile of a cut metal gate with an opening 300. The opening 300 is defined by a patterned hard mask layer 310, and the patterned hard mask layer 310 is patterned by a patterned photoresist layer 320. For example, a hardmask material, such as a suitable dielectric material, is deposited over layer 250 and interlayer dielectric layer 270, and a photoresist layer is formed over the hardmask material, such as by spin coating. The photoresist layer is then subjected to a photolithography process, which may include one or more steps, such as exposure, post-exposure baking, developing, cleaning, to form a patterned photoresist layer 320. The patterned photoresist layer 320 defines the top profile of the opening 300 for cutting the metal gate. Next, the hard mask material is patterned by the patterned photoresist layer 320, and thus the openings 300 for cutting the metal gates are transferred to the patterned hard mask layer 310.

The opening 300 through which the metal gate is cut has a dimension 330 measured in the Y direction and a dimension 340 measured in the X direction. Dimension 330 is smaller than dimension 340 and thus the top profile of opening 300 cutting the metal gate can be said to resemble a rectangle elongated in the X-direction. The top profile of the opening 300 to cut the metal gate facilitates "cutting" of the gate structure 220 in subsequent processes (in the top view, the gate structure 220 is elongated in the Y-direction).

The opening 300 for cutting the metal gate may be larger than other methods. The larger size of the opening 300 for cutting the metal gate allows for a more open etch window with a smaller etch bias. In some embodiments, the larger size of the opening 300 to cut the metal gate allows for the thickness of the liner layer to be formed. For example, dimension 330 exceeds the conventional cut metal gate opening by about twice the thickness of the liner layer to be formed, while dimension 340 exceeds the conventional cut metal gate opening by about twice the thickness of the liner layer to be formed. In some embodiments, dimension 330 is in a range between about 21nm and about 31nm, such as about 26 nm. In contrast, in some technology nodes, the corresponding dimensions (measured in the Y-direction) of the openings of conventionally cut metal gates are typically less than about 15nm, although it is understood that this number is not intended to be limiting and may vary among technology nodes. Since the Y-dimension of the opening of a conventional cut metal gate defines the Critical Dimension (CD) of the cut metal gate feature (e.g., the isolation feature provides electrical isolation between adjacent gate structures), dimension 330 can be said to be equal to the sum of the critical dimension of the cut metal gate feature and the doubled liner thickness. As such, the embodiments of the present disclosure effectively expand the critical dimension of the cut metal gate for the initial etch process discussed below, although the final critical dimension of the cut metal gate will be reduced to a more desirable dimension by forming a liner layer, as discussed in more detail below.

Referring to fig. 3A, 3B and 3C, the patterned photoresist layer 320 is removed, for example, by a photoresist ashing or stripping process. Using the patterned hard mask layer 310 as a mask, an etching process 400 is performed to etch the layers under the patterned hard mask layer 310 through the openings 300 for cutting the metal gates until the spacers 230 are exposed. In some embodiments, the etch process 400 uses a chloride/chlorine based etchant with an etch bias between about 50V and about 150V and an etch time/duration between about 100 seconds and about 300 seconds. The etch process 400 has an etch depth 410, the etch depth 410 being the depth to which the layer 250 is etched away. Since the etch process stops when the spacers 230 are reached, the etch depth 410 is smaller compared to a conventional cut metal gate etch process. In some embodiments, the etch depth 410 is in a range between about 100nm and about 180 nm. In some embodiments, the ratio of the etch depth 410 to the thickness 275 of the interlayer dielectric layer 270 is between about 0.5: 1 and about 0.9: 1, in the range between. This ratio has been optimized because if the ratio is outside this range, a large amount of etching may be required to etch a small hole having a high aspect ratio. Therefore, a significant portion of the etch may require a high etch bias to achieve such a small hole, which will cause the interlevel dielectric layer 270 to suffer a large loss at its top after the etch.

The aspect ratio of the etch process 400 is defined as the ratio of the etch depth 410 to the dimension 330 (410: 330), and in some embodiments, the aspect ratio of the etch process 400 is between about 1.2: 1 and about 7: 1, in the range between. Compared to a conventional etching process for cutting a metal gate, the etching process can have an aspect ratio of more than about 20: 1, the aspect ratio here is greatly reduced. One reason for the low aspect ratio is the larger size 330 compared to conventional cut metal gate openings. Another reason for the low aspect ratio is the smaller etch depth 410 compared to conventional openings for cutting metal gates. The low aspect ratio and the larger dimension 330 mitigate the etch bias associated with the etch process 400, which means that the etch process 400 may be performed without causing excessive damage to the interlayer dielectric layer 270. In contrast, conventional cut metal gate etch processes typically result in excessive damage to the interlayer dielectric (e.g., excessive etching of the interlayer dielectric when etching down through the opening of the cut metal gate) because of the high etch bias required to overcome the high aspect ratio and smaller critical dimension of the cut metal gate.

Referring to fig. 4A, 4B and 4C, a liner deposition process 500 is performed to form a liner layer 510 in the cut metal gate opening 300 and over exposed surfaces of the layer 250 and the interlayer dielectric layer 270. Since the liner layer 510 partially fills the opening 300, the opening 300 shrinks into a smaller opening 520, the opening 520 measuring a dimension 530 in the Y-direction. For clarity, the opening 300 previously cut through the metal gate and the now smaller opening 520 are shown in phantom in the top view of fig. 4A.

The liner layer 510 has a thickness 535. In some embodiments, thickness 535 is approximately equal to thickness 235 of spacers 230, and in other embodiments (it may be noted that the drawings herein are not necessarily to scale), thickness 535 is slightly less than thickness 235 (e.g., between about 80% and about 100% of thickness 235). The thickness 535 of the liner layer 510 is specifically configured to reduce the size 330 of the previously cut metal gate opening 300 to approximately the size of the finally formed cut metal gate feature. In other words, the dimension 530 of the now smaller cut metal gate opening 520 is approximately equal to the desired critical dimension of the cut metal gate feature, with the dimension 530 in a range between about 10nm and about 70nm in various embodiments. In some embodiments, the thickness 535 is in a range between about 3nm and about 15 nm. If the thickness 535 of the liner layer 510 is configured to be too thick, this thickness may interfere with performing a subsequent etch process to "cut" the gate structure 220. If the thickness 535 of the liner layer 510 is configured to be too thin, the thickness may not be sufficient for the purpose of reducing the critical dimension of the opening for cutting the metal gate and/or protecting the interlayer dielectric layer 270 from being etched in a subsequent etching process.

In some embodiments, the liner layer 510 and the spacer 230 have different material compositions. In some embodiments, the liner layer 510 and the interlayer dielectric layer 270 have different material compositions. In some embodiments, pad layer 510 and layer 250 have different material compositions. As a non-limiting example, the liner layer 510 may comprise SiO_x、SiN_x、SiCN、SiON、SiOCN、AlO_x、HfO_x、LaO_x、ZrO_xOr a combination of the foregoing.

Referring to fig. 5A, 5B and 5C, another etching process 600 is performed to further extend the openings 520 cutting the metal gates vertically downward, such as through the layer 250 and through the gate structures 220. In some embodiments, the etch process 600 uses a chloride/chlorine based etchant with an etch bias between about 50V and about 150V and an etch time/duration between about 100 seconds and about 300 seconds. In other words, the opening 520 that cuts the metal gate now "cuts" or separates the gate structure 220 into two distinct segments.

The etching process 600 must handle smaller openings 520 for the cut metal gates (i.e., smaller critical dimensions of the cut metal gates) and higher aspect ratios than the etching process 400 due to the presence of the liner layer 510. Accordingly, the etch process 600 may require a high etch bias. In other words, etch process 600 has a greater etch bias than etch process 400 due to the smaller critical dimension and higher aspect ratio. However, the total amount of material that needs to be etched away by the etch process 600 is small because the etch process need only be performed from the bottom section of the liner layer 510 (directly above the spacer 230).

In some embodiments, the etch depth 610 associated with the etch process 600 is in a range between about 20nm and about 100nm, the etch depth 610 being significantly less than the thickness 275 of the interlayer dielectric layer 270. Due to the small etch depth, the high etch bias of the etch process 600 is less likely to cause significant damage to the interlayer dielectric layer 270. In addition, since the liner layer 510 is located on the sidewall of the interlayer dielectric layer 270, the liner layer 510 may also protect the interlayer dielectric layer 270 during the etching process 600. As a result of the etch process, a smaller portion (near the top) of the interlayer dielectric layer 270 may be etched away by the etch process 600, which may be tolerated. The top of the section of the liner layer 510 that is on the sidewalls of the interlayer dielectric layer 270 is also etched away, resulting in a loss height 620 (the loss height of the liner layer 510) shown in fig. 5B and a loss height 625 shown in fig. 5C. In other words, the height of the pad layer 510 is reduced by the vertical height 620 shown in fig. 5B and the vertical height 625 shown in fig. 5C. In some embodiments, loss height 620 is in a range between about 20nm and about 150nm, and loss height 625 is greater than loss height 620. This is because the liner layer 510 is etched down from the patterned hard mask layer 310 in the cross-sectional views shown in fig. 4B-5B, and the liner layer 510 is etched down from the interlayer dielectric layer 270 in the cross-sectional views shown in fig. 4C-5C. Thus, the height of the pad layer 510 in fig. 5B and 5C is not the same, since the pad layer 510 is higher in fig. 5B than in fig. 5C. In some embodiments, the pad layer 510 may be completely consumed in fig. 5C, although the pad layer 510 may still remain in fig. 5B. The remaining portion of the pad layer 510 has a pad height 627 in fig. 5B and a pad height 628 in fig. 5C. In some embodiments, the liner height 627 may be in a range between about 5nm and about 100nm and the liner height 628 may be in a range between about 0nm and about 90 nm. In some embodiments, the pad height 628 may be completely consumed. However, after etching, the liner height 627 is maintained to ensure a small dimension (in the Y direction) for cutting the metal gate. The small size facilitates a small Static Random Access Memory (SRAM) and logic cell footprint.

Referring to fig. 6A, 6B and 6C, one or more processes 700 are performed to form a refill material 710 in the reopening 520. The process 700 may include a deposition step followed by a polishing step. For example, a deposition step deposits refill material 710 in opening 520, while a polishing step, such as Chemical Mechanical Polishing (CMP), planarizes the upper surface of interlevel dielectric layer 270 and refill material 710. In some embodiments, refill material 710 may comprise an electrically insulating material, such as SiO_x、SiN_x、SiCN、SiON、SiOCN、AlO_x、HfO_x、LaO_x、ZrO_xOr a combination of the foregoing. It will be appreciated that refill material 710 and pad layer 510 may not necessarily have the same material composition.

Refill material 710 is formed over the upper surface of layer 210 (which may be a dummy fin), and the sidewalls of refill material 710 physically contact the sidewalls of spacers 230, the sidewalls of liner layer 510, and a portion of the sidewalls of interlayer dielectric layer 270. The gasket layer 510 may also be said to surround a portion of the refill material 710. Note that in the cross-sectional schematic views of fig. 6B and 6C, refill material 710 also has a T-shaped cross-sectional profile. However, the T-shaped cross-sectional profiles in fig. 6B and 6C are different due to the difference in the loss heights 620 and 625 (discussed above with reference to fig. 5B-5C). For example, the top of refill material 710 in fig. 6B (e.g., the portion formed over pad layer 510) is thinner than the top of refill material 710 in fig. 6C. Refill material 710 may also be referred to as a cut metal gate feature, which, as described above, is used to provide electrical isolation between the gate structures of adjacent transistors.

As described above, the conventional cut metal gate etch process needs to have a high etch bias because of the small cut metal gate critical dimension and the high aspect ratio of the cut metal gate. However, since the interlayer dielectric layer is unintentionally etched away during the formation of the cut metal gate, a high etch bias causes excessive loss of the interlayer dielectric layer. Here, the embodiments of the present disclosure define the opening of the cut metal gate with a large size, and etch the opening of the cut metal gate by two etching processes. The first etching process is performed when the critical dimension of the cut metal gate is large (because the opening of the original cut metal gate is defined with a large critical dimension) and the aspect ratio is low (because the first etching process does not need to be etched all the time). Thus, the first etch process does not need to have a high etch bias, which means that the loss of interlayer dielectric is reduced. After the first etching process is performed, a liner layer is formed in the opening of the cut metal gate to reduce the critical dimension of the cut metal gate to a desired small critical dimension of the cut metal gate. Thereafter, a second etching process is performed. The second etch process may have a high etch bias, but since the second etch process only needs to etch a small amount (e.g., a small etch depth), the high etch bias of the second etch process will not cause excessive damage to the interlayer dielectric layer. As such, embodiments of the present disclosure may achieve small critical dimensions of the cut metal gate while ensuring that any (undesired) interlayer dielectric loss is minimized.

Fig. 7 is a flow chart of a method 900 of fabricating a semiconductor device in accordance with various aspects of the present disclosure. The method 900 includes a step 910 in which a mask layer is formed over the semiconductor device, step 910. In some embodiments, the semiconductor device comprises a finfet. The semiconductor device includes: a gate structure, a first layer disposed over the gate structure, and an interlayer dielectric (ILD) disposed on sidewalls of the first layer. The mask layer includes an opening exposing a portion of the first layer and a portion of the interlayer dielectric layer. In some embodiments, the gate structure extends in a first direction in the top view and the opening extends in a second direction in the top view, the second direction being different from the first direction. In some embodiments, the semiconductor device further comprises a spacer disposed on the sidewall of the gate structure, wherein an upper surface of the spacer is above an upper surface of the gate structure. In some embodiments, the first layer has a T-shaped profile in the cross-sectional schematic.

The method 900 includes a step 920, where the step 920 performs a first etch process to etch a portion of the first layer and a portion of the interlayer dielectric through the opening.

The method 900 includes a step 930 where a pad layer is formed in the opening after performing the first etch process at step 930. In some embodiments, the step of forming the spacer layer includes forming the spacer to have a thickness equal to or less than a thickness of each of the spacers. In some embodiments, SiO is formed_x、SiN_x、SiCN、SiON、SiOCN、AlO_x、HfO_x、LaO_x、ZrO_xOr a combination of the foregoing as a cushion layer.

The method 900 includes a step 940. after forming the liner layer, the step 940 performs a second etch process. The second etch process extends the opening down through the first layer and through the gate structure. In some embodiments, the second etch process removes a portion, but not all, of the liner layer. In some embodiments, the second etch process has a greater etch bias than the first etch process.

The method 900 includes a step 950, where the step 950 fills the opening with a second layer after performing the second etch process. In some embodiments, step 950 includes filling the opening with an electrically insulating material as a second layer.

It is understood that additional process steps may be performed before, during, or after the above-described steps 910-950 to complete the fabrication of the semiconductor device. For example, the method 900 may include forming source/drains of the semiconductor device before performing step 910, and forming contacts/vias/metal lines after performing step 950. Other steps may be performed, but for simplicity, are not discussed in detail herein.

Based on the above discussion, it can be seen that the disclosed embodiments provide advantages over conventional finfet devices and methods of fabricating the same. However, it is to be understood that other embodiments may provide additional advantages, not all of which need be disclosed herein, and not all of which require a particular advantage. One of the advantages of the disclosed embodiments is to prevent excessive interlayer dielectric loss. This is because the etching process for cutting the metal gate is performed in two steps: the first etching step is performed with a larger critical dimension and a lower aspect ratio of the cut metal gate, and thus the etching bias of the first etching step can be lower than that of the conventional etching process for cutting the metal gate. Since a high etch bias is the primary reason for excessive interlayer dielectric loss, the lower etch bias of the first etch step here reduces the interlayer dielectric loss during etching. When the second etching step is performed, the critical dimension of the cut metal gate is smaller and the aspect ratio can be larger, and thus the second etching step may require a higher etching bias than the first etching step (but still lower than the etching bias of the conventional etching process for cutting the metal gate). However, the second etching step still does not result in excessive interlayer dielectric loss. This is because the second etching step only needs to etch away a small amount of material (because the first etching step has etched a large portion of the opening that cuts the metal gate). As a result, the interlayer dielectric loss due to the second etching step is generally acceptable. Another advantage of embodiments of the present disclosure is that the critical dimensions of the small cut metal gates required for sophisticated semiconductor technology nodes may be preserved or maintained. For example, although a larger opening for cutting the metal gate is initially defined (for the first etching step), after the first etching step is performed and before the second etching step is performed, the liner layer is formed in the embodiment of the present disclosure to reduce the critical dimension of the cut metal gate to a desired dimension. Therefore, the second etching step can still form the opening of the cut metal gate with a small critical dimension of the cut metal gate. Other advantages include compatibility with existing manufacturing process flows, and the like.

One aspect of the disclosed embodiments relates to a method of fabricating a semiconductor device, the method comprising forming a mask layer over a semiconductor device, wherein the semiconductor device comprises: a gate structure; a first layer disposed over the gate structure; and an interlayer dielectric (ILD) disposed on the sidewalls of the first layer, wherein the mask layer defines an opening exposing a portion of the first layer and a portion of the interlayer dielectric. The method includes performing a first etch process to etch a portion of the first layer and a portion of the interlayer dielectric through the opening. The method includes forming a liner layer in the opening after performing a first etching process. The method includes performing a second etch process after forming the liner layer, wherein the second etch process extends the opening down through the first layer and through the gate structure. The method includes filling the opening with a second layer after performing the second etching process.

In some other embodiments, wherein the gate structure extends in a first direction in the top view; and the opening extends in a second direction in the top view, the second direction being different from the first direction.

In some other embodiments, the second etch process removes a portion, but not all, of the liner layer.

In some other embodiments, wherein the second etch process has a greater etch bias than the first etch process.

In some other embodiments, the filling step comprises filling the opening with an electrically insulating material as the second layer.

In some other embodiments, wherein the first layer has a T-shaped profile in the cross-sectional view before the first etching process is performed.

In some other embodiments, the semiconductor device further comprises spacers disposed on sidewalls of the gate structure prior to forming the mask layer, wherein an upper surface of the spacers is above an upper surface of the gate structure.

In some other embodiments, the step of forming the liner layer includes forming the liner layer to have a thickness equal to or less than a thickness of each of the spacers.

In some other embodiments, the step in which the liner layer is formed comprises forming SiO_x、SiN_x、SiCN、SiON、SiOCN、AlO_x、HfO_x、LaO_x、ZrO_xAs a cushion layer.

In some other embodiments, the semiconductor device comprises a finfet transistor.

An aspect of an embodiment of the present disclosure relates to a method of manufacturing a semiconductor device, the method including the step of forming a semiconductor element, the semiconductor element including: a gate structure, a spacer on a sidewall of the gate structure, a first layer having a T-shaped profile over the gate structure, and an interlayer dielectric (ILD) on the sidewall of the first layer and on the sidewall of the spacer, wherein an upper surface of the spacer is over an upper surface of the gate structure. The method includes forming a patterned masking layer over the semiconductor device, the patterned masking layer defining an opening exposing a portion of the first layer and a portion of the interlayer dielectric. The method includes performing a first etching process on the semiconductor device to extend the opening downward, wherein the first etching process removes a portion of the first layer over the upper surface of the spacer. The method includes forming a liner layer in the opening after performing the first etching process. The method includes, after forming the liner layer, performing a second etch process to further extend the opening down through the first layer and through the gate structure, thereby separating the gate structure into two segments. The method includes forming an electrically insulating material in the opening after performing the second etching process.

In some other embodiments, wherein when the patterned mask layer is formed, the gate structure is elongated in a first direction in a top view; and the opening is elongated in a second direction in the top view, the second direction being different from the first direction.

In some other embodiments, wherein the second etch process has a greater etch bias than the first etch process.

In some other embodiments, wherein the second etch process reduces the height of the liner layer.

In some other embodiments, the liner layer is formed to a thickness equal to or less than a thickness of each of the spacers.

Another aspect of the disclosed embodiments relates to a semiconductor device comprising a layer comprising a fin structure or a dielectric trench isolation feature; a first gate structure and a second gate structure disposed over the layer; a spacer disposed on a sidewall of the layer, wherein an upper surface of the spacer is above an upper surface of the layer; a spacer disposed above an upper surface of the spacer; and an electrically insulating material disposed over the layer and between the first gate structure and the second gate structure, between the spacers, and between the spacers, wherein the electrically insulating material provides electrical isolation between the first gate structure and the second gate structure.

In some other embodiments, the electrically insulating material has different T-shaped profiles in at least two of the cross-sectional views.

In some other embodiments, the semiconductor device further comprises an interlayer dielectric (ILD), wherein the spacers and the spacers are disposed between the ILD and the electrically insulating material.

In some other embodiments, wherein the liner surrounds at least a portion of the electrically insulating material.

In some other embodiments, wherein the thickness of the liner is equal to or less than the thickness of the spacer.

The foregoing outlines features of many embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the disclosed embodiments as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure. Various changes, substitutions, or alterations may be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure.