阅读说明：本技术 薄膜晶体管、显示装置和薄膜晶体管的制造方法 (Thin film transistor, display device, and method for manufacturing thin film transistor ) 是由 菅原祐太 道中悟志 野寺伸武 松本隆夫 于 2019-06-20 设计创作，主要内容包括：本发明的一个实施方式的薄膜晶体管包括：基板；被基板支撑的栅极；覆盖栅极的栅极绝缘层；以及氧化物半导体层,是设置在栅极绝缘层且具有结晶硅区域的氧化物半导体层,结晶硅区域包括第一区域、第二区域和位于第一区域及第二区域之间的沟道区域,沟道区域、第一区域及第二区域经由栅极绝缘层与栅极重叠；保护绝缘层,以覆盖沟道区域,且露出第一区域及第二区域的方式配置在氧化物半导体层上；源极,与第一区域电连接；漏极,与第二区域电连接,沟道区域的结晶性与所述第一区域及所述第二区域的结晶性不同。(A thin film transistor according to an embodiment of the present invention includes: a substrate; a gate electrode supported by the substrate; a gate insulating layer covering the gate electrode; and an oxide semiconductor layer which is provided on the gate insulating layer and has a crystalline silicon region including a first region, a second region, and a channel region located between the first region and the second region, the channel region, the first region, and the second region overlapping the gate electrode via the gate insulating layer; a protective insulating layer which is provided over the oxide semiconductor layer so as to cover the channel region and expose the first region and the second region; a source electrode electrically connected to the first region; and a drain electrically connected to the second region, wherein a crystallinity of the channel region is different from a crystallinity of the first region and a crystallinity of the second region.)

1. A thin film transistor, characterized in that,

the thin film transistor includes:

a substrate;

a gate supported by the substrate;

a gate insulating layer covering the gate electrode; and

an oxide semiconductor layer provided over the gate insulating layer and having a crystalline region including a first region, a second region, and a channel region located between the first region and the second region, the channel region, the first region, and the second region overlapping with the gate electrode via the gate insulating layer;

a protective insulating layer which is provided over the oxide semiconductor layer so as to cover the channel region and expose the first region and the second region;

a source electrode electrically connected to the first region;

a drain electrode electrically connected to the second region,

the channel region has a crystallinity different from the crystallinity of the first region and the second region.

2. The thin film transistor according to claim 1, wherein crystallinity of the channel region is lower than crystallinity of the first region and the second region.

3. The thin film transistor according to claim 1, wherein an average crystal grain size of the channel region is smaller than an average crystal grain size of the first region and the second region.

4. The thin film transistor according to claim 1, wherein the channel region comprises a microcrystalline oxide semiconductor,

the first region and the second region comprise a polycrystalline oxide semiconductor or a polycrystalline oxide conductor.

5. The thin film transistor according to any one of claims 1 to 4, wherein the oxide semiconductor further comprises an amorphous region.

6. A thin film transistor, characterized in that,

the thin film transistor includes:

a substrate;

a gate supported by the substrate;

a gate insulating layer covering the gate electrode; and

an oxide semiconductor layer provided over the gate insulating layer and including a first region, a second region, and a channel region located between the first region and the second region, the channel region, the first region, and the second region overlapping with the gate electrode via the gate insulating layer;

a protective insulating layer which is provided over the oxide semiconductor layer so as to cover the channel region and expose the first region and the second region;

a source electrode electrically connected to the first region;

a drain electrode electrically connected to the second region,

the channel region is amorphous, and the first region and the second region are crystalline.

7. The thin film transistor according to any one of claims 1 to 4 and 6, wherein a part of the protective insulating layer is located between the oxide semiconductor layer and the source electrode, and another part of the protective insulating layer is located between the oxide semiconductor layer and the drain electrode.

8. The thin film transistor according to any one of claims 1 to 4 and 6, wherein the oxide semiconductor layer contains indium, gallium, and zinc.

9. A display device, comprising:

the thin film transistor according to any one of claims 1 to 4 and 6;

and a display area having a plurality of pixels,

the thin film transistor is disposed on each of the plurality of pixels.

10. A method of manufacturing a thin film transistor, comprising:

a step (A) of preparing a substrate on which a gate electrode and a gate insulating layer covering the gate electrode are formed on a surface;

a step (B) of forming a semiconductor film made of an amorphous oxide semiconductor over the gate insulating layer;

a step (C) of forming an insulating film over the semiconductor film, and forming a protective insulating layer covering a portion which becomes a channel region in the semiconductor film by patterning the insulating film;

a step (D) of irradiating the semiconductor film with laser light from above the protective insulating layer to crystallize a portion of the semiconductor film covered with the protective insulating layer and a portion not covered with the protective insulating layer in a region overlapping with the gate electrode when viewed from a normal direction of the substrate, so that crystallinity of the portion covered with the protective insulating layer and crystallinity of the portion not covered with the protective insulating layer are different;

a step (E) of forming a source electrode electrically connected to one of the portions of the semiconductor film not covered with the protective insulating layer and a drain electrode electrically connected to the other of the portions not covered with the protective insulating layer.

11. The manufacturing method according to claim 10, wherein in the step (D), the semiconductor film is irradiated with laser light from above the protective insulating layer, and is crystallized in a region overlapping with the gate electrode when viewed from a normal direction of the substrate, so that crystallinity of a portion of the semiconductor film covered with the protective insulating layer is lower than crystallinity of a portion not covered with the protective insulating layer.

12. The method of manufacturing according to claim 10, wherein the laser has a wavelength of about 248nm, and the protective insulating layer is a silicon oxide layer.

13. The manufacturing method according to any one of claims 10 to 12, wherein in the step (D), the laser light is irradiated only to a part of the semiconductor film, and a part of the semiconductor film which is not irradiated with the laser light is kept in an amorphous state.

Technical Field

The invention relates to a thin film transistor, a display device, and a method for manufacturing the thin film transistor.

Background

Thin Film Transistors (TFTs) are widely used as switching elements for respective pixels in display devices such as liquid crystal displays and organic Electroluminescence (EL) displays.

The thin film transistor includes a structure in which a gate electrode, an insulating film, a semiconductor layer (channel layer), a source electrode, and a drain electrode are formed on a substrate. Among them, the bottom gate type thin film transistor is characterized in that a gate electrode is formed closer to the substrate side than a channel layer.

Recently, a thin film transistor (oxide semiconductor TFT) using an oxide semiconductor instead of a silicon semiconductor (amorphous silicon, polycrystalline silicon, or the like) on an active layer of the thin film transistor has been developed. The oxide semiconductor TFT has advantages of a large electron mobility as compared with an amorphous silicon thin film transistor, and a small off-current as compared with a polycrystalline silicon thin film transistor.

For example, patent document 1 discloses a bottom gate type oxide semiconductor TFT having an active layer made of an amorphous oxide semiconductor. Patent document 1 (japanese unexamined patent application publication No. 2014-225626) discloses a structure in which an etch stopper layer for the purpose of protecting an active layer during etching of a source/drain is provided on a part of the active layer of an oxide semiconductor TFT (referred to as an "etch stopper structure").

Disclosure of Invention

Technical problem to be solved by the invention

With the upsizing and high definition of display devices, it is required to further improve the mobility of thin film transistors to improve the on characteristics. In addition, in this specification, the mobility of a portion to be a channel in an active layer of a thin film transistor is referred to as "mobility of the thin film transistor" or "channel mobility" to distinguish the mobility of the material of the active layer itself. However, the present inventors have examined that it is difficult to improve channel mobility while suppressing a decrease in off-current in an oxide semiconductor TFT. The details will be described later. In view of the above, an embodiment of the present invention provides an oxide semiconductor TFT that can improve on-state characteristics (e.g., channel mobility) while suppressing a decrease in off-current. Technical solution for solving technical problem

A thin film transistor of one embodiment of the present invention includes a substrate; a gate supported by the substrate; a gate insulating layer covering the gate electrode; and an oxide semiconductor layer provided over the gate insulating layer and having a crystalline region including a first region, a second region, and a channel region located between the first region and the second region, the channel region, the first region, and the second region overlapping with the gate electrode via the gate insulating layer; a protective insulating layer which is provided over the oxide semiconductor layer so as to cover the channel region and expose the first region and the second region; a source electrode electrically connected to the first region; and a drain electrically connected to the second region, wherein the channel region has a crystallinity different from the crystallinity of the first region and the second region.

In some embodiments, the channel region has a lower crystallinity than the first and second regions.

In some embodiments, the average grain size of the channel region is smaller than the average grain sizes of the first and second regions.

In some embodiments, the channel region comprises a microcrystalline oxide semiconductor, and the first and second regions comprise a polycrystalline oxide semiconductor or a polycrystalline oxide conductor. In some embodiments, the oxide semiconductor further includes an amorphous region.

A thin film transistor according to another embodiment of the present invention includes: a substrate; a gate supported by the substrate; a gate insulating layer covering the gate electrode; and an oxide semiconductor layer provided over the gate insulating layer and including a first region, a second region, and a channel region located between the first region and the second region, the channel region, the first region, and the second region overlapping with the gate electrode via the gate insulating layer; a protective insulating layer which is provided over the oxide semiconductor layer so as to cover the channel region and expose the first region and the second region; a source electrode electrically connected to the first region; and the drain electrode is electrically connected with the second region, the channel region is in an amorphous state, and the first region and the second region are in a crystalline state.

In some embodiments, a portion of the protective insulating layer is between the oxide semiconductor layer and the source electrode, and another portion of the protective insulating layer is between the oxide semiconductor layer and the drain electrode.

In some embodiments, the oxide semiconductor layer includes indium, gallium, and zinc.

A display device according to an embodiment of the present invention includes: a thin film transistor of any one of the above; and a display region having a plurality of pixels, the thin film transistor being disposed on each of the plurality of pixels.

A method for manufacturing a thin film transistor according to an embodiment of the present invention includes: a step (A) of preparing a substrate on which a gate electrode and a gate insulating layer covering the gate electrode are formed on a surface; a step (B) of forming a semiconductor film made of an amorphous oxide semiconductor over the gate insulating layer; a step (C) of forming an insulating film over the semiconductor film, and forming a protective insulating layer covering a portion which becomes a channel region in the semiconductor film by patterning the insulating film; a step (D) of irradiating the semiconductor film with laser light from above the protective insulating layer to crystallize a portion of the semiconductor film covered with the protective insulating layer and a portion not covered with the protective insulating layer in a region overlapping with the gate electrode when viewed from a normal direction of the substrate, so that crystallinity of the portion covered with the protective insulating layer and crystallinity of the portion not covered with the protective insulating layer are different; a step (E) of forming a source electrode electrically connected to one of the portions of the semiconductor film not covered with the protective insulating layer and a drain electrode electrically connected to the other of the portions not covered with the protective insulating layer.

In some embodiments, in the step (D), the semiconductor film is irradiated with laser light from above the protective insulating layer, and is crystallized in a region overlapping with the gate electrode when viewed from a normal direction of the substrate, so that crystallinity of a portion of the semiconductor film covered with the protective insulating layer is lower than crystallinity of a portion not covered with the protective insulating layer.

A method for manufacturing a thin film transistor according to another embodiment of the present invention includes: a step (A) of preparing a substrate on the surface of which a gate electrode and a gate insulating layer covering the gate electrode are formed; a step (B) of forming a semiconductor film made of an amorphous oxide semiconductor over the gate insulating layer; a step (C) of forming an insulating film over the semiconductor film, and forming a protective insulating layer covering a portion which becomes a channel region in the semiconductor film by patterning the insulating film; a step (D) of irradiating the semiconductor film with laser light from above the protective insulating layer, wherein a portion of the semiconductor film not covered with the protective insulating layer is kept in an amorphous state so as to crystallize a portion of the semiconductor film not covered with the protective insulating layer in a region overlapping with the gate electrode when viewed from a normal direction of the substrate; a step (E) of forming a source electrode electrically connected to one of the portions of the semiconductor film not covered with the protective insulating layer and a drain electrode electrically connected to the other of the portions not covered with the protective insulating layer.

In some embodiments, the laser has a wavelength of about 248nm and the protective insulating layer is a silicon oxide layer.

In some embodiments, in the step (D), the laser light is irradiated only to a part of the semiconductor film, and a part of the semiconductor film which is not irradiated with the laser light is kept in an amorphous state.

Advantageous effects

According to one embodiment of the present invention, an oxide semiconductor TFT in which on-state characteristics can be improved while suppressing a decrease in off-state characteristics is provided.

Drawings

Fig. 1 is a schematic cross-sectional view illustrating a structure of a thin film transistor according to a first embodiment.

Fig. 2 is a schematic plan view illustrating the structure of the thin film transistor according to the first embodiment.

Fig. 3A is a schematic cross-sectional view illustrating a method for manufacturing a thin film transistor according to the first embodiment.

Fig. 3B is a schematic cross-sectional view illustrating the method for manufacturing the thin film transistor according to the first embodiment.

Fig. 3C is a schematic cross-sectional view illustrating the method for manufacturing the thin film transistor according to the first embodiment.

Fig. 3D is a schematic cross-sectional view illustrating the method for manufacturing the thin film transistor according to the first embodiment.

Fig. 4 is a schematic cross-sectional view showing a film structure model used in calculating the laser absorptance.

Fig. 5 is a graph showing the calculation result of the laser absorptance.

Fig. 6 is a graph showing Vg-Id characteristics of the thin film transistor according to the present embodiment.

Fig. 7 is a schematic plan view of a thin film transistor according to modification 1.

Fig. 8 is a schematic plan view of a thin film transistor according to modification 2.

Fig. 9 is a schematic plan view of a thin film transistor according to modification 3.

Fig. 10 is a schematic plan view of a thin film transistor according to modification 4.

Fig. 11 is a schematic plan view of a thin film transistor according to modification 5.

Fig. 12 is a schematic cross-sectional view illustrating the structure of the thin film transistor according to the second embodiment.

Fig. 13 is a block diagram illustrating the configuration of the display device according to the second embodiment.

Fig. 14 is a circuit diagram illustrating an example of the configuration of each pixel.

Fig. 15 is a schematic cross-sectional view illustrating a structure of a thin film transistor according to an embodiment.

Fig. 16A is a plan view showing still another example of the thin film transistor.

Fig. 16B is a plan view showing still another example of the thin film transistor.

Fig. 16C is a plan view showing still another example of the thin film transistor.

Fig. 16D is a plan view showing still another example of the thin film transistor.

Fig. 16E is a plan view showing still another example of the thin film transistor.

Fig. 16F is a plan view showing still another example of the thin film transistor.

Detailed Description

A technique of crystallizing an oxide semiconductor film by heating the oxide semiconductor film at a predetermined temperature is known.

The inventors of the present invention have studied a method of irradiating an amorphous oxide semiconductor film with laser light to crystallize it (laser annealing), with the object of improving the on-characteristics of an oxide semiconductor TFT by improving the light resistance and mobility of the oxide semiconductor film. The following findings found by the present invention through studies are described below.

When the oxide semiconductor film is crystallized by laser annealing, oxygen deficiency in the film may increase to lower the resistance. When a TFT is formed using such an oxide semiconductor film, an off-current may be increased, and switching characteristics as a transistor may not be obtained. Therefore, in a portion of the oxide semiconductor film which becomes a channel region in particular, crystallization is preferably performed under conditions in which reduction in resistance is suppressed and mobility is improved.

On the other hand, it is preferable that a portion which is a contact region electrically connected to the source or the drain in the oxide semiconductor film has reduced resistance by crystallization. Since the on-resistance of the oxide semiconductor TFT can be reduced by reducing the resistance of the contact region, the on-characteristics can be further improved.

Therefore, in an oxide semiconductor TFT having an etching stopper structure, the present inventors have found that crystallinity of a portion which becomes a channel region and a portion which becomes a contact region of an oxide semiconductor film can be made different by performing laser annealing on the oxide semiconductor film using the etching stopper layer, and have conceived of the present invention. According to the embodiments of the present invention, since crystallinity of the channel region and the contact region can be controlled separately, an oxide semiconductor TFT capable of realizing both off-characteristics and on-characteristics can be provided.

Further, for example, japanese patent laid-open publication No. 2012 and 253752 describes a method of crystallizing an oxide semiconductor film by heat treatment. However, in this method, since the entire oxide semiconductor film is crystallized under substantially the same conditions, it is difficult to optimize the crystallinity of the channel region and the crystallinity of the contact region.

Japanese patent application laid-open No. 2014-140005 discloses a method of irradiating an oxide semiconductor film with laser light from the back surface of a substrate using a gate electrode as a mask to crystallize only a portion of the oxide semiconductor film which does not overlap with the gate electrode. The crystalline portion functions as a contact region connected to the source or drain. In this method, since the channel region cannot be crystallized, the channel mobility cannot be improved. Further, since a gate electrode that can function as a light shielding film cannot be disposed on the substrate side of the contact region, there is a possibility that the characteristics may be degraded by light.

The embodiments of the present invention will be specifically described based on the drawings.

(first embodiment)

Fig. 1 is a schematic cross-sectional view illustrating a structure of a thin film transistor according to a first embodiment, and fig. 2 is a schematic plan view of the structure. The thin film transistor according to the first embodiment includes, for example, a gate electrode 2, a gate insulating layer 3, a semiconductor layer 4, an etching stopper film (protective insulating layer) 5, a source electrode 6A, and a drain electrode 6B. Here, the semiconductor layer 4 is an oxide semiconductor layer including, for example, an oxide containing indium, gallium, and zinc (In-Ga-Zn-O-based oxide). In the plan view of fig. 2, for the sake of simplicity, only the positional relationship among the gate electrode 2, the polycrystalline oxide semiconductor regions 42A and 42B and the microcrystalline oxide semiconductor region 43 constituting the semiconductor layer 4, and the etching stopper film 5 is shown, and other configurations of the thin film transistor are not shown.

The gate electrode 2 is an electrode patterned on the surface of the substrate 1, and may be formed using a material such as a metal such as Al, Mg, Mo, Cr, Ta, Cu, Ti, Ni, W, Mn, or an alloy or a metal oxide containing these metals as a main component. Here, as the substrate 1, for example, a substrate having an insulating property such as a glass substrate can be used.

The gate insulating layer 3 is formed on the substrate 1 so as to cover the gate electrode 2. The gate insulating layer 3 may be an insulating film of an organic substance or an insulating film of an inorganic substance. In the insulating film of an organic substance, for example, Tetraethyl orthosilicate (TEOS) can be used. In addition, in the insulating film of an inorganic substance, for example, SiO may be used₂、SiO₂/SiN、SiN、SiON、Al2O₃、HfO₂And the like.

The semiconductor layer 4 includes an amorphous oxide semiconductor region 41, a polycrystalline oxide semiconductor region 42A, a polycrystalline oxide semiconductor region 42B, and a microcrystalline oxide semiconductor region 43. The amorphous oxide semiconductor region 41 is formed on the upper side (the opposite side to the substrate) of the gate insulating layer 3, and has a thickness of, for example, 25nm or more. Further, similarly to the amorphous oxide semiconductor region 41, the polycrystalline oxide semiconductor region 42A, the polycrystalline oxide semiconductor region 42B, and the microcrystalline oxide semiconductor region 43 are formed on the upper side of the gate insulating layer 3 in the same layer as the amorphous oxide semiconductor region 41. In addition, the polycrystalline oxide semiconductor region 42A and the polycrystalline oxide semiconductor region 42B have low-resistance regions with lower resistance than the microcrystalline oxide semiconductor region 43 and the amorphous oxide semiconductor region 41. These regions 42A, 42B may also be polycrystalline oxide conductor regions.

In this embodiment, a polycrystalline oxide semiconductor region 42A, a polycrystalline oxide semiconductor region 42B, and a microcrystalline oxide semiconductor region 43 are formed inside a region defined by the outer edge of the gate 2 in a plan view (in the example shown in fig. 2, a rectangular region, hereinafter referred to as a "gate region"). In this embodiment, a region of the semiconductor layer 4 covered with the etching stopper film 5 is a microcrystalline oxide semiconductor region 43, and regions on both sides of the microcrystalline oxide semiconductor region 43 are distributed as a polycrystalline oxide semiconductor region 42A and a polycrystalline oxide semiconductor region 42B. That is, in this embodiment, the crystallinity of the region of the semiconductor layer 4 covered with the etching stopper film 5 is lower than the crystallinity of the other two regions outside. Here, the widths D1 and D2 of the polycrystalline oxide semiconductor region 42A and the polycrystalline oxide semiconductor region 42B in the regions that are located on both sides of the microcrystalline oxide semiconductor region 43 and are not covered with the etching stopper film 5 are preferably 3um or more, respectively.

The crystallinity (also referred to as "crystallinity") of the semiconductor layer 4 can be determined by observing the cross-sectional shape using a Transmission Electron Microscope (TEM), for example. For example, in the diffraction pattern of the transmission electron microscope, it is possible to judge that not the annular diffraction pattern, only the clouded halo pattern, or only one annular diffraction pattern among the halo patterns is amorphous (amorphous). In the diffraction pattern of the transmission electron microscope, when two or more annular diffraction patterns (Debye-Schiller rings) are observed, a large number of the observed Debye-Schiller rings can be judged as polycrystals, and a small number of the observed Debye-Schiller rings can be judged as microcrystals. In addition, the crystallinity of the semiconductor layer 4 can also be judged by measuring the shape of crystal grains using an electron micrograph. The size of crystal grains in the crystallites is 1nm or more and 1 μm or less, for example, 1nm or more and 15nm or less. On the other hand, the size of crystal grains in the polycrystal may be 15nm or more and 10 μm or less.

An island-shaped etching stopper film 5 is formed on the upper side of the microcrystalline oxide semiconductor region 43. The etching stopper film 5 may use, for example, SiO₂Etc. are formed. In this embodiment, the gate electrode 2 is located above and covered by a coverAn etching stopper film 5 is formed in a partial region of the semiconductor layer 4 (a region where the microcrystalline oxide semiconductor region 43 is formed) inside the gate region.

On the upper side of the semiconductor layer 4, a source electrode 6A and a drain electrode 6B having a desired pattern are formed to be spaced apart from each other. The source electrode 6A and the drain electrode 6B can be formed using a material such as a metal, e.g., Al, Mg, Mo, Cr, Ta, Cu, Ti, Ni, W, Mn, or an alloy or a metal oxide containing these metals as a main component. In the present embodiment, the source electrode 6A is formed above one polycrystalline oxide semiconductor region 42A not covered with the etching stopper film 5, and the drain electrode 6B is formed above the other polycrystalline oxide semiconductor region 42B not covered with the etching stopper film 5.

Fig. 3A to 3D are schematic cross-sectional views for explaining a method of manufacturing a thin film transistor according to the first embodiment. First, a metal film is formed from a metal such as Al, Mg, Mo, Cr, Ta, Cu, Ti, Ni, W, or Mn, an alloy containing the metal as a main component, or a metal oxide by a sputtering method on the surface of an insulating substrate 1 having a glass substrate or the like, and a gate electrode 2 is patterned by photolithography using a photomask, dry etching of the metal film, stripping of a resist, or cleaning.

Next, for example, SiO is used by the CVD (chemical Vapor deposition) method₂And SiN, and the like, and a gate insulating layer 3 is formed on the substrate 1 so as to cover the gate electrode 2. The gate insulating layer 3 may also be, for example, SiO₂And a laminated film of SiN or the like.

Next, an amorphous oxide semiconductor film (e.g., an amorphous In-Ga-Zn-O-based semiconductor film) (thickness: e.g., 20nm to 200nm)40 is formed over the gate insulating layer 3 by using a sputtering method In an environment where the oxide semiconductor has a low resistance or lower. In addition, the oxide semiconductor film can be formed by another film formation method such as a pulsed laser deposition method, an electron beam evaporation method, or a coating film formation method instead of the sputtering method. Then, SiO having a thickness of about 10 to 200nm is formed by using a CVD method₂An etching stopper film 5 is formed on the amorphous oxide semiconductor film 40. FIG. 3A showsA state where the gate electrode 2, the gate insulating layer 3, the amorphous oxide semiconductor film 40, and the etching stopper film 5 are formed on the surface of the substrate 1.

Next, the etching stopper film 5 is formed in an island shape by performing photolithography using a photomask, dry etching of the etching stopper film 5, peeling of a resist, and cleaning. At this time, the amorphous oxide semiconductor film 40 has a region covered with the etching stopper film 5 and a region not covered with the etching stopper film 5. The thickness of the region covered with the etching stopper film 5 may be larger than the thickness of the region not covered with the etching stopper film 5, and the thickness of the region covered with the etching stopper film 5 may be, for example, 25nm or more. Fig. 3B shows a state where an island-shaped etching stopper film 5 is formed over the amorphous oxide semiconductor film 40.

Next, inside the gate region in plan view, a laser beam (energy beam) is irradiated from above the etching stopper film 5 to a region larger than a region defined by the outer edge of the etching stopper film 5, and the amorphous oxide semiconductor film 40 is annealed. As the laser used for the annealing treatment, an excimer laser of a mixed gas such as XeF, KrF, and XeCl having a wavelength of 200 to 400nm, or a solid laser such as Yttrium Aluminum Garnet (YAG) and triple wave can be used. The laser light absorption rate of the amorphous oxide semiconductor film 40 varies with the thickness of the etching stopper film 5. In the present embodiment, the thickness of the etching stopper film 5 is set from the following point of view.

Fig. 4 is a schematic cross-sectional view showing a film structure model used in calculating the laser absorptance, and fig. 5 is a graph showing the calculation result of the laser absorptance. In this embodiment, the laser light absorptance In the amorphous In-Ga-Zn-O based semiconductor layer is calculated by taking into account the amplitude reflectance and amplitude transmittance at the interface between the respective films using a film structure model of a multilayer film structure including five layers of the gate electrode 301, the gate insulating layer 302, the gate insulating layer 303, the amorphous In-Ga-Zn-O based semiconductor layer 304, and the etching stopper layer 305.

The wavelength of the laser light used for calculation was set to 248 nm. The refractive index of the gate electrode 301 with respect to the laser beam was 1.46, and the extinction coefficient was 3.62 (thickness: not set). Grid electrodeAn SiN film (constant thickness) having a refractive index of the insulating layer 302 with respect to the laser beam of 2.28 and an extinction coefficient of 0, a gate insulating layer 303 having a refractive index of 1.51 and an SiO film having an extinction coefficient of 0₂Film (thickness: fixed). An amorphous oxide semiconductor film (thickness: constant) In which the refractive index of the amorphous In-Ga-Zn-O semiconductor layer 304 is 2.3 and the extinction coefficient is 0.5. Silicon oxide (SiO) having a refractive index of 1.51 and an extinction coefficient of 0 for the etching stopper layer 305₂) The film (thickness: variable).

The absorptance of the laser light In the amorphous In-Ga-Zn-O based semiconductor layer 304 was calculated while changing the thickness of the etching stopper layer 305 In consideration of multiple interference when the laser light having a wavelength of 248nm was incident from the direction perpendicular to the surface of the film structure model.

Fig. 5 is a graph showing the calculation result of the laser light absorptance In the amorphous In-Ga-Zn-O based semiconductor layer 304 when the thickness of the etching stopper layer 305 is changed. The horizontal axis of the graph represents the thickness (nm) of the etching stopper layer 305, and the vertical axis represents the laser absorptance of the amorphous In-Ga-Zn-O based semiconductor layer 304. As can be seen from the calculation results shown In fig. 5, the laser light absorptance In the amorphous In-Ga-Zn-O-based semiconductor layer 304 (corresponding to the amorphous oxide semiconductor film 40) periodically varies In a range from about 0.7 (minimum value) to 0.9 (maximum value) with respect to the thickness of the etching stopper layer 305 (corresponding to the etching stopper film 5).

In the present embodiment, the thickness of the etching stopper film 5 is set with reference to the calculation result of fig. 5. Specifically, the thickness is set so that the laser absorptance in the amorphous oxide semiconductor film 40 is set to a value including or near the minimum value (a value within a predetermined range including the minimum value).

For example, in the present embodiment, the thickness of the etching stopper film 5 is set to be in the range of 50 to 85nm (or 135 to 170nm), and the etching stopper film 5 is formed to be set to be thick so that the laser absorptance of the amorphous oxide semiconductor film 40 becomes a value in a predetermined range including the minimum value. After that, the etching stopper film 5 is formed into an island shape by dry etching, resist stripping, and cleaning, and laser light (excimer laser or solid laser) having the above wavelength is further irradiated thereto to perform annealing treatment on the amorphous oxide semiconductor film 40.

In the range of the thickness of the etching stopper film 5 from 50 to 85nm (or from 135 to 170nm), the laser absorptance of the amorphous oxide semiconductor film 40 is a minimum value or a value in the vicinity of the minimum value, and the laser absorptance is smaller than that in the case where the etching stopper film 5 is not present (the case where the thickness is 0). Therefore, the laser light absorption rate of the region of the amorphous oxide semiconductor film 40 covered with the etching stopper film 5 is lower than that of the region not covered with the etching stopper film 5. As a result, a region of the amorphous oxide semiconductor film 40 covered with the etching stopper film 5 is, for example, a region including a microcrystalline oxide semiconductor, and a region not covered with the etching stopper film 5 is, for example, a region including a polycrystalline oxide semiconductor.

In addition, the laser light absorption rate of the region of the amorphous oxide semiconductor film 40 covered with the etching stopper film 5 may be substantially equal to the laser light absorption rate of the region not covered with the etching stopper film 5. In this case, the thermal energy generated by the laser absorption of both is originally substantially equal. However, in the region covered with the etching stopper film 5, heat is absorbed by the etching stopper film 5, and thermal energy for crystallizing the amorphous oxide semiconductor is reduced, so that the crystallinity of the region covered with the etching stopper film 5 is lower than that of the region not covered with the etching stopper film 5. As a result, for example, a region covered with the etching stopper film 5 in the amorphous oxide semiconductor film 40 becomes a region including a microcrystalline oxide semiconductor, and a region not covered with the etching stopper film 5 becomes a region including a polycrystalline oxide semiconductor.

By performing annealing treatment on the amorphous oxide semiconductor film 40 from above the etching stopper film 5 using the laser light, a microcrystalline oxide semiconductor region 43 is formed in a region of the amorphous oxide semiconductor film 40 covered with the etching stopper film 5, and a polycrystalline oxide semiconductor region 42A and a polycrystalline oxide semiconductor region 42B are formed in regions located on both sides of the microcrystalline oxide semiconductor region 43 and not covered with the etching stopper film 5. The region of the amorphous oxide semiconductor film 40 which is not irradiated with the laser light directly remains in an amorphous state (amorphous oxide semiconductor region 41). Fig. 3C shows a state where the semiconductor layer 4 including the amorphous oxide semiconductor region 41, the polycrystalline oxide semiconductor region 42A, the polycrystalline oxide semiconductor region 42B, and the microcrystalline oxide semiconductor region 43 is formed by annealing treatment with laser light.

Next, a metal film made of a material such as a metal such as Al, Mg, Mo, Cr, Ta, Cu, Ti, Ni, W, or Mn, an alloy containing the metal as a main component, or a metal oxide is formed by a sputtering method, and the source electrode 6A and the drain electrode 6B are patterned on the semiconductor layer 4 by photolithography using a photomask, dry etching of the metal film, removal of a resist, and cleaning. At this time, photolithography using a photomask and dry etching of a metal film are performed in such a manner that the source electrode 6A and the drain electrode 6B are spaced apart from each other, and a part of the source electrode 6A is located above the polycrystalline oxide semiconductor region 42A and a part of the drain electrode 6B is located above the polycrystalline oxide semiconductor region 42B on the etching stopper film 5. Fig. 3D shows a state where the source electrode 6A and the drain electrode 6B are formed.

Next, electrical characteristics of the thin film transistor according to this embodiment will be described. Fig. 6 is a graph showing Vg-Id characteristics of the thin film transistor according to the present embodiment. The horizontal axis of the graph represents the gate voltage vg (v), and the vertical axis represents the drain current id (a). The value of the drain voltage Vd is 10V. In fig. 6, a solid line graph shows the Vg-Id characteristic of the thin film transistor according to the present embodiment, a dashed line graph shows the Vd-Id characteristic of the thin film transistor of the first comparative example In which the channel portion is formed of the amorphous oxide semiconductor region (amorphous In-Ga-Zn-O-based semiconductor region), and a one-dot chain line graph shows the Vg-Id characteristic of the thin film transistor of the second comparative example In which the channel portion is formed of only the polycrystalline oxide semiconductor region (polycrystalline In-Ga-Zn-O-based semiconductor region).

In addition, the method of manufacturing the thin film transistor of the second comparative example is the same as the method described above with reference to fig. 3A to 3D. However, the method is different from the method shown in fig. 3A to 3D in that after an insulating film serving as an etching stopper is formed over an amorphous oxide semiconductor film, laser light is irradiated to the amorphous oxide semiconductor film from above the insulating film before patterning the insulating film. Therefore, the entire region of the amorphous oxide semiconductor film irradiated with laser light is crystallized under substantially the same conditions as a polycrystalline oxide semiconductor region. Thereafter, the insulating film is patterned to form an etching stopper layer covering a part of the polycrystalline oxide semiconductor region. Therefore, in the thin film transistor according to the second comparative example, the crystallinity of the region of the semiconductor layer covered with the etching stopper layer and the region where the source and drain are connected is substantially the same.

The following electrical characteristics were obtained from the graph shown in fig. 6. (1) The mobility in the first comparative example was 8.83cm²In contrast, in the thin film transistor according to this embodiment, the mobility is 18.17cm²Vs. (2) In the thin film transistors according to the first comparative example and the present embodiment, the sub-threshold coefficient is 0.44V/dec. (3) In the first comparative example, the threshold voltage was 3.62V, whereas in the thin film transistor according to the present embodiment, the threshold voltage was 2.61V. (4) When the gate voltage was-15V, the off-current was 4.64X 10 in the first comparative example^-13In contrast, in the thin film transistor according to this embodiment, the off current is 4.90 × 10^-13A. (5) In the second comparative example, even in a region where the gate voltage is negative, a current equal to the on current flows. That is, the switching action is not performed as a TFT.

As is clear from the above results, the thin film transistor of the present embodiment has higher mobility (channel mobility) than the thin film transistor of the first comparative example. It is understood that the off-current of the thin film transistor of the present embodiment is suppressed to be as low as that of the thin film transistor of the first comparative example.

As described above, in this embodiment, the semiconductor layer 4 has the contact regions connected to (in this example, directly contacting) the source electrode 6A and the drain electrode 6B, which are formed of the low-resistance polycrystalline oxide semiconductor regions 42A and 42B, and the channel region is formed of the microcrystalline oxide semiconductor region 43, so that resistance is maintained, and thus mobility and switching operation can be improved while suppressing an increase in off current.

Next, a modification of the arrangement relationship of the gate electrode 2, the crystallization region (i.e., the laser irradiation region) of the semiconductor layer 4, and the etching stopper film 5 will be described.

(modification 1)

Fig. 7 is a schematic plan view of a thin film transistor according to modification 1. In modification 1, the crystal region (i.e., the laser-irradiated region) protrudes from the gate region. This structure is formed by expanding the laser irradiated region to the outside of the gate region in the annealing treatment of the amorphous oxide semiconductor film 40.

(modification 2)

Fig. 8 is a schematic plan view of a thin film transistor according to modification 2. In modification 2, the crystallization region (i.e., the laser irradiation region) is formed to protrude from the gate region, and the etching stopper film 5 has a portion protruding from the gate region. This structure is formed by extending the range of the photomask to the outside of the gate region and leaving the outside portion of the gate region when the etching stopper film 5 is etched. In the annealing treatment of the amorphous oxide semiconductor film 40, the laser-irradiated region is enlarged to the outside of the gate region.

(modification 3)

Fig. 9 is a schematic plan view of a thin film transistor according to modification 3. In modification 3, the etching stopper film 5 has a portion protruding from the gate region, and the crystallization region (i.e., the laser irradiation region) protrudes from the gate region and a region defined by the outer edge of the etching stopper film 5. This structure is formed by extending the range of the photomask to the outside of the gate region and leaving the outside portion of the gate region when etching the etching stopper film 5. In the annealing treatment of the amorphous oxide semiconductor film 40, the laser-irradiated region is formed by being enlarged to the outside of the gate region and the region defined by the outer edge of the etching stopper film 5.

(modification 4)

Fig. 10 is a schematic plan view of a thin film transistor according to modification 4. In modification 4, the crystal region (i.e., the laser-irradiated region) is formed to protrude from the gate region, and the etching stopper film 5 has a portion protruding from the gate region and the crystal region (i.e., the laser-irradiated region). This structure is formed by extending the range of the photomask to the outside of the gate region and the crystalline region (i.e., the laser irradiated region) and leaving the outside portions of the gate region and the crystalline region (i.e., the laser irradiated region) when the etching stopper film 5 is etched. In the annealing treatment of the amorphous oxide semiconductor film 40, the laser-irradiated region is enlarged to the outside of the gate region.

(modification 5)

Fig. 11 is a schematic plan view of a thin film transistor according to modification 5. In modification 5, the amorphous oxide semiconductor film 40 is annealed in a region where a crystalline region (i.e., a laser-irradiated region) protrudes from the gate region and the etching stopper film 5 is formed inside the gate region. This structure is formed by limiting the range of the photomask to the inside of the gate region when the etching stopper film 5 is etched. In the annealing treatment of the amorphous oxide semiconductor film 40, the laser-irradiated region is enlarged to the outside of the gate region.

(second embodiment)

In a second embodiment, a configuration of a display device using a thin film transistor according to the present embodiment will be described.

When the thin film transistor of the second embodiment is used as a switching element in a liquid crystal display device, the passivation film 82, the organic film 83, and the pixel electrode 9 are sequentially formed on the source electrode 6A and the drain electrode 6B (see fig. 12).

Fig. 14 is a schematic cross-sectional view illustrating the structure of the thin film transistor according to the second embodiment. The thin film transistor according to the second embodiment includes, for example, a gate electrode 2, a gate insulating layer 3, a semiconductor layer 4, an etching stopper film contact 5, a source electrode 6A, a drain electrode 6B, a passivation film 82, an organic film 83, and a pixel electrode 9. The gate electrode 2, the gate insulating layer 3, the semiconductor layer 4, the etching stopper film 5, and the source and drain electrodes 6A and 6B have the same configuration as in the first embodiment.

The passivation film 82 is formed on the upper layers of the source electrode 6A and the drain electrode 6B by a CVD method using SiN or the like, for example. An organic film 83 made of an acrylic resin or the like is formed on the passivation film 82. Thereafter, patterning is performed by photolithography, dry etching, resist stripping, and cleaning, and the contact hole 81 is provided so as to face the drain electrode 6B. Further, an Indium Tin Oxide (ITO) film is formed on the organic film 83 by a sputtering method, and the pixel electrode 9 is formed by patterning. In addition, a Spin-on Glass (SOG, Spin-on Glass) film other than an acrylic resin may be used in the portion of the organic film 83.

Fig. 13 is a block diagram illustrating the configuration of the display device according to the second embodiment. The display device shown in fig. 13 represents an example of a liquid crystal display device, and includes, for example, a liquid crystal display panel 100, a gate driver 101, a source driver 102, a power supply circuit 103, an image memory 104, and a control circuit 105.

The control circuit 105 outputs control signals for controlling the gate driver 101, the source driver 102, the power supply circuit 103, and the image memory 104, respectively, in synchronization with a synchronization signal input from the outside.

The image memory 104 temporarily stores video data of a display object, and outputs the video data to the source driver 102 in accordance with a memory control signal input from the control circuit 105. The image memory 104 may be built in the control circuit 105, and the video data may be output to the source driver 102 by internal processing of the control circuit 105.

The power supply circuit 103 generates a drive voltage for the gate driver 101, a drive voltage for the source driver 102, and the like based on a power supply control signal input from the control circuit 105, and supplies the generated drive voltages to the gate driver 101 and the source driver 102, respectively.

The gate driver 101 generates a scanning signal for turning on/off the switching elements 11 (see fig. 14) on the basis of a gate driver control signal input from the control circuit 105, and sequentially applies the generated scanning signal to each gate line connected to the gate driver, the switching elements 11 being switching elements provided in each pixel 10 of the liquid crystal display panel 100 and arranged in a matrix.

The source driver 102 generates a data signal from the video data input from the image memory 104 based on a source driver control signal input from the control circuit 105, and sequentially applies the generated data signal to each source line connected to the source driver 102. When the corresponding switching element 11 is turned on, a data signal supplied from the source driver 102 via the source line is written into each pixel 10.

In the present embodiment, the configuration in which the gate driver 101 and the source driver 102 are provided outside the liquid crystal display panel 100 is described, but the gate driver 101 and the source driver 102 may be mounted on the periphery of the liquid crystal display panel 100.

Fig. 14 is a circuit diagram illustrating an example of the configuration of each pixel 10. Each pixel 10 includes a switching element 11 and a display element 12. The switching element 11 is, for example, a thin film transistor as shown in the first embodiment, and the source electrode 6A is connected to a source line, and the drain electrode 6B is connected to the pixel electrode 9. Further, the gate 2 of the switching element 11 is connected to a gate line. The switching element 11 can switch on/off states in accordance with a scanning signal supplied to the gate line, the pixel electrode 9 is electrically disconnected from the source line, or the pixel electrode 9 is electrically connected to the source line.

The liquid crystal display panel 100 includes an opposite electrode opposite to the pixel electrode 9. A liquid crystal material is sealed between the pixel electrode 9 and the counter electrode, thereby forming a liquid crystal capacitance C1. The counter electrode is connected to a common voltage generation circuit, not shown, and is maintained at, for example, a fixed potential by applying a common voltage Vcom generated by the common voltage generation circuit.

Each pixel 10 includes a storage capacitor C2 connected in parallel to the liquid crystal capacitor C1, and when a voltage is applied to the pixel electrode 9, electric charges are charged in the storage capacitor C2. Therefore, even during the period when no data voltage is applied through the source line, the voltage value of the pixel 10 can be held by the potential held by the holding capacitor C2.

The control circuit 105 of the liquid crystal display device controls the magnitude of a voltage applied between the pixel electrode 9 and the counter electrode by the gate driver 101, the source driver 102, and the like, and controls the transmittance of the liquid crystal material in each pixel 10 to adjust the amount of light transmitted through the liquid crystal material, thereby performing video display.

The thin film transistor described in the first embodiment is used as the switching element 11 included in each pixel 10, whereby low power consumption can be achieved. By using the thin film transistor described in the first embodiment, a characteristic change between the thin film transistors can be suppressed, and thus, the display quality of the liquid crystal display panel 100 can be favorably maintained.

In addition, although the second embodiment shows the liquid crystal display device as an example of the display device, the thin film transistor described in the first embodiment may be used as a switching element for selecting a pixel or a switching element for driving a pixel used in the organic EL display device.

The embodiments disclosed herein are illustrative in all respects and should not be construed as being limiting. The scope of the present invention is defined by the claims rather than the above epipolar lines, and all changes that come within the meaning and range equivalent to the claims are to be considered as included therein.

With regard to the above-described embodiments, the following remarks will be further disclosed.

A thin film transistor according to an embodiment of the present invention includes: the thin film transistor includes a gate electrode formed on a substrate, a gate insulating layer formed so as to cover the gate electrode, a semiconductor layer formed on the gate insulating layer, and an etching stopper film located above the gate electrode and covering a part of a region of the semiconductor layer, wherein the semiconductor layer is an oxide semiconductor layer including an oxide of indium, gallium, and zinc, the crystallinity of the oxide semiconductor layer in the part of the region covered with the etching stopper layer is different from the crystallinity of the oxide semiconductor layer in two regions located on both sides of the part of the region, and the thin film transistor further includes a source electrode which is provided separately from the oxide semiconductor layer and at least a part of which is located above one of the two regions, and a drain electrode which is at least a part of which is located above the other of the two regions.

In the thin film transistor according to one embodiment of the present invention, the oxide semiconductor layer in the part of the region is a microcrystalline oxide semiconductor layer, and the oxide semiconductor layers in the two regions are polycrystalline oxide semiconductor layers.

A thin film transistor according to one embodiment of the present invention includes an amorphous oxide semiconductor layer in the same layer as the microcrystalline oxide semiconductor layer and the polycrystalline oxide semiconductor layer.

A display device according to one embodiment of the present invention includes a plurality of display elements, and the thin film transistor which selects or drives the display element to be displayed.

A method for manufacturing a thin film transistor according to an embodiment of the present invention includes: forming a gate electrode on a substrate; forming a gate insulating layer to cover the gate electrode; forming an oxide semiconductor layer containing a compound of indium, gallium, and zinc oxide over the gate insulating layer; forming an etching stopper layer over the oxide semiconductor layer, the etching stopper layer having a thickness set to a value in a predetermined range in which an absorptance of the oxide semiconductor layer with respect to the irradiated energy beam is a minimum value or a maximum value; removing a portion of the etching stopper film to make the oxide semiconductor layer have two regions not covered by the etching stopper film; irradiating the energy beam from above the etching plate film to make the crystallinity of the oxide semiconductor layer in the region covered by the etching barrier film different from the crystallinity of the oxide semiconductor layer in the two regions not covered by the etching barrier film; and separating and forming at least one part of the source electrode positioned above one of the two regions and at least one part of the drain electrode positioned above the other of the two regions on the semiconductor layer.

With reference to fig. 15, the structure of the thin film transistor according to one embodiment of the present invention is further described. The thin film transistor includes a substrate 1, a gate electrode 2 supported by the substrate 1, a gate insulating layer 3 covering the gate electrode, a semiconductor layer (oxide semiconductor layer) 4 provided on the gate insulating layer 3 and having a crystal region Rc, a protective insulating layer (also referred to as an "etching stopper layer") 5 disposed on a part of the semiconductor layer 4, and a source electrode 6A and a drain electrode 6B.

In addition, in this specification, the "crystalline region Rc" is a region mainly including a crystalline oxide semiconductor (a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, a single crystal oxide semiconductor, or a crystalline oxide semiconductor in which a c-axis is oriented substantially perpendicular to a layer surface).

The crystalline region Rc includes a first region 4s, a second region 4d, and a channel region 4c located between the first region 4s and the second region 4 d. The first region 4s is a region (source contact region) electrically connected to the source electrode 6A. The second region 4d is a region (drain contact region) electrically connected to the drain 6B. In the present embodiment, the channel region 4c, the first region 4s, and the second region 4d overlap with the gate electrode 2 via the gate insulating layer 3. The first region 4s may also be in direct contact with the source 6A. Similarly, the second region 4d may be in direct contact with the drain 6B.

The protective insulating layer 5 is disposed so as to cover the channel region 4c and be exposed to the first region 4s and the second region 4 d. The protective insulating layer 5 may also be in contact with the upper surface of the channel region 4 c. In the illustrated example, the protective insulating layer 5 has an island shape. The protective insulating layer 5 may be formed so as to cover the entire semiconductor layer 4, and may have an opening exposed in the first region 4s and an opening exposed in the second region 4d of the semiconductor layer 4.

In the step of patterning the conductive film to form the source electrode 6A and the drain electrode 6B (source/drain electrode separation step), the protective insulating layer 5 functions as an etching stopper layer which protects the channel region 4 c. That is, the protective insulating layer 5 is formed below the conductive film (i.e., after the semiconductor layer 4 is formed and before the conductive films for the source and drain are formed). Therefore, a part of the protective insulating layer 5 is located between the semiconductor layer 4 and the source electrode 6A, and another part of the protective insulating layer 5 is located between the semiconductor layer 4 and the drain electrode 6B.

In the present embodiment, the channel region 4c of the crystal region Rc has lower crystallinity than the first region 4s and the second region 4 d. As described above, such a crystal structure is manufactured by performing a crystallization step of irradiating laser light from above the protective insulating layer 5 after forming the protective insulating layer 5 on a part of the amorphous oxide semiconductor film, and controlling the laser light absorptance of a portion of the semiconductor film covered with the protective insulating layer 5 (i.e., the reflectance of laser light having a laminated structure of the protective insulating layer 5).

As an example, the average crystal grain diameter of the channel region 4c may also be smaller than the average crystal grain diameters of the first region 4s and the second region 4 d. Alternatively, the crystallization ratio of the channel region 4c measured using raman spectroscopy may be smaller than the crystallization ratios of the first region 4s and the second region 4 d. That is, the volume ratio of the amorphous phase contained in the channel region 4c may also be larger than the volume ratio of the amorphous phase contained in the first region 4s and the second region 4 d.

The channel region 4c, the first region 4s, and the second region 4d may each include a microcrystalline oxide semiconductor. Alternatively, the channel region 4c may include a microcrystalline oxide semiconductor, and the first region 4s and the second region 4d may include a polycrystalline oxide semiconductor or a polycrystalline oxide conductor. Alternatively, the channel region 4c may include a polycrystalline oxide semiconductor, and the first region 4s and the second region 4d may include a polycrystalline oxide semiconductor or a polycrystalline oxide conductor.

The semiconductor layer 4 may include an amorphous region Ra in addition to the crystalline region Rc. For example, when only a part of the amorphous oxide semiconductor film is irradiated with laser light and crystallized, a region irradiated with the laser light becomes a crystallization region Rc, and a region not irradiated with the laser light remains as an amorphous region Ra. As for such a crystallization method, the entire disclosures of, for example, international publication No. WO2011/055618, international publication No. WO2011/132559, international publication No. WO2016/157351, and international publication No. WO2016/170571 are cited in the present specification.

The resistivity of the crystalline region Rc may be lower than that of the amorphous region Ra. Further, the resistivity of the first region 4s and the second region 4d may be lower than the resistivity of the channel region 4 c.

The semiconductor layer 4 may include indium, gallium, and zinc. For example, an In-Ga-Zn-O-based semiconductor may be included. The kind and composition of the oxide semiconductor included in the semiconductor layer 4 are not particularly limited. The oxide semiconductor may contain at least one of indium, gallium, zinc, tin, aluminum, silicon, germanium, titanium, molybdenum, boron, manganese, and the like. For example, known oxide semiconductors such as In-Zn-O based semiconductors and In-Sn-Zn-O based semiconductors can be used. The material, structure, formation method, and the like of an oxide semiconductor are described in japanese patent No. 6275294. For reference, the entire disclosure of the specification of japanese patent No. 6275294 is incorporated in this specification.

The thin film transistor of this embodiment mode can be manufactured, for example, as follows. First, a gate electrode 2 and a gate insulating layer 3 covering the gate electrode 2 are formed on a substrate 1. Next, an amorphous oxide semiconductor film 40 made of an amorphous oxide semiconductor is formed on the gate insulating layer 3. Next, an insulating film to be a protective insulating layer is formed over the amorphous oxide semiconductor film 40, and the insulating film is patterned to obtain a protective insulating layer 5 covering a portion to be a channel region in the amorphous oxide semiconductor film 40 (see fig. 3B).

Then, the amorphous oxide semiconductor film 40 is irradiated with laser light from above the protective insulating layer 5, whereby the amorphous oxide semiconductor film 40 is crystallized so that the crystallinity of the portion covered with the protective insulating layer 5 is lower than that of the portion not covered with the protective insulating layer 5 in the region overlapping with the gate electrode 2 when viewed from the normal direction of the substrate 1. Thereby, the region irradiated with the laser light is crystallized, and the semiconductor layer 4 having the crystal region Rc is obtained.

Next, a source electrode 6A and a drain electrode 6B are formed, the source electrode 6A being electrically connected to a part (here, the first region 4s) of the portion not covered with the protective insulating layer 5 in the crystal region Rc, the drain electrode 6B being electrically connected to another part (here, the second region 4d) of the portion not covered with the protective insulating layer 5 in the crystal region Rc. Thus, a thin film transistor is manufactured.

According to this embodiment, since the portions (the first region 4s, the second region 4d, and the channel region 4c) of the semiconductor layer (the active layer) 4 of the thin film transistor, which are paths of current flowing between the source electrode 6A and the drain electrode 6B, are formed of a crystalline oxide semiconductor, channel mobility can be improved as compared with a TFT using an amorphous oxide semiconductor. Further, since the crystallinity of the channel region 4c is lower than the crystallinity of the first region 4s and the second region 4d, the increase in on-current due to the decrease in resistance of the channel region 4c can be suppressed, and the mobility can be improved. Therefore, it is possible to ensure desired off characteristics while improving on characteristics.

Further, when the thin film transistor is manufactured by the above method, after the protective insulating film is patterned to form the protective insulating layer 5, laser light is irradiated to the amorphous oxide semiconductor film 40 from above the patterned protective insulating layer 5 to perform laser annealing. Therefore, the crystallinity of the portion of the amorphous oxide semiconductor film 40 covered with the protective insulating film 5 can be made different from the crystallinity of the portion not covered. That is, by using the protective insulating layer 5, even when laser annealing is performed a plurality of times under different irradiation conditions, regions having different crystallinity can be formed separately.

In the crystallization step, by irradiating the amorphous oxide semiconductor film 40 with laser light from above the protective insulating layer 5, a portion of the amorphous oxide semiconductor film 40 not covered with the protective insulating layer 5 can be crystallized in a region overlapping with the gate electrode 2 when viewed from the normal direction of the substrate 1, and a portion covered with the protective insulating layer 5 can be kept in an amorphous state. As a result, the channel region 4c becomes an amorphous region, and the first region 4s and the second region 4d become polycrystalline regions or microcrystalline regions. This can reduce the on-resistance without increasing the off-current.

Alternatively, in the crystallization step, the channel region 4c may be crystallized so as to have higher crystallinity than the first region 4s and the second region 4 d. In such a configuration, for example, the thickness of the protective insulating layer 5 is set to a thickness (in the example shown in fig. 5, the thickness: 85 to 135nm) such that the laser absorptance in the amorphous oxide semiconductor film 40 is a maximum value or a value in the vicinity of the maximum value (a value within a predetermined range including the maximum value), and laser annealing is performed from above the protective insulating layer 5. In this case, for example, the channel region 4c is a polycrystalline region, and the first region 4s and the second region 4d are microcrystalline regions. Therefore, in the semiconductor layer (active layer) 4, while the channel mobility is improved by the partial crystallization that becomes a path for the current flowing between the source electrode 6A and the drain electrode 6B, the increase in the off-current can be suppressed by partially decreasing the crystallinity of the portion that becomes the current path (here, decreasing the crystallinity of the first region 4s and the second region 4 d).

The positional relationship of the gate electrode 2, the protective insulating layer 5, and the crystal region Rc (region irradiated with laser light) is not limited to the examples shown in fig. 1, 7 to 11 when viewed from the normal direction of the substrate 1. Fig. 16A to 16F are plan views showing still another example of the thin film transistor. The arrangement may be as illustrated in fig. 16A to 16F. In any configuration example, the protective insulating layer 5 is configured to overlap only a part of the gate electrode 2. The crystal region Rc is arranged to overlap at least a part of the gate 2. The crystalline region Rc includes a portion overlapping both the gate electrode 2 and the protective insulating layer 5 and a portion overlapping the gate electrode 2 and not overlapping the protective insulating layer 5.

For example, the protective insulating layer 5 may extend across the crystal region Rc in the channel width direction of the thin film transistor when viewed from the normal direction of the substrate 1. Alternatively, the protective insulating layer 5 may have an island shape and be located inside the crystal region Rc when viewed from the normal direction of the substrate 1. The crystal region Rc may be located inside the gate electrode 2 when viewed from the normal direction of the substrate 1. Alternatively, a part of the crystal region Rc may not overlap with the gate electrode 2. For example, the entire semiconductor film may be crystallized by a laser annealing method in which the entire surface of the semiconductor film made of an amorphous oxide semiconductor is scanned.

The present application is based on japanese patent application No. 2018-123446, filed on 28.6.2018, the entire disclosure of which is incorporated herein by reference.