阅读说明：本技术 一种控制并联mos管均衡的电路 (Circuit for controlling parallel MOS (metal oxide semiconductor) tubes to be balanced ) 是由 汤平 邓秉杰 涂建添 周平强 于 2019-09-27 设计创作，主要内容包括：本发明提供一种控制并联MOS管均衡的电路,包括MOS管、均流电阻、电流监测电路、误差监测电路、开关电源以及MCU；所述MOS管的源极通过所述均流电阻接电源地PGND,所述MOS管的漏极接母线电压；所述均流电阻的两端分别与所述电流监测电路相连接；所述开关电源与所述电流监测电路相连接；所述MCU与所述误差监测电路相连接；所述电流监测电路的输出端与所述误差监测电路相连接；所述误差监测电路的输出端与所述MOS管的栅极相连接。本发明的优点在于：均流电阻参与到调节中,可很好的实现并联MOS管中的各个MOS管的电流均衡；在均流电阻相同的条件下,同型号的MOS管无需再进行参数配对。(The invention provides a circuit for controlling the balance of parallel MOS (metal oxide semiconductor) tubes, which comprises an MOS tube, a current equalizing resistor, a current monitoring circuit, an error monitoring circuit, a switching power supply and an MCU (microprogrammed control unit); the source electrode of the MOS tube is connected with a power ground PGND through the current equalizing resistor, and the drain electrode of the MOS tube is connected with bus voltage; two ends of the current equalizing resistor are respectively connected with the current monitoring circuit; the switching power supply is connected with the current monitoring circuit; the MCU is connected with the error monitoring circuit; the output end of the current monitoring circuit is connected with the error monitoring circuit; and the output end of the error monitoring circuit is connected with the grid electrode of the MOS tube. The invention has the advantages that: the current equalizing resistor participates in the regulation, so that the current equalization of each MOS tube in the parallel MOS tubes can be well realized; under the condition that the current equalizing resistance is the same, the MOS tubes of the same type do not need to be subjected to parameter pairing.)

1. The utility model provides a control balanced circuit of parallelly connected MOS pipe which characterized in that: the current-sharing circuit comprises an MOS (metal oxide semiconductor) tube, a current-sharing resistor, a current monitoring circuit, an error monitoring circuit, a switching power supply and an MCU (microprogrammed control unit);

the source electrode of the MOS tube is connected with a power ground PGND through the current equalizing resistor, and the drain electrode of the MOS tube is connected with bus voltage; the two ends of the current equalizing resistor are respectively connected with the current monitoring circuit so as to sample and amplify the voltage difference between the two ends of the current equalizing resistor through the current monitoring circuit; the switching power supply is connected with the current monitoring circuit so as to provide power for the current monitoring circuit through the switching power supply; the MCU is connected with the error monitoring circuit to provide a driving signal for the error monitoring circuit through the MCU;

the output end of the current monitoring circuit is connected with the error monitoring circuit so as to compensate the driving signal of the error monitoring circuit through the amplified signal output by the current monitoring circuit; the output end of the error monitoring circuit is connected with the grid electrode of the MOS tube, so that the opening voltage of the grid electrode of the MOS tube is micro-regulated through the error monitoring circuit, and the currents flowing through the MOS tubes are equal.

2. The circuit for controlling the equalization of parallel MOS transistors as claimed in claim 1, wherein: the current equalizing resistor comprises a resistor R6 and a resistor R12, the source of the MOS transistor is connected with the resistor R6, the resistor R6 is connected with the resistor R12, and the resistor R12 is connected with a power ground PGND.

3. The circuit for controlling the equalization of parallel MOS transistors as claimed in claim 1, wherein: the current monitoring circuit comprises a resistor R1, a resistor R3, a resistor R8, a resistor R9, a resistor R7, a capacitor C3 and a first differential amplifier U1A; both power supply ends of the first differential amplifier U1A are powered by the switching power supply;

the resistor R3 is connected with the negative input end of the first differential amplifier U1A, and the resistor R8 is connected with the positive input end of the first differential amplifier U1A; the V + end of the current equalizing resistor is connected with the resistor R8, and the V-end of the current equalizing resistor is connected with the resistor R3; one end of the resistor R1 is connected with the negative input end of the first differential amplifier U1A, and the other end of the resistor R1 is connected with the output end of the first differential amplifier U1A; one end of the resistor R7 is connected with the output end of the first differential amplifier U1A, and the other end of the resistor R7 is connected with a power ground PGND; one end of the resistor R9 and one end of the capacitor C3 are both connected to the positive input end of the first differential amplifier U1A, and the other end of the resistor R9 and the other end of the capacitor C3 are both connected to the power ground PGND.

4. The circuit for controlling the equalization of parallel MOS transistors as claimed in claim 1, wherein: the error monitoring circuit comprises a resistor R2, a resistor R4, a resistor R5, a resistor R10, a resistor R11, a resistor R13, a capacitor C2, a capacitor C5 and a second differential amplifier U1B;

one end of the resistor R4 is connected with the output end of the current monitoring circuit, and the other end of the resistor R4 is connected with the negative input end of the second differential amplifier U1B; one end of the resistor R13 is connected with the MCU, and the other end of the resistor R13 is connected with the positive input end of the second differential amplifier U1B; one end of the capacitor C5 and one end of the resistor R10 are both connected to the positive input end of the second differential amplifier U1B, and the other ends of the capacitor C5 and the resistor R10 are both connected to a power ground PGND; one end of the resistor R2 is connected to the negative input terminal of the second differential amplifier U1B, the other end of the resistor R2 is connected to one end of the capacitor C2, and the other end of the capacitor C2 is connected to the output terminal of the second differential amplifier U1B; one end of the resistor R11 is connected with the output end of the second differential amplifier U1B, and the other end of the resistor R11 is connected with a power ground PGND; one end of the resistor R5 is connected with the output end of the second differential amplifier U1B, and the other end of the resistor R5 is connected with the grid of the MOS tube.

Technical Field

The invention relates to the field of lithium battery production, in particular to a circuit for controlling the balance of parallel MOS (metal oxide semiconductor) tubes.

Background

In the field of high-power linear power supplies, the situation that a plurality of MOS tubes are used in parallel is often met. When a plurality of MOS tubes are used in parallel, even the MOS tubes with the same type have difference in conduction impedance and on-state voltage, and the MOS tubes are difficult to realize balance, so that the MOS tubes with overlarge current are easy to overheat and burn. In order to avoid this situation, it is usually necessary to add a control circuit to make the current flowing through each MOS transistor at the moment when the MOS transistor switch is turned on or off consistent, so as to achieve the purpose of current balancing of each MOS transistor. However, the existing MOS transistor equalization circuit has the following defects:

1. the current equalizing effect achieved by adopting the current equalizing resistor is poor, and meanwhile, under the condition of large current, great power loss is often needed, so that the efficiency and the reliability of equipment are reduced, the volume of the equipment is increased, and the cost of the equipment is increased; 2. for MOS tubes of the same type, parameter matching is needed, and the use is inconvenient; 3. equal proportion current sharing cannot be performed.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a circuit for controlling the balance of parallel MOS tubes, and the circuit can well realize the current balance adjustment of each MOS tube in the parallel MOS tubes.

The circuit for controlling the balance of the parallel MOS tubes comprises the MOS tubes, a current equalizing resistor, a current monitoring circuit, an error monitoring circuit, a switching power supply and an MCU (microprogrammed control unit);

the source electrode of the MOS tube is connected with a power ground PGND through the current equalizing resistor, and the drain electrode of the MOS tube is connected with bus voltage; the two ends of the current equalizing resistor are respectively connected with the current monitoring circuit so as to sample and amplify the voltage difference between the two ends of the current equalizing resistor through the current monitoring circuit; the switching power supply is connected with the current monitoring circuit so as to provide power for the current monitoring circuit through the switching power supply; the MCU is connected with the error monitoring circuit to provide a driving signal for the error monitoring circuit through the MCU;

the output end of the current monitoring circuit is connected with the error monitoring circuit so as to compensate the driving signal of the error monitoring circuit through the amplified signal output by the current monitoring circuit; the output end of the error monitoring circuit is connected with the grid electrode of the MOS tube, so that the opening voltage of the grid electrode of the MOS tube is micro-regulated through the error monitoring circuit, and the currents flowing through the MOS tubes are equal.

Further, the current sharing resistor comprises a resistor R6 and a resistor R12, the source of the MOS transistor is connected with the resistor R6, the resistor R6 is connected with the resistor R12, and the resistor R12 is connected with a power ground PGND.

Further, the current monitoring circuit comprises a resistor R1, a resistor R3, a resistor R8, a resistor R9, a resistor R7, a capacitor C3 and a first differential amplifier U1A; both power supply ends of the first differential amplifier U1A are powered by the switching power supply;

the resistor R3 is connected with the negative input end of the first differential amplifier U1A, and the resistor R8 is connected with the positive input end of the first differential amplifier U1A; the V + end of the current equalizing resistor is connected with the resistor R8, and the V-end of the current equalizing resistor is connected with the resistor R3; one end of the resistor R1 is connected with the negative input end of the first differential amplifier U1A, and the other end of the resistor R1 is connected with the output end of the first differential amplifier U1A; one end of the resistor R7 is connected with the output end of the first differential amplifier U1A, and the other end of the resistor R7 is connected with a power ground PGND; one end of the resistor R9 and one end of the capacitor C3 are both connected to the positive input end of the first differential amplifier U1A, and the other end of the resistor R9 and the other end of the capacitor C3 are both connected to the power ground PGND.

Further, the error monitoring circuit comprises a resistor R2, a resistor R4, a resistor R5, a resistor R10, a resistor R11, a resistor R13, a capacitor C2, a capacitor C5 and a second differential amplifier U1B;

one end of the resistor R4 is connected with the output end of the current monitoring circuit, and the other end of the resistor R4 is connected with the negative input end of the second differential amplifier U1B; one end of the resistor R13 is connected with the MCU, and the other end of the resistor R13 is connected with the positive input end of the second differential amplifier U1B; one end of the capacitor C5 and one end of the resistor R10 are both connected to the positive input end of the second differential amplifier U1B, and the other ends of the capacitor C5 and the resistor R10 are both connected to a power ground PGND; one end of the resistor R2 is connected to the negative input terminal of the second differential amplifier U1B, the other end of the resistor R2 is connected to one end of the capacitor C2, and the other end of the capacitor C2 is connected to the output terminal of the second differential amplifier U1B; one end of the resistor R11 is connected with the output end of the second differential amplifier U1B, and the other end of the resistor R11 is connected with a power ground PGND; one end of the resistor R5 is connected with the output end of the second differential amplifier U1B, and the other end of the resistor R5 is connected with the grid of the MOS tube.

The invention has the advantages that:

1. the current-sharing resistor participates in regulation (namely, current is converted into voltage through the current-sharing resistor), so that the current balance of each MOS tube in the parallel MOS tubes can be well realized; under the condition that the current equalizing resistance is the same, the MOS tubes of the same type do not need to be subjected to parameter pairing;

2. the circuit of the invention has negative feedback regulation (specifically, the negative feedback regulation is carried out through an error monitoring circuit), so that the regulation is carried out without a peripheral MCU control signal;

3. the circuit of the invention can realize equal proportion current sharing under the same bus voltage and MOS tubes of the same type;

4. the circuit of the invention can also artificially and controllably set the current equalizing value of any MOS tube in the parallel MOS tubes (namely the current value of R6+ R12 in the circuit), and can be flexibly and conveniently applied under various conditions.

Drawings

The invention will be further described with reference to the following examples with reference to the accompanying drawings.

Fig. 1 is a schematic block diagram of a circuit for controlling the equalization of parallel MOS transistors according to the present invention.

Fig. 2 is a circuit diagram of a circuit for controlling the equalization of parallel MOS transistors according to the present invention.

Detailed Description

Referring to fig. 1 to 2, a preferred embodiment of a circuit 100 for controlling the equalization of parallel MOS transistors according to the present invention includes a MOS transistor 1, a current equalizing resistor 2, a current monitoring circuit 3, an error monitoring circuit 4, a switching power supply 5, and an MCU 6;

a source electrode (S) of the MOS tube 1 is connected with a power ground PGND through the current equalizing resistor 2, and a drain electrode (D) of the MOS tube 1 is connected with a bus voltage 7; the two ends of the current-sharing resistor 2 are respectively connected with the current monitoring circuit 3, so that the voltage difference between the two ends of the current-sharing resistor 2 is sampled and amplified through the current monitoring circuit 3; the switch power supply 5 is connected with the current monitoring circuit 3 to provide power for the current monitoring circuit 3 through the switch power supply 5, and during specific implementation, the switch power supply 5 can provide VCC + and VCC-power for the current monitoring circuit 3; the MCU6 is connected to the error monitoring circuit 4 to provide a driving signal for the error monitoring circuit 4 via the MCU6, and the MCU6 can AD output a level signal to provide a driving signal for the error monitoring circuit 4;

the output end of the current monitoring circuit 3 is connected with the error monitoring circuit 4, so that the driving signal of the error monitoring circuit 4 is compensated through the amplified signal output by the current monitoring circuit 3; the output end of the error monitoring circuit 4 is connected with the grid electrode of the MOS tube 1, so that the opening voltage of the grid electrode (G) of the MOS tube 1 is micro-regulated through the error monitoring circuit 4, and the currents flowing through the MOS tubes 1 are equal. In the specific implementation of the present invention, for each MOS transistor 1 in the parallel MOS transistors, the circuit 100 of the present invention is required to control, so that the currents flowing through the MOS transistors 1 are controlled to be equal by the circuit 100 of the present invention, thereby achieving the purpose of current balancing of each MOS transistor 1.

In the invention, the current sharing resistor 2 comprises a resistor R6 and a resistor R12, the source of the MOS transistor 1 is connected with the resistor R6, the resistor R6 is connected with the resistor R12, and the resistor R12 is connected with a power ground PGND. By connecting the resistor R6 and the resistor R12 in series between the source (S) of the MOS transistor 1 and the power ground PGND, the current flowing between the source (S) of the MOS transistor 1 and the power ground PGND can be converted into a voltage through the resistor R6 and the resistor R12.

In the present invention, the current monitoring circuit 3 includes a resistor R1, a resistor R3, a resistor R8, a resistor R9, a resistor R7, a capacitor C3, and a first differential amplifier U1A; both power supply ends of the first differential amplifier U1A are powered by the switching power supply 5;

the resistor R3 is connected with the negative input end of the first differential amplifier U1A, and the resistor R8 is connected with the positive input end of the first differential amplifier U1A; the V + end of the current-sharing resistor 2 is connected with the resistor R8, and the V-end of the current-sharing resistor 2 is connected with the resistor R3; one end of the resistor R1 is connected with the negative input end of the first differential amplifier U1A, and the other end of the resistor R1 is connected with the output end of the first differential amplifier U1A; one end of the resistor R7 is connected with the output end of the first differential amplifier U1A, and the other end of the resistor R7 is connected with a power ground PGND; one end of the resistor R9 and one end of the capacitor C3 are both connected to the positive input end of the first differential amplifier U1A, and the other end of the resistor R9 and the other end of the capacitor C3 are both connected to the power ground PGND. The current monitoring circuit 3 connects one end of the resistor R3 with the V + end of the source (S) of the MOS transistor 1, and connects one end of the resistor R8 with the V-end of the power ground PGND, thereby sampling the voltage difference between the two ends of the resistor R6 and the resistor R12 in the current sharing resistor 2; the differential amplification circuit composed of the resistor R1, the resistor R3, the resistor R8, the resistor R9, the resistor R7 and the first differential amplifier U1A can amplify the voltage difference between two ends of the sampled resistor R6 and the sampled resistor R12; the capacitor C3 is mainly used for filtering ripple burrs at a V + end so as to enable the system to work more stably; the resistor R3 and the resistor R8 can increase the input impedance of the first differential amplifier U1A, and thus can improve the accuracy of the differential amplifier circuit.

In the present invention, the error monitoring circuit 4 includes a resistor R2, a resistor R4, a resistor R5, a resistor R10, a resistor R11, a resistor R13, a capacitor C2, a capacitor C5, and a second differential amplifier U1B;

one end of the resistor R4 is connected with the output end of the current monitoring circuit 3, and the other end is connected with the negative input end of the second differential amplifier U1B; one end of the resistor R13 is connected with the MCU6, and the other end of the resistor R13 is connected with the positive input end of the second differential amplifier U1B; one end of the capacitor C5 and one end of the resistor R10 are both connected to the positive input end of the second differential amplifier U1B, and the other ends of the capacitor C5 and the resistor R10 are both connected to a power ground PGND; one end of the resistor R2 is connected to the negative input terminal of the second differential amplifier U1B, the other end of the resistor R2 is connected to one end of the capacitor C2, and the other end of the capacitor C2 is connected to the output terminal of the second differential amplifier U1B; one end of the resistor R11 is connected with the output end of the second differential amplifier U1B, and the other end of the resistor R11 is connected with a power ground PGND; one end of the resistor R5 is connected with the output end of the second differential amplifier U1B, and the other end of the resistor R5 is connected with the grid (G) of the MOS transistor 1. The resistor R2 and the capacitor C2 are used for forming an integral constant of PID; an integral compensation circuit consisting of the resistor R2, the resistor R4, the resistor R5, the resistor R10, the resistor R11, the resistor R13, the capacitor C2 and the capacitor C5 can be used for compensating a driving signal of the MCU 6.

The working principle of the circuit of the invention is as follows:

firstly, for each MOS tube 1 connected in parallel, the drain electrode (D) of the MOS tube 1 is connected with a bus voltage 7, and a current equalizing resistor 2 is connected between the source electrode (S) of the MOS tube 1 and a power ground PGND in series; the V + end and the V-end of the current equalizing resistor 2 are respectively connected with the current monitoring circuit 3; the amplified signal output by the current monitoring circuit 3 is connected to the error monitoring circuit 4;

secondly, the +12V power supply and the-5V power supply are provided for a first differential amplifier U1A in the current monitoring circuit 3 through a switching power supply 5; the MCU sets voltage as a driving signal of the error monitoring circuit 4;

thirdly, the grid (G) of each MOS tube 1 reaches the starting voltage through the voltage set by the MCU, each MOS tube 1 is conducted to enable the current to pass through the current equalizing resistor 2, the current monitoring circuit 3 collects the voltage difference at the two ends of the current equalizing resistor 2 and amplifies the voltage difference, and the amplified signals compensate the driving signals, so that the starting voltage of the grid (G) of each MOS tube 1 is subjected to micro-adjustment, and the current flowing through each MOS tube 1 is equal.

In summary, the invention has the following advantages:

1. the current-sharing resistor participates in regulation (namely, current is converted into voltage through the current-sharing resistor), so that the current balance of each MOS tube in the parallel MOS tubes can be well realized; under the condition that the current equalizing resistance is the same, the MOS tubes of the same type do not need to be subjected to parameter pairing;

2. the circuit of the invention has negative feedback regulation (specifically, the negative feedback regulation is carried out through an error monitoring circuit), so that the regulation is carried out without a peripheral MCU control signal;

3. the circuit of the invention can realize equal proportion current sharing under the same bus voltage and MOS tubes of the same type;

4. the circuit of the invention can also artificially and controllably set the current equalizing value of any MOS tube in the parallel MOS tubes (namely the current value of R6+ R12 in the circuit), and can be flexibly and conveniently applied under various conditions.

Although specific embodiments of the invention have been described above, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the appended claims.