阅读说明：本技术 动态放大器及其增益增强方法 (Dynamic amplifier and gain enhancement method thereof ) 是由 谢正恩 刘深渊 曾子建 林晋毅 黄国声 黄如琳 于 2019-02-26 设计创作，主要内容包括：本发明公开了一种动态放大器及其增益增强方法,所述动态放大器包括一第一输出电容、一第一开关器、一电流源、一第二开关器、一电压侦测单元、一第三开关器及一电平移位器。该第一开关器耦接于该第一输出电容的一第一端与一电压侦测节点之间。该第二开关器耦接于该电流源及该电压侦测节点。该电压侦测单元耦接于该电压侦测节点及该第一开关器。该第三开关器耦接于该电压侦测节点与一电源端之间。该电平移位器耦接于该第一输出电容的一第二端。(The invention discloses a dynamic amplifier and a gain enhancement method thereof, wherein the dynamic amplifier comprises a first output capacitor, a first switch, a current source, a second switch, a voltage detection unit, a third switch and a level shifter. The first switch is coupled between a first end of the first output capacitor and a voltage detection node. The second switch is coupled to the current source and the voltage detection node. The voltage detection unit is coupled to the voltage detection node and the first switch. The third switch is coupled between the voltage detection node and a power supply terminal. The level shifter is coupled to a second end of the first output capacitor.)

1. A dynamic amplifier, comprising:

a first output capacitor;

a first switch coupled between a first end of the first output capacitor and a voltage detection node;

a current source;

a second switch coupled to the current source and the voltage detection node;

a voltage detection unit coupled to the voltage detection node and the first switch;

a third switch coupled between the voltage detection node and a power supply terminal; and

and a level shifter coupled to a second end of the first output capacitor.

2. The dynamic amplifier of claim 1, wherein the voltage detection unit is configured to detect an output voltage of the first end of the first output capacitor via the voltage detection node.

3. The dynamic amplifier of claim 1, further comprising a second output capacitor, the voltage detection unit comprising:

a first detection capacitor coupled to the voltage detection node;

a second detection capacitor coupled to another voltage detection node for detecting the second output capacitor;

and

and the buffer is coupled with the first switch and used for controlling the first switch to be switched on or switched off according to a common-mode voltage of the first output capacitor and the second output capacitor.

4. The dynamic amplifier of claim 1, wherein the level shifter comprises a switch for selectively coupling the second terminal of the first output capacitor to a first reference voltage node or a second reference voltage node.

5. The dynamic amplifier of claim 4, wherein the switch of the level shifter comprises:

a P-type metal oxide semiconductor field effect transistor coupled between the second end of the first output capacitor and the first reference voltage node; and

an N-type metal oxide semiconductor field effect transistor coupled between the second end of the first output capacitor and the second reference voltage node;

the P-type and N-type MOSFETs are controlled by the same control signal to selectively couple the second end of the first output capacitor to the first reference voltage node or the second reference voltage node.

6. The dynamic amplifier of claim 1, wherein the first switch and the third switch are turned on during a precharge phase to reset an output voltage of the first terminal of the first output capacitor to a power supply voltage of the power source terminal.

7. The dynamic amplifier of claim 6, wherein the level shifter controls the second terminal of the first output capacitor to switch from being coupled to a first reference voltage node to being coupled to a second reference voltage node when the precharge phase is over.

8. The dynamic amplifier of claim 7, wherein the first switch and the second switch are turned on during an amplification phase, so that the current source charges or discharges the output capacitor with a charging or discharging current to perform amplification.

9. The dynamic amplifier of claim 8, wherein the voltage detection unit controls the first switch to be turned off when the voltage detection unit detects that a common mode voltage of the output voltages of the first output capacitor and a second output capacitor reaches a threshold value.

10. The dynamic amplifier of claim 8, wherein the level shifter controls the second terminal of the first output capacitor to switch from being coupled to a first reference voltage node to being coupled to a second reference voltage node during the amplification phase.

11. The dynamic amplifier of claim 8, wherein the level shifter controls the coupling of the second terminal of the first output capacitor to switch a plurality of times during the amplification stage.

12. The dynamic amplifier of claim 1, further comprising a second output capacitor, wherein an output terminal of the dynamic amplifier is coupled to the first terminal of the first output capacitor and a first terminal of the second output capacitor, and a second terminal of the second output capacitor is coupled to a ground terminal.

13. The dynamic amplifier of claim 1, wherein the level shifter shifts up an output voltage at the first terminal of the first output capacitor before the current source discharges the first output capacitor to perform amplification.

14. The dynamic amplifier of claim 1, wherein the level shifter shifts down an output voltage of the first terminal of the first output capacitor before the current source charges the first output capacitor to perform amplification.

15. A dynamic amplifier, comprising:

a first output capacitor;

a second output capacitor;

a first circuit breaking switch coupled between the first output capacitor and a first voltage detection node; a second circuit breaking switch coupled between the second output capacitor and a second voltage detection node; a current source;

an amplification control switch coupled to the current source, the first voltage detection node and the second voltage detection node;

a voltage detection unit coupled to the first voltage detection node, the second voltage detection node, the first circuit breaker and the second circuit breaker;

a first reset switch coupled between the first voltage detecting node and a power source terminal;

a second reset switch coupled between the second voltage detecting node and the power supply terminal;

a coupling capacitor; and

and the level shifter is coupled to the voltage detection unit through the coupling capacitor.

16. The dynamic amplifier of claim 15, wherein the voltage detection unit comprises: a first detection capacitor coupled between the first voltage detection node and a common mode detection node of the voltage detection unit;

a second detection capacitor coupled between the second voltage detection node and the common mode detection node;

and

and the buffer is coupled with the first circuit breaking switch and the second circuit breaking switch and used for controlling the first circuit breaking switch and the second circuit breaking switch to be switched on or switched off according to a common mode voltage on the common mode detection node.

17. A gain enhancement method for a dynamic amplifier, the dynamic amplifier including an output capacitor, the gain enhancement method comprising:

resetting an output voltage of a first terminal of the output capacitor to a power supply voltage;

the output capacitor is charged or discharged by a charging or discharging current to execute amplification so as to increase or decrease the output voltage; and

the second end of the output capacitor is controlled to be switched from being coupled to a first reference voltage node to being coupled to a second reference voltage node so as to shift the output voltage.

18. The gain-enhancement method of claim 17, wherein the step of shifting the output voltage is performed at the end of the step of resetting the output voltage to the power-supply voltage.

19. The gain enhancement method of claim 17 wherein the step of shifting the output voltage is performed between the step of charging or discharging the output capacitor to perform amplification.

Technical Field

The present invention relates to a dynamic amplifier, and more particularly, to a gain enhancement technique for a dynamic amplifier.

Background

Dynamic amplifiers are commonly used in various circuits, such as Analog to Digital converters (ADCs), integrators (integrators), and output buffers. The dynamic amplifier is the same as a general operational amplifier, and is used to provide a gain of a certain magnitude to amplify an input signal. The difference between the dynamic amplifier and the general operational amplifier is that the general operational amplifier adopts a continuous time operation mode, and the dynamic amplifier adopts a discrete time operation mode. Thus, dynamic amplifiers are well suited for discrete-time circuitry, such as pipeline analog-to-digital converters (pipeline ADCs) or residual amplifiers (residual amplifiers) of discrete-time Delta Sigma modulator analog-to-digital converters (DSM ADCs), among others.

The dynamic amplifier may receive a differential input signal pair, which may generate differential currents for charging or discharging an output capacitor to amplify the input signal. A clock may dynamically control the amplifier to perform amplification, as its name "dynamic amplifier". The gain of the dynamic amplifier can be calculated as follows:

wherein, g_mIs the transconductance value, I, of a differential input pair of an amplifier_dFor differential input pair currents, Δ V_CMIs the variation of the common mode voltage of the output end changed by signal amplification. Further, Δ V_CMThis can be obtained by the following equation:

where C is the capacitance of the output capacitor, T_intIs the integration time of the amplification.

To increase the gain of the dynamic amplifier, the gain can be increased by increasing the integration time T_intTo increase the variation DeltaV of the common mode voltage_CM. However, the variation Δ V of the common mode voltage_CMPower supply limited by dynamic amplifierResponse voltage V_DDThus limiting the range of gain a.

In the prior art, an extra capacitor pair can be added to the dynamic amplifier for gain enhancement, wherein the charging/discharging operation can be implemented on different capacitors in two steps to prolong the integration time T_int. However, this implementation requires more capacitors, which increases the circuit cost, and the larger number of capacitors also results in higher power consumption.

In view of this, there is a need for improvement in the art.

Disclosure of Invention

It is therefore a primary object of the present invention to provide a novel gain enhancement technique for use in dynamic amplifiers to achieve higher gain while avoiding the above-mentioned problems.

The invention discloses a dynamic amplifier which comprises a first output capacitor, a first switch, a current source, a second switch, a voltage detection unit, a third switch and a level shifter. The first switch is coupled between a first end of the first output capacitor and a voltage detection node. The second switch is coupled to the current source and the voltage detection node. The voltage detection unit is coupled to the voltage detection node and the first switch. The third switch is coupled between the voltage detection node and a power supply terminal. The level shifter is coupled to a second end of the first output capacitor.

The invention also discloses a dynamic amplifier, which comprises a first output capacitor, a second output capacitor, a first circuit breaker, a second circuit breaker, a current source, an amplification control switch, a voltage detection unit, a first reset switch, a second reset switch, a coupling capacitor and a level shifter. The first circuit breaker is coupled between the first output capacitor and a first voltage detection node. The second circuit breaking switch is coupled between the second output capacitor and a second voltage detection node. The amplification control switch is coupled to the current source, the first voltage detection node and the second voltage detection node. The voltage detection unit is coupled to the first voltage detection node, the second voltage detection node, the first circuit breaker and the second circuit breaker. The first reset switch is coupled between the first voltage detection node and a power supply terminal. The second reset switch is coupled between the second voltage detection node and the power supply terminal. The level shifter is coupled to the voltage detection unit through the coupling capacitor.

The invention also discloses a gain enhancing method, which is used for a dynamic amplifier, the dynamic amplifier comprises an output capacitor, and the gain enhancing method comprises the following steps: resetting an output voltage of a first terminal of the output capacitor to a power supply voltage; the output capacitor is charged or discharged by a charging or discharging current to execute amplification so as to increase or decrease the output voltage; and controlling a second terminal of the output capacitor to switch from being coupled to a first reference voltage node to being coupled to a second reference voltage node so as to shift the output voltage.

Drawings

Fig. 1 is a schematic diagram of a general dynamic amplifier.

Fig. 2 shows an exemplary circuit configuration of the dynamic amplifier of fig. 1.

Fig. 3 shows a detailed operation of the dynamic amplifier of fig. 1.

Fig. 4 is a schematic diagram of a dynamic amplifier according to an embodiment of the invention.

Fig. 5 shows an exemplary circuit configuration of the dynamic amplifier of fig. 4.

Fig. 6 shows a detailed operation of the dynamic amplifier of fig. 4.

FIG. 7 is a diagram of a level shifter according to an embodiment of the present invention.

Fig. 8 is a schematic diagram of a dynamic amplifier according to an embodiment of the invention.

Fig. 9 is a schematic diagram of another dynamic amplifier according to an embodiment of the invention.

Fig. 10 is a schematic diagram of another dynamic amplifier according to an embodiment of the invention.

Fig. 11 shows a detailed operation of the dynamic amplifier of fig. 10.

Fig. 12 is a schematic diagram of another dynamic amplifier according to an embodiment of the invention.

Fig. 13 shows a detailed operation of the dynamic amplifier of fig. 12.

Fig. 14 is a schematic diagram of a gain enhancement process according to an embodiment of the invention.

Fig. 15 is a schematic diagram of a gain enhancement process according to an embodiment of the invention.

Wherein the reference numerals are as follows:

10. 40, 80, 90, 100, 120 dynamic amplifier

102、C_L1、C_L2、C_L3、C_L4Output capacitor

104. 104_1, 104_2 voltage-controlled current source

106 voltage detecting unit

108 power supply terminal

SW1, SW1_1 and SW1_2 disconnecting switch

SW2, SW2_1 and SW2_2 amplifying control switch

SW3, SW3_1, SW3_2, SW3_3, reset switch

SW3_4

ΔV_INInput signal

V_OUTOutput signal

ND, ND1, ND2 voltage detection node

M₁、M₂、M₃、M₄Input transistor

V_inp、V_innDifferential input voltage

I_d、I_d1、I_d2Electric current

Clkn, Clkp clock signal

Rst reset signal

V1、V2、V_LS、V_mn、V_mpVoltage of

V_outn、V_outpOutput voltage

V_XControl signal

V_DDPower supply voltage

V_comCommon mode voltage

V_THCritical value

ΔV_CM、ΔV_CM,LS、ΔV_CM0、ΔV_CM0,LSCommon mode voltage variation

ΔV_CM1、ΔV_CM1,LS

LS, LS1, LS2, 70 level shifter

CS Shift control Signal

N_REF1、N_REF2Reference voltage node

V_REF1、V_REF2Reference voltage

T_int、T_int0、T_int1、T_LSIntegration time

C_D1、C_D2Detecting capacitor

BUF buffer

MP 1P-type MOSFET

MN 1N-type MOSFET

C_LSCoupling capacitor

C_m1、C_m2Capacitor with a capacitor element

1206 voltage detecting and pre-charging module

140. 150 gain enhancement procedure

1400-1408, 1500-1512 steps

Detailed Description

Referring to fig. 1, fig. 1 is a schematic diagram of a general dynamic amplifier 10. As shown in fig. 1, the dynamic amplifier 10 includes an output capacitor 102, a Voltage-Controlled Current Source (VCCS) 104, a Voltage detection unit 106, and switches SW 1-SW 3. The dynamic amplifier 10 receives a power supply voltage V from a power supply terminal 108_DDThe power supply terminal 108 may be included within the dynamic amplifier 10 or may be provided independently of the dynamic amplifier 10. Based on a received input signal DeltaV_INThe voltage-controlled current source 104 can output a charging or discharging current to charge or discharge the output capacitor 102 for amplifying the input signal Δ V_INTo generate an output signal V_OUT. The voltage detecting unit 106 is coupled to a voltage detecting node ND and the switches SW1 and SW2, and can detect the output voltage of the output capacitor 102 through the voltage detecting node ND, and accordingly control the switches SW1 and/or SW2 to be turned on or off. The switch SW1 is coupled between one end of the output capacitor 102 and the voltage detection node ND, can be controlled by the voltage detection unit 106, and serves as a circuit breaker for breaking a signal path between the voltage detection node ND and the output capacitor 102. The switch SW2 is coupled between the voltage-controlled current source 104 and the voltage detection node ND, and can be used as an amplification control switch for controlling the voltage-controlled current source 104 to start outputting the charging or discharging current or stop outputting the charging or discharging current. The switch SW3 is coupled between the voltage detection node ND and the power supply terminal 108, and serves as a reset switch for resetting the output voltage of the output capacitor 102 to the power supply voltage V when turned on_DD。

Fig. 2 shows an exemplary circuit configuration of the dynamic amplifier 10 of fig. 1. The output capacitor 102 may be composed of two output capacitors C_L1And C_L2Composition, output capacitance C_L1And C_L2May be respectively disposed at the differential output terminals of the dynamic amplifier 10 and respectively coupled to the switches SW1_1 and SW1_ 2. The switches SW1_1 and SW1_2 are used as the detailed components of the circuit breaker SW1Receives control of the voltage detection unit 106. The voltage controlled current source 104 comprises an input transistor M₁And M₂Which respectively receive differential input voltages V_inpAnd V_innTo generate a current I_d1And I_d2. The amplification control switch SW2 may receive control of a clock signal Clkn, and the reset switch SW3 may receive control of a reset signal Rst. The voltage detecting unit 106 receives a voltage V1 at a voltage detecting node ND1 to detect the output capacitor C_L1Output voltage V of_outnAnd receives a voltage V2 at a voltage detection node ND2 to detect the output capacitor C_L2Output voltage V of_outp。

Fig. 3 shows the detailed operation of the dynamic amplifier 10, which includes a precharge phase and an amplification phase. In the precharge phase, the reset switch SW3 and the cut-off switch SW1 are turned on, and the amplification control switch SW2 is turned off. More specifically, the reset signal Rst is at a "low" level to turn on the reset switch SW3 (which may be implemented by a P-type metal oxide semiconductor field effect transistor (PMOS)); the clock signal Clkn is at a "low" level to turn off the amplification control switch SW2 (which may be implemented by an N-type metal oxide semiconductor field effect transistor (NMOS)). The switches SW1_1 and SW1_2 can be controlled by a control signal V from the voltage detecting unit 106_XAnd (4) opening. In this case, the current from the power supply terminal can be applied to the output capacitor C_L1And C_L2Charging is carried out so that the output voltage V is_outnAnd V_outpAnd the voltages V1 and V2 of the voltage detection nodes ND1 and ND2 are both reset to the power supply voltage V_DDAs shown in fig. 3.

When the precharge phase ends, the clock signal Clkn rises to the "high" level, causing the dynamic amplifier 10 to enter the amplification phase and begin performing signal amplification. During the amplification stage, the disconnection switch SW1 and the amplification control switch SW2 are turned on, and the reset switch SW3 is turned off. More specifically, the clock signal Clkn is at the "high" level to turn on the amplification control switch SW 2; the reset signal Rst is at a "high" level to turn off the reset switch SW 3. The switches SW1_1 and SW1_2 are continuously controlled by the control signal V from the voltage detecting unit 106_XAnd (4) opening. In this case, the outputOutput capacitor C_L1And C_L2The current I that can be generated by the voltage-controlled current source 104_d1And I_d2Discharge is performed and the voltage V is output_outnAnd V_outpAs the voltages V1 and V2 at the voltage detection nodes ND1 and ND2 drop, the dropping speed depends on the discharge current I_d1And I_d2The size of (2). During the discharging process, the voltage detecting unit 106 can detect the output voltage V_outnAnd V_outpOf the common-mode voltage V_comWhether a critical value V is reached_THWhen the common mode voltage V is detected_comReaches a critical value V_THThe voltage detecting unit 106 can detect the voltage via the control signal V_XThe switches SW1_1 and SW1_2 are turned off, and the amplification control switch SW2 is also turned off at the same time to stop the discharging operation.

Therefore, after the above-described discharge process, the input signal Δ V_IN(which is equal to the input voltage V_inpAnd V_innIs converted into a discharge current I)_d1And I_d2Is amplified to generate an output signal V_OUT(which is equal to the difference between voltages V1 and V2, and is also equal to the output voltage V_outnAnd V_outpThe difference of (d). In this example, the gain a of the dynamic amplifier 10 can be obtained by the following equation:

wherein, g_mFor the input transistor M₁And M₂Transconductance value of (1)_dEqual to one-half of the total current supplied to the voltage controlled current source 104, av_CMFor causing a common mode voltage V due to a discharge operation during signal amplification_comSupply voltage V from power supply_DDThe amount of voltage change dropped.

To increase the gain A, a level shifter is used to shift the output voltage V_outnAnd V_outpShifting to a higher voltage to increase the variation Δ V of the common mode voltage_CM. Referring to fig. 4, fig. 4 is a schematic diagram of a dynamic amplifier 40 according to an embodiment of the invention. The structure of the dynamic amplifier 40 is similar to that of the dynamic amplifier 10 of FIG. 1, so that it works wellIdentical components or modules are denoted by the same reference numerals. The difference between the dynamic amplifier 40 and the dynamic amplifier 10 is that the dynamic amplifier 40 further includes a level shifter LS coupled to the other end of the output capacitor 102. The level shifter LS receives a shift control signal CS for controlling the output capacitor 102 to be coupled to different reference voltage nodes.

In the embodiment shown in FIG. 4, the level shifter LS comprises a switch controlled by the shift control signal CS for selectively coupling the output capacitor 102 to a reference voltage node N_REF1Or another reference voltage node N_REF2. Reference voltage node N_REF1And N_REF2Different reference voltage values may be provided, so that when the switch is turned to switch the output capacitor 102 from being coupled to one reference voltage node to being coupled to another reference voltage node, the output voltage of the output capacitor 102 will shift to different levels.

Fig. 5 shows an exemplary circuit configuration of the dynamic amplifier 40 of fig. 4. In the dynamic amplifier 10 of fig. 2, the output capacitor C_L1And C_L2The upper end (e.g., top plate) of the output capacitor C is coupled to the voltage-controlled current source 104 through switches SW1_1 and SW1_2_L1And C_L2The lower end (e.g., the bottom plate) of the base is coupled to ground. In contrast, in the dynamic amplifier 40 of fig. 5, the output capacitor C_L1And C_L2Is also coupled to the voltage controlled current source 104, but the output capacitor C_L1And C_L2The lower ends of the level shifters are coupled to LS1 and LS2, respectively.

Fig. 6 shows the detailed operation of the dynamic amplifier 40, which also includes a precharge phase and an amplification phase, similar to the case of fig. 3. As shown in FIG. 6, at the end of the precharge phase, at the output capacitor C_L1And C_L2Voltage V at the lower end_LSFrom V_REF2Is raised to V_REF1The level shifters LS1 and LS2 control the transistors coupled to the reference voltage node N_REF2Output capacitor C_L1And C_L2The lower terminal is switched to be coupled to the reference voltage node N_REF1So as to be located at the output capacitor C_L1And C_L2Voltage of upper endV_outnAnd V_outpIs shifted to a higher level. Therefore, the variation Δ V of the output common mode voltage_CMAlso rises synchronously to Δ V_CM,LSAnd thus the gain of the dynamic amplifier 40. Likewise, the gain enhancement method of the present invention can also be viewed as being implemented by increasing the integration time of the discharge of the output capacitor, as shown in FIG. 6, from T_intIs lifted to T_int+T_LS。

In one embodiment, the voltage detection unit 106 includes two detection capacitors C_D1And C_D2And a buffer BUF, as shown in FIG. 5. Detecting capacitor C_D1Coupled to the voltage detection node ND1 for receiving the voltage V1 to detect the output capacitor C_L1Output voltage V of_outn. Detecting capacitor C_D2Coupled to the voltage detection node ND2 for receiving the voltage V2 to detect the output capacitor C_L2Output voltage V of_outp. Detecting capacitor C_D1And C_D2Further, an output voltage V is obtained at a common mode detection node_outnAnd V_outpOf the common-mode voltage V_com. The buffer BUF is coupled to the switches SW1_1 and SW1_2 for receiving the common mode voltage V_comIs converted into a control signal V_XAccording to a common mode voltage V_comTo control the switches SW1_1 and SW1_2 to be turned on or off.

It is noted that the level shifter of the present invention can be implemented in various ways or can be any type of level shifter, such as capacitive, resistive, or current. In one embodiment, the level shifter may be implemented as a structure having an inverter, such as the level shifter 70 shown in FIG. 7. The inverter structure, which may be used as a switch to control the coupling of the output capacitor, includes a P-type mosfet MP1 and an N-type mosfet MN 1. The P-type MOSFET MP1 is coupled between the output terminal of the level shifter 70 and the reference voltage node N_REF1In the meantime. An N-type MOSFET MN1 is coupled between the output of the level shifter 70 and a reference voltage node N_REF2In the meantime. The P-type MOSFET MP1 and the N-type MOSFET MN1 are controlled by the same shift control signal to selectCoupling the output terminal to the reference voltage node N_REF1Or reference voltage node N_REF2. In this example, reference voltage node N_REF1Can output a reference voltage V_REF1At a level equal to the power supply voltage or any voltage greater than the reference voltage V_REF2The level of (d); reference voltage node N_REF2Can output a reference voltage V_REF2At a level equal to ground or any voltage lower than the reference voltage V_REF1Of (c) is detected.

As shown in fig. 7, the shift control signal CS may be a logic signal generated by a digital control circuit, for example. If the shift control signal CS is at "high" level, the NFET MN1 is turned on and the PFET MP1 is turned off, such that the level shifter 70 can output the reference voltage V_REF2As a voltage V_LSAnd transmitted to the output capacitor. If the shift control signal CS is at "low" level, the PMOS 1 is turned on and the NMOS MN1 is turned off, so that the level shifter 70 can output the reference voltage V_REF1As a voltage V_LSAnd transmitted to the output capacitor. In this case, the level shift method for the output capacitance of the dynamic amplifier can be implemented by changing the state of the shift control signal CS.

The dynamic amplifier 40 of fig. 5 is a level shifter coupled to the lower end of the output capacitor (the lower end of the output capacitor is originally coupled to ground, see the dynamic amplifier 10 shown in fig. 2) to implement the level shifting method of the present invention. In this way, the level shifting method can be realized without adding extra capacitance. But in other embodiments the level shifting method may be implemented in other ways.

Referring to fig. 8, fig. 8 is a schematic diagram of a dynamic amplifier 80 according to an embodiment of the invention. As shown in fig. 8, the structure of the dynamic amplifier 80 is similar to that of the dynamic amplifier 10 in fig. 2, so that the components or modules with the same functions are represented by the same symbols. The difference between the dynamic amplifier 80 and the dynamic amplifier 10 is that the dynamic amplifier 80 further comprises an output capacitor C_L3And C_L4Respectively coupled to the differential output terminals of the dynamic amplifier 80. Output capacitorC_L3And C_L4The other end of the level shifter is coupled to level shifters LS1 and LS2, respectively. In this case, each output terminal of the dynamic amplifier 80 is coupled to two output capacitors, one of which is coupled to a level shifter and the other of which is coupled to ground. When the level shifter switches to change its output voltage level, the output voltage of the dynamic amplifier 80 is shifted.

In the dynamic amplifier 80, the level shifting method can be regarded as adding an additional output capacitor and a corresponding level shifter to the general dynamic amplifier 10 of fig. 2. Alternatively, the implementation of the dynamic amplifier 80 can be regarded as dividing each output capacitor of the dynamic amplifier 10 into two parts, and then coupling one part to the level shifter and the other part to the ground.

Referring to fig. 9, fig. 9 is a schematic diagram of another dynamic amplifier 90 according to another embodiment of the invention. As shown in fig. 9, the structure of the dynamic amplifier 90 is similar to that of the dynamic amplifier 40 in fig. 5, so that the components or modules with the same functions are represented by the same symbols. The difference between the dynamic amplifier 90 and the dynamic amplifier 40 is that in the dynamic amplifier 90, the level shifter is coupled to the voltage detection unit 106 instead of the output capacitor C_L1And C_L2. As shown in FIG. 9, the dynamic amplifier 90 includes a coupling capacitor C_LSAnd a level shifter LS. The level shifter LS is coupled to the output voltage V at the common mode detection node of the voltage detection unit 106_outnAnd V_outpOf the common-mode voltage V_comShifting so that the common mode voltage V_comDown to critical value V_THIs delayed, thereby increasing the integration time for amplifying the signal. Thus, the gain of the dynamic amplifier 90 can be increased.

Referring back to fig. 5, two level shifters are respectively coupled to the output capacitor C of the dynamic amplifier 40_L1And C_L2. If the output capacitance C_L1And C_L2When there is mismatch between them, the output voltage V will also be caused_outnAnd V_outpMismatch of the amount of shift up. In contrast, as shown in FIG. 9, only one level shifter LS is usedTo the output voltage V_outnAnd V_outpOf the common-mode voltage V_comThe shift is performed so that the shift amounts applied to the two output terminals are necessarily the same, thereby solving the above-mentioned mismatch problem.

It is noted that one of the objectives of the present invention is to provide a gain enhancement method for a dynamic amplifier, which can shift the level of the output voltage or the output common-mode voltage of the dynamic amplifier to increase the variation of the output common-mode voltage and increase the integration time of the amplification. And those skilled in the art may make modifications or variations thereon without being limited thereto. For example, in the above embodiments, the level shifter may change its state to output the voltage V at the end of the precharge phase_outnAnd V_outpShifting to a higher level as shown in fig. 6. In another embodiment, the level shifting operation may also be implemented at another point in time. For example, in the dynamic amplifier 40, the level shifter LS may control the node N originally coupled to the reference voltage during the amplification phase_REF2The output capacitor is switched to be coupled to the reference voltage node N_REF1To shift the level of the output voltage.

It should be noted that the gain enhancement method of the present invention can be applied to any type of dynamic amplifier, and the level shifter and the gain enhancement method of the present invention can be applied as long as the output signal of the dynamic amplifier is generated by charging or discharging the output capacitor through the current outputted by the voltage-controlled current source.

Referring to fig. 10, fig. 10 is a schematic diagram of another dynamic amplifier 100 according to an embodiment of the invention. As shown in fig. 10, the structure of the dynamic amplifier 100 is similar to that of the dynamic amplifier 40 in fig. 5, so that components or modules with similar functions are denoted by similar symbols. Dynamic amplifier 100 differs from dynamic amplifier 40 in that dynamic amplifier 100 includes two additional transistors M₃And M₄As a source follower (source follower) and, in addition to the output capacitance C_L1And C_L2In addition, the dynamic amplifier 100 further includes two capacitors C_m1And C_m2Coupled to the transistors M respectively₃And M₄The source terminal of (1). Capacitor C_m1And C_m2Can receive the control of the reset switches SW3_1 and SW3_4 through the capacitor C_m1、C_m2And an output capacitor C_L1、C_L2Discharging in sequence can achieve higher gain.

Fig. 11 shows the detailed operation of the dynamic amplifier 100. similar to fig. 6, the operation of the dynamic amplifier 100 also includes a precharge phase and an amplification phase. In the pre-charge phase, the capacitor C_m1、C_m2、C_L1And C_L2The lower voltage is reset to the power supply voltage V at the same time_DD. When the amplification phase begins, the discharge current of the voltage controlled current source 104 begins to couple to the capacitor C_m1And C_m2Discharging is carried out when the voltage V is_mnAnd V_mpDown to a specific threshold (i.e. the power supply voltage V)_DDMinus transistor M₃And M₄Threshold voltage of) of the transistor M, the transistor M₃And M₄Is turned on and the discharging current of the voltage controlled current source 104 starts to the output capacitor C_L1And C_L2And discharging is performed. In this case, the amplification stage includes a two-stage discharge period, thereby increasing the integration time of the amplification. At the same time, the variation Δ V of the output common mode voltage_CMCan be considered as equivalent extension to Δ V_CM0The gain of the dynamic amplifier 100 is increased by increasing the output common mode voltage variation.

In addition, when the output capacitor C_L1And C_L2When the discharge is started, the level shifters LS1 and LS2 can respectively control the output voltage V_outnAnd V_outpIs shifted up as shown in fig. 11. This operation can further increase the variation of the output common mode voltage to Δ V_CM0,LSAnd the integration time is also synchronously increased to T_int0+T_LSThereby achieving the effect of gain enhancement. Output voltage V for level shifters LS1 and LS2_outnAnd V_outpThe detailed operation of shifting the level is similar to the embodiments shown in fig. 4 to 6, and is not repeated here.

Referring to fig. 12, fig. 12 is a schematic diagram of a dynamic amplifier 120 according to another embodiment of the invention. As shown in fig. 12The structure of the dynamic amplifier 120 is similar to that of the dynamic amplifier 40 in fig. 5, and therefore, components or modules with similar functions are denoted by similar symbols. The dynamic amplifier 120 differs from the dynamic amplifier 40 in that the dynamic amplifier 120 includes two voltage-controlled current sources 104_1 and 104_2, and the voltage-controlled current source 104_1 is composed of two N-type mosfets M₁And M₂The voltage-controlled current source 104_2 is composed of two P-type metal oxide semiconductor field effect transistors M₃And M₄The composition is as follows. The voltage detecting and pre-charging module 1206 can detect the output voltage V in the amplifying stage_outnAnd V_outpAnd resetting the output voltage V in the precharge phase_outnAnd V_outp。

Fig. 13 shows the detailed operation of the dynamic amplifier 120, and similar to fig. 6, the operation of the dynamic amplifier 120 also includes a precharge phase and an amplification phase. In the pre-charge phase, at the capacitor C_L1And C_L2The voltage at the upper end is reset to the power supply voltage V_DD. When the amplification stage begins, the discharging current output by the voltage-controlled current source 104_1 is applied to the capacitor C_L1And C_L2Discharging to output voltage V_outnAnd V_outpAnd correspondingly decreases. If the voltage detection and pre-charge module 1206 detects the output voltage V_outnAnd V_outpOf the common-mode voltage V_comWhen the threshold value is decreased, the nmos transistor of the voltage-controlled current source 104_1 is turned off by the switch SW2_1, and the pmos transistor of the voltage-controlled current source 104_2 is turned on by the switch SW2_ 2. Then, the voltage-controlled current source 104_2 can output a charging current to the output capacitor C_L1And C_L2Charging is carried out to make the output voltage V_outnAnd V_outpAnd correspondingly rises. If the voltage detection and pre-charge module 1206 detects the output voltage V_outnAnd V_outpOf the common-mode voltage V_comWhen the voltage rises to another threshold, the voltage detection and precharge module 1206 may turn off the disconnect switches SW1_1 and SW1_ 2. In this case, the voltage detecting and pre-charging module 1206 can set a plurality of threshold values for controlling the operations of the voltage-controlled current sources 104_1 and 104_2 and the disconnectors SW1_1 and SW1_ 2. Dynamic amplifierThe amplifier 120 is a bi-directional amplifier, in which the signal amplification is achieved by the discharging current from the voltage controlled current source 104_1 of the NFET and the charging current from the voltage controlled current source 104_2 of the PFET. Therefore, the amplification stage includes a discharge period and a charge period, thereby increasing the integration time of amplification. At the same time, the variation Δ V of the output common mode voltage_CMCan be considered as equivalent extension to Δ V_CM1The gain of the dynamic amplifier 120 is increased by increasing the output common mode voltage variation.

In addition, when the discharge is over and the charge is started, the level shifters LS1 and LS2 can respectively output the output voltage V_outnAnd V_outpIs shifted down as shown in fig. 13. This operation can further extend the variation of the output common mode voltage to Δ V_CM1,LSAnd the integration time is also synchronously increased to T_int1+T_LSThereby achieving the effect of gain enhancement. It should be noted that the level shift operation can be performed on the output capacitor C of the voltage-controlled current source 104_2_L1And C_L2Is performed before charging is performed so that the output voltage V is_outnAnd V_outpCan reach larger common mode voltage variation and longer integration time. In the embodiment shown in FIG. 6, the level shift operation is performed by a voltage-controlled current source pair to output capacitor C_L1And C_L2The upward shift performed before the discharge is performed can be used to increase the common mode voltage variation and the integration time.

In another embodiment, the level shifting operation may be performed multiple times to further boost the gain of the dynamic amplifier. For example, in the dynamic amplifier 120 shown in FIG. 12, when the voltage-controlled current source 104_1 outputs a discharging current to the output capacitor C_L1And C_L2Before discharging (i.e., the point in time when the precharge phase ends), the level shifters LS1 and LS2 can output the voltage V_outnAnd V_outpShift up, and then, when the voltage-controlled current source 104_2 outputs a charging current to the output capacitor C_L1And C_L2Before charging, the level shifters LS1 and LS2 can output the voltage V_outnAnd V_outpMove downwardsA bit. To achieve this, level shifters LS1 and LS2 can control output capacitor C_L1And C_L2The lower terminal of the switch is coupled to a first reference voltage node for receiving the lower reference voltage, to a second reference voltage node for receiving the higher reference voltage, and then back to the first reference voltage node for receiving the lower reference voltage. Furthermore, during the amplifying stage, the discharging and charging operations can be performed alternately for a plurality of times, so that the level shifting operations (the up-shift and the down-shift performed sequentially) can be performed correspondingly, and the gain of the dynamic amplifier 120 can be increased without limitation.

Compared to the dynamic amplifier 100 shown in fig. 10, the dynamic amplifier 120 can further achieve the effect of reducing the number of capacitors, and can achieve lower circuit cost. Meanwhile, in each pre-charging stage, the number of capacitors to be pre-charged is small, and therefore the consumed electric quantity is low. Furthermore, in the dynamic amplifier 120, the voltage-controlled current source 104_2 can couple to the output capacitor C during the amplification stage_L1And C_L2Charging is performed, the charging operation can drive the output voltage V_outnAnd V_outpTo a voltage closer to the power supply voltage V_DDSo that, in the next precharge phase, the output capacitor C is precharged_L1And C_L2The amount of power required to perform the precharge is also reduced.

It should be noted that the level shifters of fig. 8 and 9 may also be applied to the dynamic amplifiers 100 and 120, i.e., some of the output capacitors are coupled to the level shifter and the other output capacitors are coupled to ground, and/or a level shifter is coupled to the common mode detection node of the voltage detection unit.

The gain enhancement operation of the present invention can be summarized as a gain enhancement process 140, as shown in FIG. 14. The gain enhancement process 140 may be applied to any of the dynamic amplifiers 40, 80, 90, 100, and 120, and includes the steps of:

step 1400: and starting.

Step 1402: an output voltage of a first end of the output capacitor is reset to a power supply voltage.

Step 1404: a second terminal of the control output capacitor is switched from being coupled to a first reference voltage node to receive the lower reference voltage to being coupled to a second reference voltage node to receive the higher reference voltage, so as to shift the output voltage upward.

Step 1406: the output capacitor is discharged with a discharge current to perform amplification for reducing the output voltage.

Step 1408: and (6) ending.

For the detailed operation and variation of the gain enhancement process 140, reference is made to the description in the above paragraphs, which are not repeated herein. It is noted that the gain enhancement process 140 may achieve gain enhancement by shifting the output voltage upward, however, in another embodiment, gain enhancement may also be achieved by shifting the output voltage downward, which may also be used for the dynamic amplifier 120. As shown in fig. 15, a gain enhancement process 150 can achieve gain enhancement by shifting the output voltage up and down, which includes the following steps:

step 1500: and starting.

Step 1502: an output voltage of a first end of the output capacitor is reset to a power supply voltage.

Step 1504: a second terminal of the control output capacitor is switched from being coupled to a first reference voltage node to receive the lower reference voltage to being coupled to a second reference voltage node to receive the higher reference voltage, so as to shift the output voltage upward.

Step 1506: the output capacitor is discharged with a discharge current to perform amplification for reducing the output voltage.

Step 1508: the second terminal of the output capacitor is controlled to switch from being coupled to the second reference voltage node to receive the higher reference voltage to being coupled to the first reference voltage node to receive the lower reference voltage, so as to shift the output voltage downwards.

Step 1510: the output capacitor is charged with a charging current to perform amplification for increasing the output voltage.

Step 1512: and (6) ending.

It is noted that steps 1504-1510 can be repeated to increase the gain without limitation. For further details and variations of the gain enhancement process 150, reference is made to the above paragraphs, which are not repeated herein.

In summary, embodiments of the present invention provide a gain enhancement method for a dynamic amplifier, which can shift the level of the output voltage or the output common mode voltage of the dynamic amplifier to increase the variation of the output common mode voltage and increase the integration time of the amplification. The level shifter having a switch may be coupled to the output capacitor or the voltage detection unit to implement the gain enhancement method. The gain enhancement method using the shifted voltage level may be performed at a time point when the precharge phase is ended or during the amplification phase, and may be performed one or more times according to system requirements. The gain enhancement method of the present invention can be used for any type of dynamic amplifier or with any structure, and is not limited to the embodiments provided in this specification.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.