阅读说明：本技术 瞬态稳定的绝缘体上硅场效应晶体管 (Transient stable silicon-on-insulator field effect transistor ) 是由 罗伯特·马克·恩格尔基尔克 凯特·巴尔格罗夫 克里斯多佛·C·墨菲 泰罗·塔皮奥·兰塔 西蒙 于 2018-04-30 设计创作，主要内容包括：避免或减轻在绝缘体上硅(SOI)衬底特别是具有富陷阱层的SOI衬底中产生累积电荷的变化的集成电路(IC)。在一个实施方式中,FET被配置成使得在待机模式下,关断FET,同时保持与活动模式期间基本相同的V<Sub>DS</Sub>。在另一实施方式中,FET被配置成使得在待机模式下,中断流经FET的电流,同时保持与活动模式期间基本相同的V<Sub>GS</Sub>。在另一实施方式中,FET被配置成使得在待机模式下,FET被切换至使V<Sub>GS</Sub>和V<Sub>DS</Sub>二者均保持接近它们各自的活动模式操作电压的非常低的电流状态(“涓流电流”状态)。可选地,可以在IC衬底中形成S接触件以创建包括对累积电荷影响敏感的FET的受保护区域。(Avoiding or mitigating variations in accumulated charge generation in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layerAn Integrated Circuit (IC) of (a). In one embodiment, the FET is configured such that in standby mode, the FET is turned off while maintaining substantially the same V as during active mode DS . In another embodiment, the FET is configured such that in a standby mode, current flow through the FET is interrupted while maintaining substantially the same V as during an active mode GS . In another embodiment, the FET is configured such that in the standby mode, the FET is switched such that V GS And V DS Both remain in a very low current state ("trickle current" state) close to their respective active mode operating voltages. Optionally, S-contacts may be formed in the IC substrate to create protected regions comprising FETs that are sensitive to accumulated charge effects.)

1. An integrated circuit susceptible to accumulated charge and fabricated on a silicon-on-insulator (SOI) substrate, the integrated circuit comprising at least one Field Effect Transistor (FET) having V_DSIs characterized and configured such that in standby mode, the FET is turned off while maintaining substantially the same V as during active mode_DSThereby eliminating or reducing the variation in accumulated charge.

2. A circuit fabricated on a silicon-on-insulator (SOI) substrate as part of an integrated circuit susceptible to accumulated charge, the circuit comprising:

(a) at least one fieldAn effect transistor (FET) having at least one drain, source, gate, V_DSA characteristic and a signal path between the drain and the source through the FET;

(b) a first switch coupled to the gate of the FET, the first switch configured to selectively couple the gate to one of a bias voltage or a standby voltage source; and

(c) a second switch coupled to the signal path of the FET, the second switch configured to selectively couple the signal path to one of a load or a pseudo-load voltage source;

wherein, in an active mode, the first switch couples the gate of the FET to the bias voltage and the second switch couples the signal path of the FET to the load; and is

Wherein in a standby mode, the first switch couples the gate of the FET to the standby voltage source and the second switch couples the signal path of the FET to the pseudo-load voltage source, thereby maintaining substantially the same V as during the active mode_DSCharacteristic, and thereby eliminate or reduce variations in the accumulated charge.

3. The invention of claim 2 wherein a standby mode pseudo-load voltage source outputs a voltage approximately equal to a voltage present on the drain of the FET during active mode operation.

4. An integrated circuit susceptible to accumulated charge and fabricated on a silicon-on-insulator (SOI) substrate, the integrated circuit comprising at least one Field Effect Transistor (FET) having V_GSIs characterized and configured such that in a standby mode, the current through the FET is interrupted while maintaining substantially the same V as during an active mode_GSThereby eliminating or reducing the variation in accumulated charge.

5. A circuit fabricated on a silicon-on-insulator (SOI) substrate as part of an integrated circuit susceptible to accumulated charge, the circuit comprising:

(a) at least one Field Effect Transistor (FET) having a drain, a source, a gate, V_GSA characteristic and a signal path between the drain and the source through the FET; and

(b) a switch coupled to the signal path of the FET, the switch configured to selectively couple the signal path to a load or interrupt current flowing through the signal path of the FET;

wherein, in an active mode, the switch couples the signal path of the FET to the load; and is

Wherein in a standby mode, the switch interrupts current flow through the signal path of the FET to maintain substantially the same V as during the active mode_GSCharacteristic, and thereby eliminate or reduce variations in the accumulated charge.

6. An integrated circuit susceptible to accumulated charge and fabricated on a silicon-on-insulator (SOI) substrate, the integrated circuit comprising at least one Field Effect Transistor (FET) having a drain, a source, a gate, a V_DSCharacteristic, V_GSA characteristic and a signal path between the drain and the source through the FET and configured such that in a standby mode, the FET is switched to have the V of the FET with respect to current flowing through the signal path_GSCharacteristic and said V_DSCharacteristics both remain close to for the V_GSCharacteristic and said V_DSThe respective active modes of the characteristics operate very low current states of the voltage, thereby reducing variations in the accumulated charge.

7. A circuit fabricated on a silicon-on-insulator (SOI) substrate as part of an integrated circuit susceptible to accumulated charge, the circuit comprising:

(a) at least one Field Effect Transistor (FET) having a drain, a source, a gate, V_DSCharacteristic, V_GSA characteristic and a signal path between the drain and the source through the FET; and

(b) a switch coupled to the signal path of the FET, the switch configured to selectively couple the signal path to either a normal current flow path or a trickle current path;

wherein, in an active mode, the switch couples the signal path of the FET to the normal current flow path; and is

Wherein in a standby mode, the switch couples the signal path of the FET to the trickle current path such that the V of the FET_GSCharacteristic and said V_DSCharacteristics both approaching for the V_GSCharacteristic and said V_DSThe respective active modes of the characteristics operate on the voltage, thereby reducing variations in the accumulated charge.

8. The invention as defined in claim 7 wherein said trickle current path has a high resistance relative to said normal current flow path.

9. The invention as defined in claim 7 wherein said trickle current path comprises a regulated current source relative to said normal current flow path, said regulated current source causing only trickle current to flow through said FET.

10. A circuit fabricated on a silicon-on-insulator (SOI) substrate as part of an integrated circuit susceptible to accumulated charge, the circuit comprising:

(a) at least one Field Effect Transistor (FET) having a drain, a source, a gate, V_DSCharacteristic, V_GSA characteristic and a signal path between the drain and the source through the FET; and

(b) a switch coupled to the signal path of the FET, the switch configured to selectively couple the signal path to a load resistance or a high resistance;

wherein, in an active mode, the switch couples the signal path of the FET to the load resistance; and is

Wherein in a standby mode, the switch couples the signal path of the FET to the high resistance such that the V of the FET_GSCharacteristic and said V_DSCharacteristics both approaching for the V_GSCharacteristic and said V_DSThe respective active modes of the characteristics operate on the voltage, thereby reducing variations in the accumulated charge.

11. The invention of claim 10, wherein the high resistance is at least about 100 times greater than the load resistance.

12. A circuit fabricated on a silicon-on-insulator (SOI) substrate as part of an integrated circuit susceptible to accumulated charge, the circuit comprising:

(a) at least one Field Effect Transistor (FET) having a drain, a source, a gate, V_DSCharacteristic, V_GSA characteristic and a signal path between the drain and the source through the FET; and

(b) a switch coupled to the signal path of the FET, the switch configured to selectively couple the signal path to a first current source or to a second current source, the second current source providing a lower current than the first current source;

wherein, in an active mode, the switch couples the signal path of the FET to the first current source; and is

Wherein, in a standby mode, the switch couples the signal path of the FET to the second current source such that the V of the FET_GSCharacteristic and said V_DSCharacteristics both approaching for the V_GSCharacteristic and said V_DSThe respective active modes of the characteristics operate on the voltage, thereby reducing variations in the accumulated charge.

13. An integrated circuit susceptible to accumulated charge and fabricated on a silicon-on-insulator (SOI) substrate, the integrated circuit comprising:

(a) having a V_DSCharacteristic sum V_GSAt least one Field Effect Transistor (FET) of a characteristic; and

(b) at least one switch coupled to the FET and configured to be set to a standby mode in which no significant current flows through the at least one FET while maintaining substantially the same VV for the at least one FET as during active mode_DSCharacteristic sum V_GSThereby eliminating or reducing the variation in accumulated charge.

14. The invention of claim 1, 2, 4, 5,6, 7, 10, 12, or 13 wherein the SOI substrate comprises a trap rich layer that is susceptible to accumulated charge in or near the trap rich layer.

15. The invention of claim 1, 2, 4, 5,6, 7, 10, 12, or 13, further comprising at least one substrate contact in proximity to at least one FET.

16. The invention of claim 1, 2, 4, 5,6, 7, 10, 12, or 13, further comprising an at least partial ring of substrate contacts around at least one FET.

17. A method for eliminating or reducing variations in accumulated charge in an integrated circuit that is susceptible to accumulated charge and that is fabricated on a silicon-on-insulator (SOI) substrate, the method comprising:

(a) providing a compound having V_DSAt least one Field Effect Transistor (FET) of a characteristic; and

(b) configuring the at least one FET to be in standbyIn mode, the FET is turned off while maintaining substantially the same V as during active mode_DSThereby eliminating or reducing the variation in accumulated charge.

18. A method for eliminating or reducing variation in accumulated charge in a circuit fabricated on a silicon-on-insulator (SOI) substrate as part of an integrated circuit susceptible to accumulated charge, the method comprising:

(a) providing at least one Field Effect Transistor (FET) having a drain, a source, a gate, V_DSA characteristic and a signal path between the drain and the source through the FET;

(b) coupling a first switch to the gate of the FET and configured to selectively couple the gate to one of a bias voltage or a voltage source;

(c) coupling a second switch to the signal path of the FET and configured to selectively couple the signal path to one of a load or a pseudo-load voltage source;

(d) in an active mode, setting the first switch to couple the gate of the FET to the bias voltage and the second switch to couple the signal path of the FET to the load; and

(e) in a standby mode, the first switch is arranged to couple the gate of the FET to the voltage source and the second switch is arranged to couple the signal path of the FET to the pseudo-load voltage source, thereby maintaining substantially the same V as during the active mode_DSCharacteristic, and thereby eliminate or reduce variations in the accumulated charge.

19. The method of claim 18 wherein a standby mode pseudo-load voltage source outputs a voltage approximately equal to a voltage present on the drain of the FET during active mode operation.

20. A method for eliminating or reducing variations in accumulated charge in an integrated circuit that is susceptible to accumulated charge and that is fabricated on a silicon-on-insulator (SOI) substrate, the method comprising:

(a) providing a compound having V_GSAt least one Field Effect Transistor (FET) of a characteristic; and

(b) configuring the at least one FET such that in a standby mode, current flow through the FET is interrupted while maintaining substantially the same V as during an active mode_GSThereby eliminating or reducing the variation in accumulated charge.

21. A method for eliminating or reducing variation in accumulated charge in a circuit fabricated on a silicon-on-insulator (SOI) substrate as part of an integrated circuit susceptible to accumulated charge, the method comprising:

(a) providing at least one Field Effect Transistor (FET) having a drain, a source, a gate, V_GSA characteristic and a signal path between the drain and the source through the FET;

(b) coupling a switch to the signal path of the FET and configuring the switch to selectively couple the signal path to a load or interrupt current flow through the signal path of the FET;

(c) in an active mode, setting the switch to couple the signal path of the FET to the load; and

(d) in a standby mode, the switch is set to interrupt current flowing through the signal path of the FET so as to maintain substantially the same V as during the active mode_GSThereby eliminating or reducing the variation in accumulated charge.

22. A method for eliminating or reducing variations in accumulated charge in an integrated circuit that is susceptible to accumulated charge and that is fabricated on a silicon-on-insulator (SOI) substrate, the method comprising:

(a) provide forAt least one Field Effect Transistor (FET) having a drain, a source, a gate, V_DSCharacteristic, V_GSA characteristic and a signal path between the drain and the source through the FET; and

(b) configuring the at least one FET such that in a standby mode, switching the FET to cause the V of the FET relative to current flowing through the signal path_GSCharacteristic and said V_DSCharacteristics both remain close to for the V_GSCharacteristic and said V_DSThe respective active modes of the characteristics operate very low current states of the voltage, thereby reducing variations in the accumulated charge.

23. A method for eliminating or reducing variation in accumulated charge in a circuit fabricated on a silicon-on-insulator (SOI) substrate as part of an integrated circuit susceptible to accumulated charge, the method comprising:

(a) providing at least one Field Effect Transistor (FET) having a drain, a source, a gate, V_DSCharacteristic, V_GSA characteristic and a signal path between the drain and the source through the FET;

(b) coupling a switch to the signal path of the FET and configuring the switch to selectively couple the signal path to either a normal current flow path or a trickle current path;

(c) in an active mode, setting the switch to couple the signal path of the FET to the normal current flow path; and

(d) in a standby mode, setting the switch to couple the signal path of the FET to the trickle current path such that the V of the FET_GSCharacteristic and said V_DSCharacteristics are all close to those for the V_GSCharacteristic and said V_DSThe respective active modes of the characteristics operate on the voltage, thereby reducing variations in the accumulated charge.

24. The method of claim 23, wherein the trickle current path has a high resistance relative to the normal current flow path.

25. The method of claim 23, further comprising providing a regulated current source coupled to the trickle current path relative to the normal current flow path, the regulated current source causing only trickle current to flow through the FET.

26. A method for eliminating or reducing variation in accumulated charge in an integrated circuit fabricated on a silicon-on-insulator (SOI) substrate as part of the integrated circuit susceptible to accumulated charge, the method comprising:

(a) providing at least one Field Effect Transistor (FET) having a drain, a source, a gate, V_DSCharacteristic, V_GSA characteristic and a signal path between the drain and the source through the FET;

(b) coupling a switch to the signal path of the FET, the switch configured to selectively couple the signal path to a load resistance or to a high resistance;

(c) in an active mode, setting the switch to couple the signal path of the FET to the load resistance; and

(d) in a standby mode, setting the switch to couple the signal path of the FET to the high resistance such that the V of the FET_GSCharacteristic and said V_DSCharacteristics both approaching for the V_GSCharacteristic and said V_DSThe respective active modes of the characteristics operate on the voltage, thereby reducing variations in the accumulated charge.

27. The method of claim 26, wherein the high resistance is at least about 100 times greater than the load resistance.

28. A method for eliminating or reducing a change in accumulated charge in an integrated circuit fabricated on a silicon-on-insulator (SOI) substrate as part of the integrated circuit susceptible to the accumulated charge, the method comprising:

(a) providing at least one Field Effect Transistor (FET) having a drain, a source, a gate, V_DSCharacteristic, V_GSA characteristic and a signal path between the drain and the source through the FET;

(b) coupling a switch to the signal path of the FET, the switch configured to selectively couple the signal path to a first current source or to a second current source, the second current source providing a lower current than the first current source;

(c) in an active mode, setting the switch to couple the signal path of the FET to the first current source; and

(d) in a standby mode, setting the switch to couple the signal path of the FET to the second current source such that the V of the FET_GSCharacteristic and said V_DSCharacteristics both approaching for the V_GSCharacteristic and said V_DSThe respective active modes of the characteristics operate on the voltage, thereby reducing variations in the accumulated charge.

29. A method for eliminating or reducing variations in accumulated charge in an integrated circuit that is susceptible to accumulated charge and that is fabricated on a silicon-on-insulator (SOI) substrate, the method comprising:

(a) providing a compound having V_DSCharacteristic sum V_GSAt least one Field Effect Transistor (FET) of a characteristic; and

(b) configuring the at least one FET such that in a standby mode, no significant current flows through the at least one FET while maintaining substantially the same Vv for the at least one FET as during an active mode_DSCharacteristic sum V_GSThereby eliminating or reducing the variation in accumulated charge.

30. The method of claim 17, 18, 20, 21, 22, 23, 26, 28 or 29, wherein the SOI substrate comprises a trap rich layer that is susceptible to accumulated charge in or near the trap rich layer.

31. The method of claim 17, 18, 20, 21, 22, 23, 26, 28, or 29, further comprising providing at least one substrate contact in proximity to at least one FET.

32. The method of claim 17, 18, 20, 21, 22, 23, 26, 28 or 29, further comprising providing an at least partial ring of substrate contacts around at least one FET.

(1) Field of the invention

The present invention relates to electronic circuits and, more particularly, to radio frequency circuits fabricated using silicon-on-insulator technology.

Background

Disclosure of Invention

The present invention includes several types of Radio Frequency (RF) Integrated Circuits (ICs) that avoid or mitigate the generation of accumulated charge in a silicon-on-insulator (SOI) substrate, particularly one having a trap rich layer, by avoiding having at least some Field Effect Transistors (FETs) within the circuit in a fully off state. By keeping the standby operating conditions of such critical FETs at or as close to the active state as possible, the accumulated charge is stabilized at a nearly constant level. An important insight into the function of such FETs is the following recognition: the smaller the voltage variations at certain nodes of FETs within an SOI IC, the more stable the charge that can accumulate due to circuit activity in the active layer of the IC.

In a first general embodiment, the FET is configured such that in standby mode, the FET is turned off, while maintaining substantially the same V as during active mode_DSThereby eliminating or reducing the variation in the accumulated charge.

In a second general embodiment, the FET is configured such that in a standby mode, current flow through the FET is interrupted while maintaining substantially the same V as during an active mode_GSThereby eliminating or reducing the variation in the accumulated charge.

In a third general embodiment, the FET is configured such that in the standby mode, the FET is switched such that V_GSAnd V_DSBoth maintain very low current states near their respective active mode operating voltages (') "Trickle current "state) to reduce the change in accumulated charge.

In some implementations, an S-contact is formed in an IC substrate to create a protected region including a FET that is sensitive to accumulated charge effects. More specifically, the S-contact substantially surrounds each circuit to be protected, substantially forming a respective "well" at least partially surrounded by a "ring" of S-contacts. The loop of the S-contact reduces the substrate impedance and therefore the build-up time of the substrate voltage under the circuit, helps shield the circuit from electrical interference, helps drain accumulated charge from certain layers of the IC, and helps improve impedance matching for circuits within the well by preventing substrate potential non-uniformity between circuits.

Notably, embodiments of the present invention, particularly the "trickle current" method described below, help address the large cumulative charge effects, including the floating body effect, of SOI substrates (particularly SOI substrates having trap rich layers).

The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.

Drawings

Fig. 1 is a block diagram of a typical prior art transceiver, such as of the type that may be used in a cellular telephone.

Fig. 2 is a block diagram of a prior art bias voltage generating circuit.

Fig. 3 is a block diagram illustrating a typical prior art SOI IC structure for a single FET.

Fig. 4 is a block diagram illustrating an improved prior art SOI IC structure for a single FET.

FIG. 5A is a graph of V for the FET when in standby mode_DSSchematic illustration of a stabilized first embodiment of the invention.

FIG. 5B is a schematic diagram for generating V for the circuit of FIG. 5A_LOADA schematic diagram of a circuit of (1).

Fig. 5C is a schematic diagram of the circuit of fig. 5A configured in an active (non-standby) mode.

Fig. 5D is a schematic diagram of the circuit of fig. 5A configured in a standby mode.

FIG. 6A is a graph of V for the FET when in standby mode_GSSchematic illustration of a second embodiment of the invention stabilized.

Fig. 6B is a schematic diagram of the circuit of fig. 6A but configured in a standby mode.

FIG. 7A is a schematic diagram of a third embodiment of the present invention providing a trickle current state for a PFET when in a standby mode.

FIG. 7B is a schematic diagram of a fourth embodiment of the present invention providing a trickle current state for the NFET when in standby mode.

FIG. 7C is a schematic diagram of a fifth embodiment of the present invention utilizing a fixed current source to provide a trickle current state for the NFETs when in standby mode.

FIG. 7D is a schematic diagram of a fourth embodiment of the present invention providing a trickle current state for the PFET when in standby mode.

FIG. 8 is a circuit for providing a reference current V to a bias generator circuit such as that of FIG. 2_BGSchematic diagram of current mirror circuit of/R.

Fig. 9A is a schematic diagram of a current mirror circuit based on the PFET circuit of fig. 7A.

Fig. 9B is a schematic diagram of a current mirror circuit based on the NFET circuit of fig. 7B.

Fig. 10 is a schematic diagram of a current mirror circuit with matched drain characteristics based on the PFET circuit of fig. 7A.

Fig. 11 is a schematic diagram of a bias circuit based on the NFET circuit of fig. 7B used in conjunction with a variable bias source follower circuit.

Fig. 12 is a schematic diagram of a bias circuit based on the NFET circuit of fig. 7C used in conjunction with a current mirror having a variable current source.

Fig. 13 is a block diagram illustrating an SOI IC structure with a trap rich layer, a BOX insulator layer, and substrate contacts for a single FET.

Fig. 14 is a top view of an area of a programmed IC that includes twelve example circuits (e.g., current mirrors for bias circuits of a power amplifier).

FIG. 15 is a top view of a region of a programmed IC including twelve example circuits surrounded by a plurality of S-contacts.

Fig. 16 is a process flow diagram illustrating a first method for eliminating or reducing variations in accumulated charge in an integrated circuit that is susceptible to accumulated charge and that is fabricated on a silicon-on-insulator (SOI) substrate.

Fig. 17 is a process flow diagram illustrating a second method for eliminating or reducing variation in accumulated charge in an integrated circuit fabricated on an SOI substrate as part of the integrated circuit susceptible to accumulated charge.

Fig. 18 is a process flow diagram illustrating a third method for eliminating or reducing variations in accumulated charge in an integrated circuit that is susceptible to accumulated charge and that is fabricated on an SOI substrate.

Fig. 19 is a process flow diagram illustrating a fourth method for eliminating or reducing variation in accumulated charge in an integrated circuit fabricated on an SOI substrate as part of the integrated circuit susceptible to accumulated charge.

Fig. 20 is a process flow diagram illustrating a fifth method for eliminating or reducing variations in accumulated charge in an integrated circuit that is susceptible to accumulated charge and that is fabricated on an SOI substrate.

Fig. 21 is a process flow diagram illustrating a sixth method for eliminating or reducing variation in accumulated charge in an integrated circuit fabricated on an SOI substrate as part of the integrated circuit susceptible to accumulated charge.

Fig. 22 is a process flow diagram illustrating a seventh method for eliminating or reducing variation in accumulated charge in an integrated circuit fabricated on an SOI substrate as part of the integrated circuit susceptible to accumulated charge.

FIG. 23 is a process flow diagram illustrating an eighth method for eliminating or reducing variation in accumulated charge in an integrated circuit fabricated on a silicon-on-insulator (SOI) substrate as part of the integrated circuit susceptible to accumulated charge.

FIG. 24 is a process flow diagram 2400 illustrating a ninth method for eliminating or reducing variation in accumulated charge in an integrated circuit that is susceptible to accumulated charge and that is fabricated on a silicon-on-insulator (SOI) substrate that is part of the integrated circuit.

Like reference numbers and designations in the various drawings indicate like elements.

Detailed Description

The present invention includes several types of Radio Frequency (RF) Integrated Circuits (ICs) that avoid or mitigate the generation of accumulated charge in silicon-on-insulator (SOI) substrates, particularly those having trap rich layers, by avoiding having at least some Field Effect Transistors (FETs) within the circuit in a fully off state. By keeping the standby operating condition of such critical FETs at or as close to the active state as possible, the accumulated charge is stabilized at a nearly constant level. Important insights into the function of such FETs are the following: the smaller the voltage changes at certain nodes of FETs within an SOI IC, the more stable the charge that may accumulate due to circuit activity in the active layer of the IC.

In particular applications, using one or more embodiments of the present invention reduces standby power consumption of FETs while achieving very fast sleep-to-active transition times (e.g., <1 μ S) and very stable gain shortly after becoming active (e.g., <0.05dB gain stability in <30 μ S).

Notably, embodiments of the present invention, and particularly the "trickle current" approach described below, help address the large cumulative charge effects, including the floating body effect, of SOI substrates (particularly SOI substrates having trap rich layers).

Fixed V_DSDetailed description of the preferred embodiments

FIG. 5A is a graph of V for the FET when in standby mode_DSSchematic illustration of a stabilized first embodiment of the invention. Shown coupled at a supply voltage V_DDAnd a P-type FET M1 between the controlled path switch S1. The gate of M1 is coupled to a bias voltage V through a controlled gate switch S2_BIASOr standby voltage V_SB(which may be V)_DD). As an example, FET M1 may be a component of a power amplifier bias circuit.

The pass switch S1 may be switched to connect M1 to a load or "dummy" load V_LOAD。V_LOADMay be provided by a voltage supply approximately equal to the voltage present on the drain of M1 during active mode operation. FIG. 5B is a schematic diagram for generating V for the circuit of FIG. 5A_LOADA schematic diagram of a circuit of (1). In this example, V_LOADGenerated by a simple resistive divider circuit comprising a series coupling at V_DDResistors R1 and R2 from circuit ground. V_LOADIs dependent on V_DDAnd the ratio of R1 to R2. Other circuits may be coupled between M1 and V_DDAnd/or between M1 and a load. The NFET version of the circuit of fig. 5A would look similar, but "upside down": s1, load and V_LOADWill be connected at V_DDAnd M1, wherein the source of the NFET version of M1 is coupled to circuit ground; the gate of M1 will be at V_BIASAnd circuit ground, and the drain of M1 will be under load and V through S1_LOADTo switch between.

As should be apparent to one of ordinary skill in the art, S1 and S2 may each be implemented as FETs coupled in a conventional manner to function as Single Pole Double Throw (SPDT) switches. The difference between M1 and S1/S2 is that M1 is typically modulated by an applied input signal (not shown) and essentially behaves as a variable resistor, while S1 and S2 have two binary states, connecting the common terminal to either the first node or the second node (in fig. 5A, S1 and S2 are drawn in an intermediate position, but both are typically binary).

Fig. 5C is a schematic diagram of the circuit of fig. 5A configured in an active (non-standby) mode. In this configuration, the state of S1 is set to couple M1 to the load, and the state of S2 is set to couple the gate of M1 to V_BIAS. Thus, all current to the gate of M1 and through M1 (i.e., source-drain current I)_DS) Normal flow, and M1 is in active conduction mode.

Fig. 5D is a schematic diagram of the circuit of fig. 5A configured in a standby mode. In this configuration, the state of S1 is set to couple M1 to V_LOADAnd the state of S2 is set toThe gate of M1 is coupled to V_SBIn which V is_SBIs set to a value that turns all current off. For example, by mixing V_SB＝V_DDGate source voltage V of M1 applied to gate of M1_GSBecomes 0V, turning M1 off. Due to V_LOADApproximately equal to the voltage present on the drain of M1 during active mode operation, thus V across M1_DSSubstantially the same as during active (non-standby) mode, thereby reducing operating point relative to V_DSA change in (c). V due to M1_DSRemains substantially unchanged upon transition from active mode to standby mode, so little or no additional charge may accumulate that would adversely affect the switching characteristics of M1. Therefore, by switching S1 and S2 back to the configuration shown in fig. 5C, M1 can be quickly returned to active mode.

Control signals (not shown) for switches S1 and S2 may be provided, for example, from microprocessor 142 or from a dedicated power control circuit or external circuit (e.g., where M1 is part of a power amplifier IC that does not include all of the circuitry for a complete transceiver).

Although fig. 5A, 5C, and 5D depict P-type FETs, the same principles apply to N-type FETs: in standby mode, the FET is turned off while maintaining substantially the same V as during active mode_DSThereby eliminating or reducing the variation in the accumulated charge.

In summary, this aspect of the invention includes an integrated circuit susceptible to accumulated charge and fabricated on an SOI substrate (particularly an SOI substrate having a trap rich layer) that includes at least one FET having V_DSIs characterized and configured such that in standby mode, the FET is turned off while maintaining substantially the same V as during active mode_DSThereby eliminating or reducing variations in accumulated charge in or near the SOI substrate and/or any trap rich layer and/or elsewhere in the FET (e.g., at the gate, drain or source of the FET).

This aspect of the invention also includes circuitry fabricated on an SOI substrate (particularly an SOI substrate having a trap rich layer) as an integrated circuit susceptible to accumulated chargeThe circuit comprising: at least one FET having a drain, a source, a gate, V_DSCharacteristics and a signal path between drain and source through the FET; a first switch coupled to the gate of the FET, the first switch configured to switchably couple the gate to one of a bias voltage or a standby voltage source; and a second switch coupled to the signal path of the FET, the second switch configured to switchably couple the signal path to one of a load or a pseudo-load voltage source; wherein, in the active mode, the first switch couples the gate of the FET to a bias voltage and the second switch couples the signal path of the FET to the load; and wherein in the standby mode the first switch couples the gate of the FET to a standby voltage source and the second switch couples the signal path of the FET to a pseudo-load voltage source, thereby maintaining substantially the same VDS characteristics as during the active mode and thereby eliminating or reducing variations in accumulated charge in or near the SOI substrate and/or any trap rich layer and/or elsewhere in the FET (e.g., at the gate, drain or source of the FET).

Fixed V_GSDetailed description of the preferred embodiments

FIG. 6A is a graph of V for the FET when in standby mode_GSSchematic illustration of a second embodiment of the invention stabilized. Shown coupled at a supply voltage V_DDAnd a P-type FET M1 coupled to the controlled path switch S1, the controlled path switch S1 being coupled to the load. The gate of M1 is coupled to a bias voltage V_BIAS. S1 may be implemented as a FET coupled in a conventional manner to function as a Single Pole Single Throw (SPST) switch. Thus, S1 has two binary states, namely a closed state (as shown in fig. 6A) and an open state (as shown in fig. 6B). As an example, FET M1 may be a component of a bias circuit for a power amplifier. In addition, other circuits may be coupled between M1 and V_DDAnd/or between M1 and a load. The NFET version of the circuit of fig. 6A would look similar, but "upside down": s1 and the load will be at V_DDAnd the drain of M1, wherein the source of the NFET version of M1 is coupled to circuit ground, and the gate of M1 is connected to V_BIASAnd the drain of M1 is coupled to the load through S1.

In the figureIn 6A, M1 is configured in an active (non-standby) mode. In this configuration, the state of S1 is set to closed, coupling M1 to the load. Thus, all current to the gate of M1 and through M1 (i.e., source-drain current I)_DS) Normal flow, and M1 is in active conduction mode.

Fig. 6B is a schematic diagram of the circuit of fig. 6A but configured in a standby mode. In this configuration, the state of S1 is set to off, and thus current cannot flow to the load through M1. More specifically, V of M1_DSIs 0V, and V of M1_GSUnchanged, thus reducing the operating point with respect to V_GSA change in (c). V due to M1_GSRemains substantially unchanged upon transition from active mode to standby mode, so little or no additional charge may accumulate that would adversely affect the switching characteristics of M1. Therefore, by switching S1 back to the configuration shown in fig. 6A, it is possible to quickly return M1 to the active mode.

Also, a control signal (not shown) for switch S1 may be provided, for example, from microprocessor 142 or from a dedicated power control circuit or an external circuit. Although fig. 6A and 6B depict P-type FETs, the same principles apply to N-type FETs: in standby mode, the current (I) through the FET is interrupted_DS) While maintaining substantially the same V as during active mode_GSThereby eliminating or reducing the variation in the accumulated charge.

In summary, this aspect of the invention includes an integrated circuit susceptible to accumulated charge and fabricated on an SOI substrate (particularly an SOI substrate having a trap rich layer) that includes at least one FET having V_GSIs characterized and configured such that in a standby mode, the current flowing through the FET is interrupted while maintaining substantially the same V as during an active mode_GSThereby eliminating or reducing variations in accumulated charge in or near the SOI substrate and/or any trap rich layer and/or elsewhere in the FET (e.g., at the gate, drain or source of the FET).

This aspect of the invention also includes circuitry fabricated on an SOI substrate, particularly an SOI substrate having a trap rich layerAs part of an integrated circuit susceptible to accumulated charge, the circuit comprising: at least one FET having a drain, a source, a gate, V_GSCharacteristics and a signal path between drain and source through the FET; and a switch coupled to the signal path of the FET, the switch configured to switchably couple the signal path to a load or interrupt current flowing through the signal path of the FET; wherein in the active mode, the switch couples the signal path of the FET to the load; and wherein in the standby mode the switch interrupts current flowing through the signal path of the FET so as to maintain substantially the same V as during the active mode_GSAnd thereby eliminate or reduce variations in accumulated charge in or near the SOI substrate and/or any trap rich layer and/or elsewhere in the FET (e.g., at the gate, drain, or source of the FET).

Trickle current embodiment

In the first and second embodiments described above, V_GSOr V_DSIs set to substantially 0V to turn off or interrupt the flow of current through the FET. However, to meet a particular power consumption specification, the FETs need not be completely turned off or have all current flow interrupted; alternatively, the FET may be switched so that V_GSAnd V_DSBoth remain in a very low current state ("trickle current" state) close to their respective active mode operating voltages. Essentially, the trickle current embodiment of the present invention enables sufficient current to pass through the FET to maintain an active conduction channel in the FET. In contrast, if the FET is turned off completely, the conduction channel is no longer formed and needs to be re-formed when the FET exits the standby mode. In practice, the trickle current mode FET circuit simply passes enough current to keep the conduction channel active and keep the FET ready to turn on at any time when transitioning from standby mode to active mode. For example, for many applications, a trickle current in standby mode with 1/1000 less than the active mode current is sufficient, while in other applications a trickle current in standby mode with 1/10000 or even 1/100000 less than the active mode current is sufficientThe current may be more useful. As another example, in one power amplifier bias circuit, the active mode current consumption is about 10mA, while the standby mode current consumption is in the range of about 0.1 μ A to 1 μ A.

FIG. 7A is a schematic diagram of a third embodiment of the present invention providing a trickle current state for a PFET when in a standby mode. Shown coupled at a supply voltage V_DDAnd a P-type FET M1 between the controlled path switch S1. The gate of M1 is coupled to a bias voltage V_BIAS. Also coupled to the gate of the M1 PFET is a feedback voltage 702 from the drain of M1, the feedback voltage 702 providing V to M1_GSControl of (2); in some applications, the feedback voltage 702 may be controlled or modified by an optional circuit 704 (an example of one such control circuit is shown in fig. 8). Note that feedback voltage 702 may be V_BIAS(ii) a That is, no external bias voltage is applied to the gate of M1, only feedback voltage 702 is applied to the gate of M1. As in the example above, FET M1 may be a component of the power amplifier bias circuit.

The pass switch S1 may be switched to connect M1 to the active mode resistor R_L(which may be provided by a load) or standby mode resistance R_SB. As in the above embodiments, S1 may be implemented as a FET coupled in a conventional manner to function as a Single Pole Double Throw (SPDT) switch, such that S1 has two binary states, connecting the common terminal to either the first node or the second node (S1 is drawn in an intermediate position, but is typically binary). Other circuits may be coupled between M1 and V_DDAnd/or M1 and R_LIn the meantime.

When the circuit of FIG. 7A is configured in an active (non-standby) mode, the state of S1 is set to couple M1 to R_L. Thus, current through M1 flows normally, and M1 is in active conduction mode. When the circuit of FIG. 7A is configured in standby mode, the state of S1 is set to couple M1 to R_SB. The current through M1 is primarily controlled by the gate of M1. When R is_LIs changed to R_SBWhen, I_DSMust be changed by passing V of M1 through by means of feedback voltage 702_GSWhile changing at the same time and automatically (if V_BIASIs a fixed value, and R_LIs switched to R_SBThen V is_DSWill approach 0V because of normal mode I_DS×R_SBMuch greater than V_DD)。

R_SBShould be substantially greater than R_LTo prevent the current through M1 from dropping to a trickle. In general, R_SBShould have some resistance value (taking into account PVT effects) that is repeatable so that the trickle current is higher than the leakage current of M1. For example, in some embodiments, R_SBAnd R_LIn the resistance ratio of about 100: 1 to about 1000: 1, in the above range. Therefore, since in R_SBA small amount of trickle current continues to flow through M1 when switched into the circuit, so M1 is still active, but the power and speed levels are greatly reduced.

FIG. 7B is a schematic diagram of a fourth embodiment of the present invention providing a trickle current state for the NFET when in standby mode. An N-type FET M1 is shown coupled between circuit ground and a controlled path switch S1(S1 is drawn in an intermediate position, but is typically binary). The gate of M1 is coupled to a bias voltage V_BIAS. Also coupled to the gate of the M1 NFET is a feedback voltage 702 from the drain of M1, feedback voltage 702 providing V to M1_GSControl of (2); in some applications, the feedback voltage 702 may be controlled or modified by optional circuitry 704. Note again that V_BIASMay be provided entirely by the feedback voltage 702.

The pass switch S1 can be switched to pass through the active resistor R_L(which may be provided by a load) or standby mode resistance R_SBConnecting M1 to V_DD. When the circuit of FIG. 7B is configured in an active (non-standby) mode, the state of S1 is set to couple M1 to R_L. Thus, current through M1 flows normally, and M1 is in active conduction mode. When the circuit of fig. 7B is configured in the standby mode, the state of S1 is set to pass through R_SBCoupling M1 to V_DDAnd V of M1_GSAccording to the feedback voltage 702, so as to reduce I_DS. Likewise, R_SBShould be much greater than R_LTo prevent current flow through M1The motion drops to a trickle. Therefore, since in R_SBA small amount of current continues to flow through M1 when switched into the circuit, so M1 is still active, but the power and speed levels are greatly reduced.

FIG. 7C is a schematic diagram of a fifth embodiment of the present invention utilizing a fixed current source to provide a trickle current state for the NFETs when in standby mode. An N-type FET M1 is shown coupled between circuit ground and a controlled path switch S1(S1 is drawn in an intermediate position, but is typically binary). The gate of M1 is coupled to a bias voltage V_BIAS. Also coupled to the gate of the M1 NFET is a feedback voltage 702 from the drain of M1, feedback voltage 702 providing V to M1_GSControl of (2); also, in some applications, the feedback voltage 702 may be controlled or modified by the optional circuit 704, and V_BIASMay be provided entirely by the feedback voltage 702.

The pass switch S1 may be switched to connect M1 to the active mode current source I_NOr a lower power standby mode current source I_SB. When the circuit of FIG. 7C is configured in an active (non-standby) mode, the state of S1 is set to couple M1 to I_N. Thus, current through M1 flows normally, and M1 is in active conduction mode. When the circuit of FIG. 7C is configured in standby mode, the state of S1 is set to couple M1 to I_SBAnd V of M1_GSAccording to the feedback voltage 702, so as to reduce I_DS. Should be aligned with_SBThe current provided is adjusted so that only a trickle current flows through M1. Therefore, since in I_SBA small amount of current continues to flow through M1 when switched into the circuit, so M1 is still active, but the power and speed levels are greatly reduced.

FIG. 7D is a schematic diagram of a fourth embodiment of the present invention providing a trickle current state for the PFET when in standby mode. Shown coupled at a supply voltage V_DDAnd a P-type FET M1 between the controlled path switch S1. The gate of M1 is selectively coupled to a bias voltage V through a switch S2_BIASOr trickle voltage V_TRICKLE. As in the example above, FET M1 may be a component of the power amplifier bias circuit. Examples shown in FIGS. 7B and 7CEmbodiments may be similarly configured with switch S2 to select bias voltage V_BIASOr trickle voltage V_TRICKLERather than using the feedback voltage 702.

The pass switch S1 may be switched to connect M1 to the active mode resistor R_L(which may be provided by a load) or standby mode resistance R_SB. Switch S2 will be controlled to be simultaneously at V_BIAS(for active mode) or V_TRICKLE(for standby mode). As in the above embodiments, S1 and S2 may each be implemented as FETs coupled in a conventional manner to function as Single Pole Double Throw (SPDT) switches such that they have two binary states, connecting a common terminal to either a first node or a second node (both S1 and S2 are drawn in an intermediate position, but are typically binary). Other circuits may be coupled between M1 and V_DDAnd/or M1 and R_LIn the meantime.

When the circuit of FIG. 7D is configured in an active (non-standby) mode, the state of S1 is set to couple M1 to R_LAnd the state of S2 is set to V_BIASCoupled to the gate of M1. Thus, current through M1 flows normally, and M1 is in active conduction mode. When the circuit of FIG. 7D is configured in standby mode, the state of S1 is set to couple M1 to R_SBAnd the state of S2 is set to V_TRICKLEGate coupled to M1, thereby reducing I_DS。

A common feature of the embodiments of fig. 7A-7D is that switch S1 selectively couples the source-drain signal path to the active mode normal current flow path or current sink (e.g., by R_SB) Preventing or (e.g. by I)_SB) One of the regulated standby mode trickle current paths.

In all the trickle current embodiments described above, V of M1 is used_DSAnd V_GSThe variation is small when going from active mode to standby mode, so little additional charge can accumulate in or near the SOI substrate and/or any trap rich layer and/or elsewhere in the FET (e.g., at the gate, drain or source of the FET). Thus, M1 may be quickly returned by switching S1 back to the active mode configurationTo an active mode. In all cases, a control signal (not shown) for switch S1 may be provided, for example, from microprocessor 142 or from a dedicated power control circuit or an external circuit.

Regardless of the specific implementation, the same principle applies to all trickle current implementations: in standby mode, the current (I) through the FET is substantially limited_DS) While making V_GSAnd V_DSBoth are maintained close to their respective active mode operating voltages, thereby reducing variations in accumulated charge.

In summary, this aspect of the invention includes an integrated circuit susceptible to accumulated charge and fabricated on an SOI substrate (particularly an SOI substrate having a trap rich layer) that includes at least one FET having a drain, a source, a gate, a V_DSCharacteristic, V_GSCharacteristics and a signal path between the drain and the source through the FET and configured such that in a standby mode, the FET is switched to have V of the FET with respect to current flowing through the signal path_GSCharacteristic sum V_DSCharacteristics both remain close to V_GSCharacteristic sum V_DSThe characteristic respective active mode operates a very low current state of voltage, reducing the variation of accumulated charge in or near the SOI substrate and/or any trap rich layer and/or elsewhere in the FET (e.g., at the gate, drain or source of the FET).

This aspect of the invention also includes a circuit fabricated on an SOI substrate (particularly an SOI substrate having a trap rich layer) as part of an integrated circuit susceptible to accumulated charge, the circuit comprising: at least one FET having a drain, a source, a gate, V_DSCharacteristic, V_GSCharacteristics and a signal path between drain and source through the FET; and a switch coupled to the signal path of the FET, the switch configured to switchably couple the signal path to either the normal current flow path or the trickle current path; wherein in the active mode, the switch couples the signal path of the FET to the normal current flow path; and wherein in the standby mode the switch couples the signal path of the FETTo trickle current path, so that V of FET_GSCharacteristic sum V_DSCharacteristics both close to V_GSCharacteristic sum V_DSThe characteristic respective active mode operating voltage, thereby reducing variations in accumulated charge in or near the SOI substrate and/or any trap rich layer and/or elsewhere in the FET (e.g., at the gate, drain or source of the FET). The trickle current path may have a high resistance relative to the normal current flow path and/or the trickle current path may include a regulated current source relative to the normal current flow path that causes only a trickle current to flow through the FET.

Trickle current circuit application

The trickle current circuits shown in fig. 7A-7D may be used in a variety of applications. For example, FIG. 8 is a circuit for providing a reference current V to a bias generator circuit 206 such as that of FIG. 2_BGSchematic diagram of current mirror circuit 800 of/R. Based on the PFET circuit of FIG. 7A, the differential amplifier 802 is based on a reference voltage V_BGAnd the voltage V at the drain of M1_SENSEA comparison is made to provide a substantially constant bias voltage V to M1 and a current mirror PFET M2_BIAS. In both cases, the load (resistance) is switched to a much higher value in the standby mode.

As in FIG. 2, the reference voltage V_BGMay be, for example, a bandgap voltage reference. As in the example of FIG. 7A, the current mirror circuit 800 may be in an active mode (where M1 is coupled to resistor R through switch S1) and a trickle current standby mode (where M1 is coupled to a higher resistor R through switch S1)_SB) To switch between.

Fig. 9A is a schematic diagram of a current mirror circuit 900 based on the PFET circuit of fig. 7A. Fig. 9B is a schematic diagram of a current mirror circuit 920 based on the NFET circuit of fig. 7B. In each configuration, FET M1 is self-biased to act as a diode and provides a bias voltage to current mirror FET M2, current mirror FET M2 typically being designed to be significantly larger than M1 by a scaling factor M; for example, in some embodiments, m is 100. In each configuration, FET M3 represents an example load or replica device for a power amplifier. The available voltage is provided at a respective node N, which may be coupled to other circuitry downstream (not shown); for example, each configuration may be useful for biasing a power amplifier FET stack or a Low Noise Amplifier (LNA) from node N.

In either case, in the low power standby mode (i.e., R)_SBSwitched into the circuit by S1), the normal bias current is replaced by a trickle current. When switching between active and standby modes, the trickle current reduces the voltage change on the gate of each FET (e.g., as compared to pulling the gate to ground). The trickle current also reduces the voltage change on the FET drain if the normal mode load remains connected. Note that more current mirror stages can be connected to M2, and at R_SBWhen switched into the circuit through S1, each current mirror stage will remain in the preferred low power state.

Fig. 10 is a schematic diagram of a current mirror circuit with matched drain characteristics. In this example, the two SPDT switches S1a and S1b are configured to switch in unison (but in opposite directions for the depicted circuit; both switches are depicted in an intermediate position, but are typically binary). The PFET M1 is self-biased to act as a diode. In normal mode, the drain of PFET M1 is coupled to R0 through S1a, and the drain of current mirror PFET M2 is coupled to the load through S1 b. In standby mode, the drain of M1 is coupled to R through S1a_SBAnd the drain of M2 is coupled to R through S1b_SBThus shorting the drains together.

Shorting the drains together in the low power standby mode limits additional SOI substrate coupling effects because the two FETs act as one device, meaning that their terminal voltages match and the current densities are the same (ignoring possible device mismatches). Upon returning to active mode, the FET will have a value for V_DSAnd V_GSThis helps active mode current accuracy and settling time (note that the active mode configuration may include a feedback loop, not shown).

In some configurations, separate resistances (e.g., R) corresponding to switches S1a and S1b may be used_SBa and R_SBb) To better match the trickle current of other circuits (not shown) coupled to M1 and/or M2Flow requirements. As one of ordinary skill in the art will appreciate, the concept shown in fig. 10 may be extended to NFETs.

Fig. 11 is a schematic diagram of a bias circuit based on the NFET circuit of fig. 7B used in conjunction with a variable bias source follower circuit. NFET M1 is self-biased to act as a diode and provides a bias voltage to NFET MN1, NFET MN1 is typically designed to be significantly larger than M1 by a scaling factor M. In this example, the drain of MN1 is controlled by a source follower NFETMN coupled to the load_SFAnd (5) controlling. NFET MN shown in isolation_SFAs indicated by the dashed line connected to the load, a practical implementation may use a stack of two or more source follower stages instead of one source follower.

The function of switch S1 is as described above with respect to FIG. 7B, to switch R in the active mode₀Coupled to M1, and will have a much higher resistance R in standby mode_SBCoupled to M1. In the illustrated example, as an additional feature, to the MN_SFThe bias voltage of the gate may also be changed in mode by controlling switch S2 in concert with switch S1 (both switches are drawn in a neutral position, but are typically binary). In active mode, switch S2 will be set to MN_SFProvides the normal bias voltage Vb 1. However, in standby mode, switch S2 will be set to MN_SFProvides a lower bias voltage Vb 2. The lower bias voltage Vb2 will keep the drain voltage of MN1 closer to the voltage at which it will be in active mode (e.g., just above V for NFET MN 1)_TH) Thereby reducing the variation in the accumulated charge.

Fig. 12 is a schematic diagram of a bias circuit based on the NFET circuit of fig. 7C used in conjunction with a current mirror having a variable current source. Standby mode current source I_SB1And an active mode current source I_N1May be coupled to diode D through switch S1 a. Similarly, a standby mode current source I_SB2And an active mode current source I_N2May be coupled to the sources of PFETS M1 and M3 through switch S1 b. The switches S1a, S1b are drawn in an intermediate position, but are typically binary, and both are configured to switch in unison. PFET M1 is composed of twoDiode D is biased and coupled in series to NFET M2, NFET M2 is self-biased to act as a diode and provide a bias voltage to NFET M4. PFET M3 is self-biased to act as a diode and is coupled in series to NFET M4. The output Δ V between M3 and M4 may be used to bias a power amplifier circuit (not shown).

In the normal mode, switches S1a and S1b will source the normal current I_N1And I_N2Coupled in the circuit. In standby mode, switches S1a and S1b couple a low power current source I_SΒ1And I_SB2Coupled in the circuit. In the illustrated configuration, to prevent large voltage changes (i.e., large Δ V) on the amplifier input when switching between standby and active modes, the input to diode D remains biased with a trickle current in the low power standby mode, rather than discharging to ground.