阅读说明：本技术 一种goa电路布局 (GOA circuit layout ) 是由 张留旗 韩佰祥 于 2019-09-12 设计创作，主要内容包括：一种GOA电路布局,包括多个驱动薄膜晶体管单元,每一所述驱动薄膜晶体管单元具有走线侧与电容侧,任两相邻所述驱动薄膜晶体管单元间隔设置且彼此串联；及多个第一电容区域,每一所述第一电容区域设置于两相邻所述驱动薄膜晶体管单元的电容侧之间。本发明提供的GOA电路布局,增大了驱动薄膜晶体管的散热面积,更有利于散热,另一方面由于第一电容区域的充分利用,而基本没有增大布局尺寸。(A GOA circuit layout comprises a plurality of driving thin film transistor units, wherein each driving thin film transistor unit is provided with a wiring side and a capacitance side, and any two adjacent driving thin film transistor units are arranged at intervals and are connected in series with each other; and each first capacitor area is arranged between the capacitor sides of two adjacent driving thin film transistor units. The GOA circuit layout increases the heat dissipation area of the driving thin film transistor, is more favorable for heat dissipation, and basically does not increase the layout size due to the full utilization of the first capacitor region.)

1. A GOA circuit arrangement, comprising:

the driving thin film transistor units are provided with wiring sides and capacitance sides, and any two adjacent driving thin film transistor units are arranged at intervals and are connected in series; and

each first capacitor area is arranged between the capacitor sides of two adjacent driving thin film transistor units.

2. The GOA circuit layout of claim 1, wherein the driving tft cells are rectangular, the routing side is located at a short side of the rectangle, and the capacitance side is located at a long side of the rectangle.

3. The GOA circuit layout of claim 2, further comprising a series line disposed on a routing side of the driving tft units, wherein any two adjacent driving tft units are connected in series via the series line.

4. The GOA circuit layout of claim 3, wherein each of the driving tft units has two channels, a length direction of the channels is parallel to the capacitor side, and a distance between two adjacent first capacitor regions is greater than or equal to a width of the two channels.

5. The GOA circuit layout of claim 4, wherein a width of the channel is adjustable.

6. The GOA circuit layout of claim 4, wherein each of the driving TFT units further has a source side and a drain side on the trace side.

7. The layout of claim 6, further comprising a plurality of second capacitor regions, each of the second capacitor regions being disposed on the source side and connected to the first capacitor region through the source side.

8. The GOA circuit layout of claim 3, wherein the driving tft cells connected in series comprise the driving tft cells at two ends of the series structure and the driving tft cell in the middle of the series structure, and the driving tft cells at two ends of the series structure have a channel with a length direction parallel to the capacitor side.

9. The GOA circuit arrangement of claim 8, wherein each of the driving tft cells further has a source side and a drain side on the trace side.

10. The GOA circuit layout of claim 9, further comprising a plurality of second capacitor regions, each disposed on the drain side and connected to the first capacitor region through the drain side.

Technical Field

The invention relates to the technical field of display, in particular to a GOA circuit layout.

Background

With the continuous development of display technology, people have increasingly strong requirements on high contrast, high resolution, narrow frame and thinness. In order to achieve the purpose, currently, a gate Driver on array (GOA) driving circuit is widely used as a gate driving circuit in mainstream products of display technologies such as liquid crystal display and organic light emitting diode display, but because the GOA circuit adopts an alternating current driving mode, part of thin film transistors fail due to a serious self-heating effect, and particularly, the driving thin film transistors with larger sizes are used.

Fig. 1 is a schematic diagram illustrating a layout relationship between a driving tft and a capacitor in a conventional GOA circuit layout, in which a capacitor region 2 is independently disposed below or at the right of the driving tft region 1 (not shown), which results in a problem of insufficient heat dissipation effect.

Disclosure of Invention

The invention provides a GOA circuit layout, which aims to solve the technical problem that the existing GOA circuit layout is insufficient in heat dissipation effect.

In order to solve the above problems, the technical scheme provided by the invention is as follows:

the invention provides a GOA circuit layout, which comprises a plurality of driving thin film transistor units, wherein each driving thin film transistor unit is provided with a wiring side and a capacitance side, and any two adjacent driving thin film transistor units are arranged at intervals and are connected in series; and each first capacitor area is arranged between the capacitor sides of two adjacent driving thin film transistor units.

In at least one embodiment of the present invention, the driving thin film transistor unit has a rectangular shape, the routing side is located at a short side of the rectangular shape, and the capacitance side is located at a long side of the rectangular shape.

In at least one embodiment of the present invention, the GOA circuit layout further includes a serial line disposed on a routing side of the driving thin film transistor units, and any two adjacent driving thin film transistor units are connected in series with each other through the serial line.

In at least one embodiment of the present invention, each of the driving tft units has two channels, a length direction of the channel is parallel to the capacitor side, and a distance between two adjacent first capacitor regions is greater than or equal to a width of the two channels.

In at least one embodiment of the present invention, the width of the channel is adjustable.

In at least one embodiment of the present invention, each of the driving thin film transistor units further has a source side and a drain side on the wiring side.

In at least one embodiment of the present invention, the GOA circuit layout further includes a plurality of second capacitor regions, each of the second capacitor regions is disposed on the source side and connected to the first capacitor region through the source side.

In at least one embodiment of the present invention, the driving thin film transistor units connected in series include the driving thin film transistor units located at both ends of the series structure and the driving thin film transistor unit located in the middle of the series structure, and the driving thin film transistor units located at both ends of the series structure have a channel, and a length direction of the channel is parallel to the capacitor side.

In at least one embodiment of the present invention, the GOA circuit layout further includes a plurality of second capacitor regions, each of the second capacitor regions is disposed on the drain side and connected to the first capacitor region through the drain side.

The invention has the beneficial effects that: the GOA circuit layout increases the heat dissipation area of the driving thin film transistor, is more favorable for heat dissipation, and basically does not increase the layout size due to the full utilization of the first capacitor region.

Drawings

In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic diagram of a layout relationship between a driving TFT and a capacitor in a conventional GOA circuit layout;

FIG. 2 is a schematic diagram illustrating a layout relationship between a driving TFT and a capacitor in a GOA circuit layout according to the present invention;

FIG. 3 is a schematic layout diagram of a GOA circuit according to a first embodiment of the present invention;

fig. 4 is a schematic layout diagram of a GOA circuit according to a second embodiment of the present invention.

Detailed Description

The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.

The invention aims at the technical problem of insufficient heat dissipation effect of the conventional GOA circuit layout, and the embodiment can solve the defect.

Fig. 2 is a schematic diagram showing a layout relationship between a driving thin film transistor and a capacitor in a GOA circuit layout according to the present invention, in which the driving thin film transistor region 1 is divided into a series structure of a plurality of driving thin film transistor units 1 ', and a capacitor region 2 is inserted between each smaller driving thin film transistor unit 1', so that the driving thin film transistor region 1 can be divided reasonably by the capacitor region 2, the heat dissipation area of the driving thin film transistor region 1 is increased, and the heat dissipation function is realized.

Fig. 3 is a schematic diagram of a GOA circuit layout according to a first embodiment of the present invention, where the GOA circuit layout includes: a plurality of driving thin film transistor units 1 ', each driving thin film transistor unit 1 ' having a wiring side 11 and a capacitance side 12, any two adjacent driving thin film transistor units 1 ' being arranged at intervals and connected in series with each other; and a plurality of capacitor regions 2, each capacitor region 2 is disposed between two capacitor sides 12 of two adjacent driving thin film transistor units 1'. The driving thin film transistor unit 1' is rectangular, the wiring side 11 is located on the short side of the rectangle, and the capacitor side 12 is located on the long side of the rectangle. The GOA circuit layout further includes a series line 3 disposed on the routing side 11 of the driving thin film transistor unit 1 ', and any two adjacent driving thin film transistor units 1' are connected in series with each other through the series line 3.

As shown in fig. 3, the first capacitor region 2 is inserted between the driving tft units 1 ', the driving tft units 1' are divided into five parts, and each driving tft unit 1 'is connected in series with each other through the series lines 3 on the wiring side 11, so that on one hand, the heat dissipation area of the driving tft units 1' is increased, which is more beneficial to heat dissipation, and on the other hand, the layout size is not substantially increased due to the full utilization of the first capacitor region 2.

In this embodiment, each of the driving tft units 1' has two channels 13, the length direction of the channels 13 is parallel to the capacitor side 12, and the distance between two adjacent first capacitor regions 2 is greater than or equal to the width of two channels 13. The width of the channel 13 is adjustable. Each of the driving tft units 1' further has a source side 14 and a drain side 15, which are located on the routing side 11. The GOA circuit layout further includes a plurality of second capacitor regions 4, each second capacitor region 4 disposed on the source side 14 and connected to the first capacitor region 2 through the source side 14.

Fig. 4 is a schematic layout diagram of a GOA circuit according to a second embodiment of the present invention, where as shown in the figure, the first capacitor region 2 is inserted between the driving tft units 1 ', so as to divide the driving tft units 1' into six parts, and each of the driving tft units 1 'is connected in series with each other through the series lines 3 on the routing side 11, on one hand, the heat dissipation area of the driving tft units 1' is increased, which is more favorable for heat dissipation, and on the other hand, the layout size is not substantially increased due to the full utilization of the first capacitor region 2.

In this embodiment, unlike the first embodiment, the driving thin film transistor cells 1 'connected in series with each other include the driving thin film transistor cells 1' located at both ends of the series structure and the driving thin film transistor cell 1 'located in the middle of the series structure, and the driving thin film transistor cells 1' located at both ends of the series structure have a channel 13 whose length direction is parallel to the capacitor side. Each of the driving tft units 1' further has a source side 14 and a drain side 15, which are located on the routing side 11. The GOA circuit layout further comprises a plurality of second capacitive regions 4, each second capacitive region 4 being disposed on the drain side 15 and being connected to the first capacitive region 2 via the drain side 15.

Since the drain voltage is higher and the voltage difference between the gate and the drain is smaller than that between the gate and the source in the operation process of the thin film transistor, the resistance between the gate and the drain is larger and the heat is more easily generated, so the invention provides the above two embodiments.

Has the advantages that: the GOA circuit layout increases the heat dissipation area of the driving thin film transistor, is more beneficial to heat dissipation, and on the other hand, the layout size is not increased basically due to the full utilization of the first capacitor region 2.

In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.