阅读说明：本技术 台面结构PNP型肖特基集电区SOI SiGe HBT结构及其制备方法 (Mesa-structured PNP type Schottky collector region SOI SiGe HBT structure and preparation method thereof ) 是由 李迈克 于 2019-11-11 设计创作，主要内容包括：本发明提供一种台面结构PNP型肖特基集电区SOI SiGe HBT结构,包括单晶硅衬底及层叠于单晶硅衬底表面的埋氧层构成的SOI衬底,埋氧层表面顺序层叠有P型重掺杂单晶硅层、金属硅化物薄层、N型重掺杂Si<Sub>1-x</Sub>Ge<Sub>x</Sub>基区层、P型掺杂单晶硅发射区帽层和P型重掺杂多晶硅发射区层,P型重掺杂多晶硅发射区层至P型掺杂单晶硅发射区帽层刻蚀形成有发射区和基区电极接触台面,P型重掺杂多晶硅发射区层至金属硅化物薄层刻蚀形成有集电区电极接触台面,台面结构表面覆盖有氧化薄膜层,电极窗口形成有对应金属电极,基区电极接触区域里沉积有N型重掺杂Si<Sub>1-</Sub><Sub>y</Sub>Ge<Sub>y</Sub>。本发明还提供一种前述结构制备方法。本申请能提高器件截止频率和增益并减小基区渡越时间且能与常规硅基工艺兼容。(The invention provides a mesa structure PNP type Schottky collector region SOI SiGe HBT structure, which comprises a monocrystalline silicon substrate and an SOI substrate consisting of an oxygen burying layer laminated on the surface of the monocrystalline silicon substrate, wherein a P type heavily doped monocrystalline silicon layer, a metal silicide thin layer and an N type heavily doped Si layer are sequentially laminated on the surface of the oxygen burying layer 1‑x Ge x The base region layer, the P-type doped monocrystalline silicon emitter region cap layer and the P-type heavily doped polycrystalline silicon emitter region layer from the P-type heavily doped polycrystalline silicon emitter region layer to the P-type doped polycrystalline silicon emitter region layerA monocrystalline silicon emitter region cap layer is etched to form an emitter region and a base region electrode contact mesa, a collector region electrode contact mesa is etched from a P-type heavily doped polycrystalline silicon emitter region layer to a metal silicide thin layer, an oxide film layer covers the surface of the mesa structure, a corresponding metal electrode is formed on an electrode window, and N-type heavily doped Si is deposited in a base region electrode contact region 1‑ y Ge y . The invention also provides a preparation method of the structure. The method can improve the cut-off frequency and the gain of the device, reduce the base region transit time and be compatible with the conventional silicon-based process.)

1. The PNP Schottky collector region SOI SiGe HBT structure with the mesa structure is characterized by comprising an SOI substrate, wherein the SOI substrate comprises a monocrystalline silicon substrate and a buried oxide layer laminated on the surface of the monocrystalline silicon substrate, a P-type heavily doped monocrystalline silicon layer is formed on the surface of the buried oxide layer, the thickness of the P-type heavily doped monocrystalline silicon layer is far greater than the depletion thickness of the layer caused by the bias of the SOI substrate, a metal silicide thin layer is formed on the surface of the P-type heavily doped monocrystalline silicon layer, and an N-type heavily doped Si thin layer is formed on the surface of the metal silicide thin layer_1-xGe_xBase region layer of said N-type heavily doped Si_1-xGe_xA P-type doped monocrystalline silicon emitter region cap layer is formed on the surface of the base region layer, a P-type heavily doped polycrystalline silicon emitter region layer is formed on the surface of the P-type doped monocrystalline silicon emitter region cap layer, emitter region electrodes and left and right lateral side group region electrode contact table tops are formed by etching the P-type heavily doped polycrystalline silicon emitter region layer to the P-type doped monocrystalline silicon emitter region cap layer, left and right lateral collector region electrode contact table tops are formed by etching the P-type heavily doped polycrystalline silicon emitter region layer to the metal silicide thin layer, an oxidized thin film layer covers the whole surface of the table top structure, corresponding electrode contact windows are formed by etching the oxidized thin film layers corresponding to the positions of the base region, the collector region and the middle emitter region, and corresponding electrode contact windows are formed by etching_1-xGe_xA base electrode contact area is formed by etching the base layer, a corresponding metal electrode is formed on the electrode contact window, and N-type heavily doped Si is deposited in the base electrode contact area_1-yGe_yAnd 0 is<y<x<1。

2. The mesa structure of claim 1 having a PNP schottky collector SOI SiGe HBT structure wherein the buried oxide layer has a thickness of 0.5 μm.

3. The mesa structure of claim 1 having a PNP schottky collector SOI SiGe HBT structure wherein the thin layer of metal silicide is a 5nm thick CoSi₂。

4. The mesa structure of claim 1 having a PNP schottky collector SOI SiGe HBT structure wherein the N-type heavily doped Si is doped with Si_1-xGe_xThe thickness of the base region layer is 20-30 nm.

5. The mesa structure of the PNP schottky collector SOI SiGe HBT structure of claim 1 wherein the thickness of the cap layer of the P-doped monocrystalline silicon emitter is 10nm and the thickness of the layer of the P-doped polycrystalline silicon emitter is 0.5 μm.

6. The mesa structure of claim 1 having a PNP schottky collector SOI SiGe HBT structure, wherein the oxide film layer is 100nm thick SiO₂And oxidizing the layer.

7. A method for fabricating a mesa structure PNP schottky junction SOI SiGe HBT structure according to any one of claims 1 to 6, comprising the steps of:

s1, preparing an SOI substrate including a monocrystalline silicon substrate and a buried oxide layer laminated on the surface of the monocrystalline silicon substrate, depositing a heavily doped P-type monocrystalline silicon layer with a doping concentration of 2 × 10 on the surface of the buried oxide layer¹⁹cm^-3And the thickness of the P-type heavily doped monocrystalline silicon layer is far greater than the depletion thickness of the layer caused by the bias of the SOI substrate, and then the surface of the P-type heavily doped monocrystalline silicon layer is cleaned and chemically and mechanically polished;

s2, growing a layer of metal with the thickness of 5nm on the surface of the P-type heavily doped monocrystalline silicon layer by utilizing physical vapor deposition, and then carrying out rapid thermal annealing treatment to oxidize the metal and the monocrystalline silicon surface below so as to form a metal silicide thin layer as a collector region;

s3, depositing a layer of thin N-type heavily doped Si on the surface of the metal silicide thin layer by using molecular beam epitaxy technology_1-xGe_xBase region layer with doping concentration of 1 × 10¹⁹cm^-3(ii) a Then heavily doping Si in N type_1-xGe_xA P-type doped monocrystalline silicon emitter cap layer is continuously grown on the surface of the base region layer, and the doping concentration is 5 multiplied by 10¹⁷cm^-3(ii) a Finally, depositing a P-type heavily doped polysilicon emitter region layer with a typical thickness of 0.5 μm on the surface of the cap layer of the P-type doped monocrystalline silicon emitter region, wherein the doping concentration is 2 × 10¹⁹cm^-3；

S4, etching an emitter and a base region from the P-type heavily doped polysilicon emitter region layer to the P-type doped monocrystalline silicon emitter region cap layer according to the emitter width preset by the device, and etching a collector region from the P-type heavily doped polycrystalline silicon emitter region layer to the metal silicide thin layer to form a mesa structure;

s5, forming an oxide film layer covering the whole mesa by dry oxygen oxidation on the etched mesa structure, determining electrode contact windows of the emitter, the base and the collector, and etching off the oxide film layer of the emitter region, the base region and the collector region window and the N-type heavily doped Si below the base region window_1-xGe_xBase region, then Si etched away_1-xGe_xN-type heavily doped Si deposited in the region_1-yGe_yAnd 0 is<y<x<And 1, finally depositing metal on electrode contact windows of the emitter region, the base region and the collector region to be used as an emitter electrode, a base electrode and a collector electrode, and finishing the manufacture of the device.

8. The method of claim 7, wherein in step S2, the metal grown on the surface of the heavily doped monocrystalline silicon layer is Co, and the Co is oxidized with the surface of the underlying monocrystalline silicon to form CoSi₂。

9. The method for fabricating the mesa structure PNP Schottky collector region SOI SiGe HBT structure as claimed in claim 7, wherein in the step S5, the oxide film layer is SiO with a thickness of 10nm₂And oxidizing the layer.

10. The method for fabricating the mesa structure PNP schottky junction SOI SiGe HBT structure of claim 7, wherein in step S5, y is 0.1 and x is 0.3.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a mesa-structured PNP-type Schottky collector region SOISIGe HBT structure and a preparation method thereof.

Background

The market at present has increasingly strong demands for high-performance devices such as high-speed devices, high-frequency devices, low-cost devices and the like. But because of the limitation of the physical properties of the Si material, the performances of high speed, high frequency and the like of the conventional Si device are difficult to improve; although III-V compound semiconductor devices (e.g., GaAs, InP, etc.) are much better than Si devices in high-speed high-frequency performance, they have disadvantages of incompatibility with Si device processes, high cost, etc. A silicon-germanium heterojunction bipolar transistor (SiGe HBT) is a silicon-based bipolar junction transistor (SiBJT) with a small amount of Ge added to the base region. The base region is made of SiGe material, so that the device performance is remarkably improved, and the SiGe HBT becomes a standard bipolar transistor in high-speed application. The key indicator of UHF semiconductor devices is the cut-off frequency (f)_T) The SiGe HBT developed on the basis of a mature silicon process utilizes the advantages of 'energy band engineering', and fundamentally solves the contradiction between the improvement of the amplification factor and the improvement of the frequency characteristic. Due to the complete compatibility with the mature silicon process and the development and maturation of the process technologies such as Molecular Beam Epitaxy (MBE) and Chemical Vapor Deposition (CVD), the SiGe HBT has its unique advantages and is widely used in high-performance microwave rf devices and circuits.

The SOI (Silicon On Insulator) technology is an ideal platform for developing novel devices and integrated circuits with low power consumption, radiation resistance, high temperature resistance and the like, and simultaneously, the application prospect of the CMOS process is expanded. In the SOI substrate technology, the SiGe HBT device can play roles of reducing the parasitic capacitance effect, reducing the power consumption of the device, avoiding the latch-up effect, and the like by using the insulator substrate in the SOI substrate. In recent years, SiGe HBTs based on SOI substrate technology are becoming one of the hot spots for research in the microelectronics field.

In addition, it is noted that under the same doping condition, since minority carrier (hole) mobility of the PNP base region is lower than that of the NPN-type SiGe HBT, gain of the PNP-type device is smaller, and base transit time is longer, so the NPN-type is mostly used for the current SiGe HBT. On the other hand, under the condition of the same base material, the mobility of a base multi-electron (electron) of the PNP type transistor is higher, so that the square resistance of the PNP type intrinsic base is far smaller than that of the NPN type intrinsic base, the charge-discharge time of the emitter junction capacitor can be shortened, and the switching conversion speed of the device can be improved. Therefore, the PNP SiGe HBT has obvious advantages and application potential in a switching circuit as long as the base transit time is further reduced and the current gain of the device is improved. Furthermore, if the collector junction of a conventional SiGe HBT is replaced by a schottky junction, the operating speed of the device can be further improved, since the schottky contact has two significant main advantages: (1) the collector resistance is 0; (2) because there is no collector junction space charge region, the collector junction transit time can be 0, as can the charge storage time, which can further increase the cutoff frequency.

The inventors of the present invention have studied and found that, compared to the above-mentioned two advantages (1) and (2), more importantly, for the carriers transported at the collector junction, the use of the schottky collector junction can effectively avoid the transition process of the carriers from the base region of the narrow bandgap to the collector region of the wide bandgap, because of the discontinuous amount Δ E of the collector junction valence band of the conventional PNP-type Si/SiGe/Si HBT structure_VGreatly, it is not favorable for further improvement of device performance due to the combined action of the speed overshoot effect of the carrier, and the hole concentration accumulated at the collector junction is increased by exp (q Δ E)_Vand/kT) (q is the electron electric quantity, k is the boltzmann constant, and T is the temperature), the collector current is reduced, the collector junction transit time is increased, and the above adverse factors can be effectively avoided if a schottky barrier is used.

The inventor of the present invention has further found through research that, in order to achieve the purpose of reducing the transit time of the PNP-type SiGe HBT base region, the advantages of "strain engineering" can be combined with the conventional means of reducing the thickness of the SiGe base region. At present, "strain engineering" is mainly applied in the process of high-speed MOSFET, especially in the strain process under 90 nm, uniaxial strain is a commonly used technique. Therefore, if the uniaxial strain technology can be introduced into the PNP type SiGe HBT, stress is applied to the base region of the PNP type SiGe HBT through simple process steps, the longitudinal mobility of base region minority carriers (holes) is reduced, the base region transit time is reduced, and the cut-off frequency of the device is improved; meanwhile, the compatibility with the conventional silicon-based CMOS process is also considered, and the method is convenient for large-scale commercial manufacturing.

Disclosure of Invention

The invention provides a mesa structure PNP type Schottky collector SOI SiGe HBT structure, aiming at the technical problems that the existing PNP type SiGe HBT device has smaller gain, longer base region transit time and lower switching speed and cut-off frequency of a device because the mobility of a hole is smaller than that of an electron.

In order to solve the technical problems, the invention adopts the following technical scheme:

the mesa structure PNP type Schottky collector region SOI SiGe HBT structure comprises an SOI substrate, wherein the SOI substrate comprises a monocrystalline silicon substrate and a buried oxide layer stacked on the surface of the monocrystalline silicon substrate, a P type heavily doped monocrystalline silicon layer is formed on the surface of the buried oxide layer, the thickness of the P type heavily doped monocrystalline silicon layer is far greater than the depletion thickness of the layer caused by the bias of the SOI substrate, a metal silicide thin layer is formed on the surface of the P type heavily doped monocrystalline silicon layer, and an N type heavily doped Si thin layer is formed on the surface of the metal silicide thin layer_1-xGe_xBase region layer of said N-type heavily doped Si_1-xGe_xA P-type doped monocrystalline silicon emitter region cap layer is formed on the surface of the base region layer, a P-type heavily doped polycrystalline silicon emitter region layer is formed on the surface of the P-type doped monocrystalline silicon emitter region cap layer, emitter region electrodes and left and right lateral side group region electrode contact table tops are formed by etching the P-type heavily doped polycrystalline silicon emitter region layer to the P-type doped monocrystalline silicon emitter region cap layer, left and right lateral collector region electrode contact table tops are formed by etching the P-type heavily doped polycrystalline silicon emitter region layer to the metal silicide thin layer, an oxidized thin film layer covers the whole surface of the table top structure, corresponding electrode contact windows are formed by etching the oxidized thin film layers corresponding to the positions of the base region, the collector region and the middle emitter region, and corresponding electrode contact windows are formed by etching_1-xGe_xA base electrode contact area is formed by etching the base layer, a corresponding metal electrode is formed on the electrode contact window, and N-type heavily doped Si is deposited in the base electrode contact area_1-yGe_yAnd 0 is<y<x<1。

Further, the thickness of the oxygen buried layer is 0.5 μm.

Further, the thin metal silicide layer is CoSi with the thickness of 5nm₂。

Further, the N-type heavily doped Si_1-xGe_xThe thickness of the base region layer is 20-30 nm.

Further, the thickness of the cap layer of the P-type doped monocrystalline silicon emitter region is 10nm, and the thickness of the P-type heavily doped polycrystalline silicon emitter region layer is 0.5 μm.

Further, the oxide film layer is SiO with the thickness of 100nm₂And oxidizing the layer.

The invention also provides a preparation method of the mesa structure PNP type Schottky collector region SOI SiGe HBT structure, which comprises the following steps:

s1, preparing an SOI substrate including a monocrystalline silicon substrate and a buried oxide layer laminated on the surface of the monocrystalline silicon substrate, depositing a heavily doped P-type monocrystalline silicon layer with a doping concentration of 2 × 10 on the surface of the buried oxide layer¹⁹cm^-3And the thickness of the P-type heavily doped monocrystalline silicon layer is far greater than the depletion thickness of the layer caused by the bias of the SOI substrate, and then the surface of the P-type heavily doped monocrystalline silicon layer is cleaned and chemically and mechanically polished;

s2, growing a layer of metal with the thickness of 5nm on the surface of the P-type heavily doped monocrystalline silicon layer by utilizing physical vapor deposition, and then carrying out rapid thermal annealing treatment to oxidize the metal and the monocrystalline silicon surface below so as to form a metal silicide thin layer as a collector region;

s3, depositing a layer of thin N-type heavily doped Si on the surface of the metal silicide thin layer by using molecular beam epitaxy technology_1-xGe_xBase region layer with doping concentration of 1 × 10¹⁹cm^-3(ii) a Then heavily doping Si in N type_1-xGe_xA P-type doped monocrystalline silicon emitter cap layer is continuously grown on the surface of the base region layer, and the doping concentration is 5 multiplied by 10¹⁷cm^-3(ii) a Finally, depositing a P-type heavily doped polysilicon emitter region layer with a typical thickness of 0.5 μm on the surface of the cap layer of the P-type doped monocrystalline silicon emitter region, wherein the doping concentration is 2 × 10¹⁹cm^-3；

S4, etching an emitter and a base region from the P-type heavily doped polysilicon emitter region layer to the P-type doped monocrystalline silicon emitter region cap layer according to the emitter width preset by the device, and etching a collector region from the P-type heavily doped polycrystalline silicon emitter region layer to the metal silicide thin layer to form a mesa structure;

s5, forming an oxide film layer covering the whole mesa by dry oxygen oxidation on the etched mesa structure, determining electrode contact windows of the emitter, the base and the collector, and etching off the oxide film layer of the emitter region, the base region and the collector region window and the N-type heavily doped Si below the base region window_1-xGe_xBase region, then Si etched away_1-xGe_xN-type heavily doped Si deposited in the region_1-yGe_yAnd 0 is<y<x<And 1, finally depositing metal on electrode contact windows of the emitter region, the base region and the collector region to be used as an emitter electrode, a base electrode and a collector electrode, and finishing the manufacture of the device.

Further, in step S2, the metal grown on the surface of the heavily doped P-type monocrystalline silicon layer is Co, and Co is oxidized with the underlying monocrystalline silicon surface to form CoSi₂。

Further, in the step S5, the oxide film layer is SiO with a thickness of 10nm₂And oxidizing the layer.

Further, in the step S5, y is 0.1, and x is 0.3.

Compared with the prior art, the mesa structure PNP type Schottky collector region SOI SiGe HBT structure and the preparation method thereof provided by the invention have the following technical advantages:

1. using extremely thin layers of metal silicides, e.g. CoSi₂Forming Si/CoSi with the single crystal silicon of the base region₂The Schottky contact ensures excellent contact interface characteristics, can improve the switching speed and cut-off frequency of a device switch, is compatible with the conventional silicon-based process, and has relatively simple process;

2. in Si_1-xGe_xSi is formed on both sides of the base region in the form of "embedded" growth_1-yGe_yBase region ofA contact region (note: forming a base metal electrode in contact with a metal) satisfying 0<y<x<Under the condition of 1, the Ge component content values of x and y can be flexibly designed, so that the design freedom of the device is improved; si on both sides due to lattice mismatch_1-yGe_yFor intermediate Si_1-xGe_xThe base region generates a transverse uniaxial tensile stress effect and a longitudinal compressive stress effect, wherein the longitudinal compressive stress can effectively improve the mobility of minority carriers (holes) in the base region and the base region transit time, and the cut-off frequency of the device is improved;

3. the method uses a very thin P-type doped monocrystalline silicon emitter region cap layer and a very thick P-type heavily-doped polycrystalline silicon emitter region layer as a combined emitter electrode structure, and simultaneously, according to the principle of elasticity, the transverse uniaxial tensile stress of a base region can be conducted into the upper P-type doped monocrystalline silicon emitter region cap layer to form a strain silicon layer with compressive strain, namely the P-type doped monocrystalline silicon emitter region cap layer is simultaneously subjected to tensile strain Si_1-xGe_xUniaxial compressive strain silicon is formed under the influence of the base region, and according to the physical theory of the semiconductor device, the compressive strain silicon cap layer can further improve the injection efficiency of an emitter and the cut-off frequency and the direct-current amplification factor (gain) of the device;

4. the mature SOI substrate technology is introduced, the effects of reducing the parasitic capacitance effect, reducing the power consumption of the device, avoiding the latch-up effect and the like are further achieved, the overall performance of the device is improved, the process integration with the existing small-size low-power SOI CMOS device is facilitated, and the technical route of the equal-scale reduction of the device is met.

Drawings

Fig. 1 is a schematic structural diagram of a PNP schottky collector SOI SiGe HBT with a mesa structure provided by the present invention.

Fig. 2a to 2e are schematic cross-sectional structures of the respective process stages in the method for fabricating the mesa PNP schottky collector SOI SiGe HBT structure according to the present invention.

Detailed Description

In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further explained below by combining the specific drawings.

In the description of the present invention, it is to be understood that the terms "longitudinal", "radial", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. In the description of the present invention, "a plurality" means two or more unless otherwise specified.

Referring to fig. 1, the present invention provides a mesa PNP schottky collector SOI SiGe HBT structure, which comprises an SOI substrate including a single-crystal silicon substrate and a buried oxide layer (BOX) stacked on the surface of the single-crystal silicon substrate, wherein the buried oxide layer is formed by oxidizing SiO formed on the surface of the single-crystal silicon substrate₂An oxide layer, wherein a P-type heavily doped monocrystalline silicon layer is formed on the surface of the buried oxide layer, the thickness of the P-type heavily doped monocrystalline silicon layer is far greater than the depletion thickness of the layer caused by the bias of the SOI substrate, so that the resistance of a collector region is not influenced by the width of the depletion region and becomes too large, a metal silicide thin layer is formed on the surface of the P-type heavily doped monocrystalline silicon layer, the P-type heavily doped monocrystalline silicon layer and the metal silicide thin layer thereon form a combined collector structure, and an N-type heavily doped Si layer is formed on the surface of the metal silicide thin layer_1-xGe_xBase region layer of said N-type heavily doped Si_1-xGe_xA P-type doped monocrystalline silicon emitter region cap layer is formed on the surface of the base region layer, a P-type heavily doped polycrystalline silicon emitter region layer is formed on the surface of the P-type doped monocrystalline silicon emitter region cap layer, the P-type heavily doped polycrystalline silicon emitter region layer and the P-type doped monocrystalline silicon emitter region cap layer form a combined emitter electrode structure, emitter region electrodes and left and right lateral group region electrode contact table surfaces are formed by etching from the P-type heavily doped polycrystalline silicon emitter region layer to the P-type doped monocrystalline silicon emitter region cap layer,the method comprises the steps that an electrode contact table top of an emitter region is located in the middle, base region electrode contact table tops are located on the left side and the right side of the electrode contact table top of the emitter region, left and right collector region electrode contact table tops are formed by etching from a P-type heavily doped polycrystalline silicon emitter region layer to a metal silicide thin layer, the left collector region electrode contact table top is located on the left side of the left base region electrode contact table top, the right collector region electrode contact table top is located on the right side of the right base region electrode contact table top, an oxide film layer covers the whole surface of the table top structure, corresponding electrode contact windows, namely a base region window, a collector region window and an emitter region window, are formed by etching the oxide film layers corresponding to the base region, the collector region and the middle emitter_1-xGe_xA base electrode contact area is formed by etching the base layer, corresponding metal electrodes, namely a base electrode, a collector electrode and an emitter electrode, are formed on the electrode contact window, and N-type heavily doped Si is deposited in the base electrode contact area_1-yGe_yI.e. heavily doped with Si in the N-type_1-xGe_xN-type heavily doped Si on the left and right sides of the base region layer_1-yGe_yWherein x and y are the molar content of Ge (germanium), and 0<y<x<1。

As a specific example, the thickness of the buried oxide layer should not be too thick, with a typical thickness value of 0.5 μm.

As a specific embodiment, the interface morphology and the interface state at the interface of the metal silicide thin layer and the monocrystalline silicon contact in the P-type heavily doped monocrystalline silicon layer below the metal silicide thin layer have great influence on the device characteristics, and according to the conventional silicon process at present, a layer of extremely thin CoSi (usually less than 10 nanometers) with good interface morphology and interface state can be grown on the monocrystalline silicon material₂And CoSi₂The barrier height in contact with the P-type single crystal silicon is about 0.7eV, so CoSi₂Is the preferred metal silicide material for forming the collector schottky barrier. As a preferred embodiment, the thin layer of metal silicide CoSi₂Is 5 nm.

As a specific embodiment, the N type heavily doped Si_1-xGe_xThe thickness of the base layer is 20-30nm, thereby ensuring that the SiGe layer of the base region does not relaxUnder the condition of the square resistance, the thickness of the base region is reduced as much as possible, so that the base region transit time is reduced, but the base region transit time cannot be reduced too much, and if the base region transit time is reduced too much, the square resistance of the base region is increased.

As a specific embodiment, the thickness of the cap layer of the P-type doped monocrystalline silicon emitter region is 10nm, and the thickness of the P-type heavily doped polycrystalline silicon emitter region layer is 0.5 μm, so that a combined emitter structure is formed by polycrystalline silicon and monocrystalline silicon, at the moment, the monocrystalline silicon layer is strained, and the energy band structure of the monocrystalline silicon layer is changed by stress, so that the direct current gain of the device can be improved through physical analysis.

As a specific embodiment, the oxide film layer is SiO with the thickness of 100nm₂And oxidizing the layer, thereby being beneficial to reducing the self-heating effect of the device.

The invention also provides a preparation method of the mesa structure PNP type Schottky collector region SOI SiGe HBT structure, which comprises the following steps:

s1, preparing an SOI substrate which comprises a monocrystalline silicon substrate and a buried oxide layer (BOX) laminated on the surface of the monocrystalline silicon substrate, wherein the buried oxide layer is formed by oxidizing SiO formed on the surface of the monocrystalline silicon substrate₂Oxide layer of said SiO₂The thickness of the oxide layer should not be too thick, and the typical thickness value is 0.5 μm, then a P-type heavily doped monocrystalline silicon layer with the doping concentration of 2 x 10 is deposited on the surface of the buried oxide layer¹⁹cm^-3And the thickness of the P-type heavily doped monocrystalline silicon layer is much greater than the depletion thickness t of the layer caused by the bias of the SOI substrate, and then cleaning and Chemical Mechanical Polishing (CMP) are performed on the surface of the P-type heavily doped monocrystalline silicon layer to form a metal silicide on the P-type heavily doped monocrystalline silicon layer, as shown in fig. 2 a. Specifically, under the action of the substrate voltage, the SOI substrate forms a back-to-back MOS capacitor structure, and the depletion thickness t can be solved by the following unitary quadratic equation according to the physics of the semiconductor device:

wherein q is the electron electric quantity, N_SiIs a P-type heavily doped single crystal on the buried oxide layerDoping concentration of silicon layer, epsilon_SiAnd ε_OXDielectric constants, t, of the monocrystalline silicon and the buried oxide layer in the P-type heavily doped monocrystalline silicon layer_OXThickness of buried oxide layer, V_S、V_CAnd V_MSThe difference values of the substrate voltage, the collector voltage and the work function of the monocrystalline silicon regions at two sides of the buried oxide layer are respectively.

S2, growing a layer of metal with the thickness of 5nm on the surface of the P-type heavily doped monocrystalline silicon layer by using the existing Physical Vapor Deposition (PVD) method, and then carrying out Rapid Thermal Annealing (RTA) treatment to oxidize the metal and the monocrystalline silicon surface below to form a metal silicide thin layer as a collector region; as a specific implementation mode, the metal grown on the surface of the P-type heavily doped monocrystalline silicon layer is Co, and the Co is oxidized with the surface of the lower monocrystalline silicon layer to form CoSi₂Mixing CoSi₂As a collector region, please refer to fig. 2b for a specific structure.

S3, forming a thin layer of metal silicide such as CoSi₂The surface is deposited with a thin layer of heavily N-doped Si (e.g. 30nm thick) by Molecular Beam Epitaxy (MBE) technique_1-xGe_xBase region layer with doping concentration of 1 × 10¹⁹cm^-3The Ge component x is preferably 0.3; then heavily doping Si in N type_1-xGe_xA layer of P-type doped monocrystalline silicon emitter cap layer with the thickness of 10nm is continuously grown on the surface of the base region layer, and the doping concentration is 5 multiplied by 10¹⁷cm^-3(ii) a Finally, depositing a P-type heavily doped polysilicon emitter region layer with a typical thickness of 0.5 μm on the surface of the cap layer of the P-type doped monocrystalline silicon emitter region, wherein the doping concentration is 2 × 10¹⁹cm^-3The detailed structure is shown in fig. 2 c.

S4, etching an emitter and a base region from the P-type heavily doped polysilicon emitter region layer to the P-type doped polysilicon emitter region cap layer according to the emitter width preset by the device, where the emitter region is located in the middle of the base region, that is, the base region is located at both sides of the emitter region, and then etching a collector region from the P-type heavily doped polysilicon emitter region layer to the metal silicide thin layer to form a mesa structure, where the collector region is located at both sides of the base region, and the specific structure is shown in fig. 2 d.

S5, passing dry oxygen on the whole etched mesa structureOxidizing to form a thin oxide layer covering the entire mesa, e.g., a 10nm thick layer of SiO₂Determining electrode contact windows of an emitter, a base and a collector by using an oxide layer as an oxide film layer, etching off the oxide film layer of the emitter region, the base region and the collector region windows, and etching off the N-type heavily doped Si below the base region windows_1-xGe_xBase region, then Si etched away_1-xGe_xN-type heavily doped Si deposited in the region_{1- y}Ge_yDoping concentration of 2X 10¹⁹cm^-3And 0 is<y<x<And 1, finally, depositing metal on electrode contact windows of the emitter region, the base region and the collector region to be used as an emitter electrode, a base electrode and a collector, and finishing the manufacturing of the device, wherein the specific structure is shown in fig. 2 e.

As a specific example, in the step S5, Si is heavily doped N-type_1-yGe_yThe value of the medium Ge component y is 0.1, and N type heavily doped Si_1-xGe_xThe value of the Ge component x in the base region layer is 0.3.

Compared with the prior art, the mesa structure PNP type Schottky collector region SOI SiGe HBT structure and the preparation method thereof provided by the invention have the following technical advantages:

1. using extremely thin layers of metal silicides, e.g. CoSi₂Forming Si/CoSi with the single crystal silicon of the base region₂The Schottky contact ensures excellent contact interface characteristics, can improve the switching speed and cut-off frequency of a device switch, is compatible with the conventional silicon-based process, and has relatively simple process;

2. in Si_1-xGe_xSi is formed on both sides of the base region in the form of "embedded" growth_1-yGe_yThe base contact region (note: forming a base metal electrode in contact with a metal) of (1) satisfies 0<y<x<Under the condition of 1, the Ge component content values of x and y can be flexibly designed, so that the design freedom of the device is improved; si on both sides due to lattice mismatch_1-yGe_yFor intermediate Si_1-xGe_xThe base region generates a transverse uniaxial tensile stress effect and a longitudinal compressive stress effect, wherein the longitudinal compressive stress can effectively improve the baseThe mobility of the minority carrier (hole) in the region and the base region transit time improve the cut-off frequency of the device;

3. the method uses a very thin P-type doped monocrystalline silicon emitter region cap layer and a very thick P-type heavily-doped polycrystalline silicon emitter region layer as a combined emitter electrode structure, and simultaneously, according to the principle of elasticity, the transverse uniaxial tensile stress of a base region can be conducted into the upper P-type doped monocrystalline silicon emitter region cap layer to form a strain silicon layer with compressive strain, namely the P-type doped monocrystalline silicon emitter region cap layer is simultaneously subjected to tensile strain Si_1-xGe_xUniaxial compressive strain silicon is formed under the influence of the base region, and according to the physical theory of the semiconductor device, the compressive strain silicon cap layer can further improve the injection efficiency of an emitter and the cut-off frequency and the direct-current amplification factor (gain) of the device;

4. the mature SOI substrate technology is introduced, the effects of reducing the parasitic capacitance effect, reducing the power consumption of the device, avoiding the latch-up effect and the like are further achieved, the overall performance of the device is improved, the process integration with the existing small-size low-power SOI CMOS device is facilitated, and the technical route of the equal-scale reduction of the device is met.

Finally, the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all of them should be covered in the claims of the present invention.