阅读说明：本技术 增强型场效应晶体管 (Enhancement mode field effect transistor ) 是由 王元刚 冯志红 吕元杰 宋旭波 谭鑫 周幸叶 房玉龙 尹甲运 于 2019-09-20 设计创作，主要内容包括：本发明适用于半导体器件技术领域,公开了一种增强型场效应晶体管,增强型场效应晶体管自下而上依次包括衬底、沟道层、势垒层、钝化层和至少一层预设结构；预设结构自下而上依次包括绝缘介质层和场板；沟道层上分列有源电极和漏电极,势垒层上设有栅电极,钝化层位于源电极与栅电极之间以及栅电极与漏电极之间,绝缘介质层覆盖栅电极；在源电极和漏电极之间的沟道层中存在无载流子区和载流子区,在栅电极正下方以外的沟道层中存在无载流子区,且在栅电极正下方的沟道层中存在载流子区；在无载流子区的正上方具有场板。本发明提供的增强型场效应晶体管利用横向能带工程实现增强型器件,并利用场板结构能够提高击穿电压,提高器件的可靠性。(The invention is suitable for the technical field of semiconductor devices and discloses an enhanced field effect transistor which sequentially comprises a substrate, a channel layer, a barrier layer, a passivation layer and at least one layer of preset structure from bottom to top; the preset structure sequentially comprises an insulating medium layer and a field plate from bottom to top; the channel layer is provided with a source electrode and a drain electrode in a row, the barrier layer is provided with a gate electrode, the passivation layer is positioned between the source electrode and the gate electrode and between the gate electrode and the drain electrode, and the insulating medium layer covers the gate electrode; a carrier-free region and a carrier region are present in the channel layer between the source electrode and the drain electrode, a carrier-free region is present in the channel layer outside directly below the gate electrode, and a carrier region is present in the channel layer directly below the gate electrode; there is a field plate directly above the non-carrier region. The enhancement type field effect transistor provided by the invention realizes an enhancement type device by utilizing a transverse energy band engineering, and can improve the breakdown voltage and the reliability of the device by utilizing a field plate structure.)

1. An enhancement mode field effect transistor is characterized by comprising a substrate, a channel layer, a barrier layer, a passivation layer and at least one layer of preset structure from bottom to top in sequence;

the preset structure sequentially comprises an insulating medium layer and a field plate from bottom to top;

the source electrode and the drain electrode are respectively arranged on the channel layer, the barrier layer is provided with a gate electrode, the passivation layer is positioned between the source electrode and the gate electrode and between the gate electrode and the drain electrode, and the insulating medium layer covers the gate electrode;

a carrier-free region and a carrier region are present in the channel layer between the source electrode and the drain electrode, the carrier-free region is present in the channel layer other than directly below the gate electrode, and the carrier region is present in the channel layer directly below the gate electrode;

the field plate is arranged right above the non-carrier region.

2. An enhancement mode field effect transistor according to claim 1 wherein said carrier-free region is free of carriers and said carrier region has carriers;

the current carrier is body doping or two-dimensional electron gas or two-dimensional hole gas or two-dimensional material.

3. The enhancement mode field effect transistor of claim 1 wherein said field plate is entirely on said insulating dielectric layer or wherein said field plate is partially on said insulating dielectric layer forming an air bridge field plate.

4. The enhancement mode field effect transistor according to claim 1 wherein the thickness of the insulating dielectric layer is greater than or equal to 1nm and the thickness of the insulating dielectric layer is less than or equal to 10 μm.

5. The enhancement mode field effect transistor according to claim 1 wherein the thickness of the insulating dielectric layer is greater than or equal to 2nm and the thickness of the insulating dielectric layer is less than or equal to 20 nm.

6. The enhancement-mode field-effect transistor according to claim 1, wherein the number of non-carrier regions is greater than or equal to 1.

7. An enhancement mode field effect transistor according to claim 1 wherein the width of the non-carrier region is greater than or equal to 1nm and the width of the non-carrier region is less than or equal to 10 μm.

8. The enhancement mode field effect transistor of claim 1 wherein the width of the non-carrier region is greater than or equal to 50nm and the width of the non-carrier region is less than or equal to 800 nm.

9. An enhancement mode field effect transistor according to claim 1, characterized in that the number of gate electrodes is larger than or equal to 1.

10. The enhancement mode fet of any of claims 1 to 9 further comprising a gate insulating dielectric layer between the barrier layer and the passivation layer;

the gate insulating dielectric layer is arranged below at least one gate electrode.

Technical Field

The invention belongs to the technical field of semiconductor devices, and particularly relates to an enhanced field effect transistor.

Background

The field effect transistor is called field effect transistor for short, and has the advantages of high input resistance, low noise, low power consumption, large dynamic range, easy integration, no secondary breakdown phenomenon, wide safe working area and the like. One of the operating modes of the field effect transistor is the enhancement mode.

At present, an enhancement type field effect transistor is usually realized based on longitudinal energy band engineering, but the enhancement type field effect transistor realized by adopting the mode has the advantages of smaller breakdown voltage, easy damage and poorer reliability.

Disclosure of Invention

In view of this, embodiments of the present invention provide an enhancement mode field effect transistor to solve the problems of a smaller breakdown voltage, easy damage and poor reliability of the enhancement mode field effect transistor implemented in the prior art.

The embodiment of the invention provides an enhancement type field effect transistor which sequentially comprises a substrate, a channel layer, a barrier layer, a passivation layer and at least one layer of preset structure from bottom to top;

the preset structure sequentially comprises an insulating medium layer and a field plate from bottom to top;

the source electrode and the drain electrode are respectively arranged on the channel layer, the barrier layer is provided with a gate electrode, the passivation layer is positioned between the source electrode and the gate electrode and between the gate electrode and the drain electrode, and the insulating medium layer covers the gate electrode;

a carrier-free region and a carrier region are present in the channel layer between the source electrode and the drain electrode, the carrier-free region is present in the channel layer other than directly below the gate electrode, and the carrier region is present in the channel layer directly below the gate electrode;

the field plate is arranged right above the non-carrier region.

Optionally, the carrier-free region is free of carriers, the carrier region having carriers;

the current carrier is body doping or two-dimensional electron gas or two-dimensional hole gas or two-dimensional material.

Optionally, the field plate is entirely located on the insulating dielectric layer, or a part of the field plate is located on the insulating dielectric layer to form an air bridge field plate.

Optionally, the thickness of the insulating dielectric layer is greater than or equal to 1nm, and the thickness of the insulating dielectric layer is less than or equal to 10 μm.

Optionally, the thickness of the insulating dielectric layer is greater than or equal to 2nm, and the thickness of the insulating dielectric layer is less than or equal to 20 nm.

Optionally, the number of the carrier-free regions is greater than or equal to 1.

Optionally, the width of the carrier-free region is greater than or equal to 1nm, and the width of the carrier-free region is less than or equal to 10 μm.

Optionally, the width of the carrier-free region is greater than or equal to 50nm, and the width of the carrier-free region is less than or equal to 800 nm.

Optionally, the number of gate electrodes is greater than or equal to 1.

Optionally, the enhancement mode field effect transistor further comprises a gate insulating dielectric layer located between the barrier layer and the passivation layer;

the gate insulating dielectric layer is arranged below at least one gate electrode.

Compared with the prior art, the embodiment of the invention has the following beneficial effects: the enhancement mode field effect transistor provided by the embodiment of the invention sequentially comprises a substrate, a channel layer, a barrier layer, a passivation layer and at least one layer of preset structure from bottom to top; the preset structure sequentially comprises an insulating medium layer and a field plate from bottom to top; the channel layer is provided with a source electrode and a drain electrode in a row, the barrier layer is provided with a gate electrode, the passivation layer is positioned between the source electrode and the gate electrode and between the gate electrode and the drain electrode, and the insulating medium layer covers the gate electrode; a carrier-free region and a carrier region are present in the channel layer between the source electrode and the drain electrode, a carrier-free region is present in the channel layer outside directly below the gate electrode, and a carrier region is present in the channel layer directly below the gate electrode; there is a field plate directly above the non-carrier region. The enhancement type field effect transistor provided by the embodiment of the invention utilizes the transverse energy band engineering to realize an enhancement type device, and utilizes the field plate structure to improve the breakdown voltage and the reliability of the device.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

Fig. 1 is a schematic structural diagram of an enhancement mode fet according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of an enhancement mode fet according to another embodiment of the present invention;

FIG. 3 is a schematic diagram of an enhancement mode FET according to yet another embodiment of the present invention;

fig. 4 is a schematic structural diagram of an enhancement mode fet according to yet another embodiment of the present invention.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

In order to explain the technical means of the present invention, the following description will be given by way of specific examples.

Fig. 1 is a schematic structural diagram of an enhancement mode field effect transistor according to an embodiment of the present invention, and only a portion related to the embodiment of the present invention is shown for convenience of description. The enhancement mode field effect transistor provided by the embodiment of the invention is manufactured on the basis of a III-nitride material.

As shown in fig. 1, the enhancement mode field effect transistor may include, in order from bottom to top, a substrate 10, a channel layer 20, a barrier layer 30, a passivation layer 40, and at least one layer of a predetermined structure 50;

the preset structure 50 sequentially comprises an insulating medium layer 51 and a field plate 52 from bottom to top;

the channel layer 20 is provided with a source electrode 60 and a drain electrode 70 in a row, the barrier layer 30 is provided with a gate electrode 80, the passivation layer 40 is positioned between the source electrode 60 and the gate electrode 80 and between the gate electrode 80 and the drain electrode 70, and the insulating medium layer 51 covers the gate electrode 80;

there are no-carrier regions and carrier regions in the channel layer 20 between the source electrode 60 and the drain electrode 70, no-carrier regions in the channel layer 20 other than directly below the gate electrode 80, and carrier regions in the channel layer 20 directly below the gate electrode 80;

there is a field plate 52 directly above the non-carrier region.

The substrate 10 may be a compound semiconductor, Si, Ge, a two-dimensional material, an insulator, or a combination thereof. The substrate 10 may also be other realizable materials, and is not limited thereto.

The channel layer 20 may be a compound semiconductor or Si or Ge or a two-dimensional material or a combination of the above. The channel layer 20 may also be other realizable materials, and is not limited thereto.

The barrier layer 30 may be a compound semiconductor or Si or Ge or a two-dimensional material or a combination of the above. The barrier layer 30 may also be other materials that may be implemented, and is not limited thereto. The barrier layer 30 may be located between the source electrode 60 and the drain electrode 70.

In one embodiment, as shown in FIG. 1, substrate 10 isSiC; the channel layer 20 is GaN; the barrier layer 30 is In_xAl_yGa_(1-x-y)N, wherein x is more than or equal to 0 and less than or equal to 1, y is more than or equal to 0 and less than or equal to 1, and x + y is more than 0 and less than or equal to 1.

In one embodiment, as shown in FIG. 2, substrate 10 is GaAs; the channel layer 20 is GaAs; the barrier layer 30 is In_xGa_(1-x)As, where x is 0. ltoreq. x.ltoreq.1, and the barrier layer 30 includes a highly doped region of Si to provide carriers for the channel.

In one embodiment, as shown in FIG. 3, the substrate 10 is sapphire; the channel layer 20 is graphene.

In one embodiment, as shown in FIG. 4, the substrate 10 is Si; the channel layer 20 is Si or GaN.

The enhancement mode fet shown in fig. 1 comprises a predetermined structure including a first layer of insulating dielectric layer 51 and a first layer of field plate 52, wherein the field plate in fig. 1 is a source field plate; the enhancement mode field effect transistor shown in fig. 2 comprises two layers of preset structures, including a first layer of insulating dielectric layer 51, a first layer of field plate 52, a second layer of insulating dielectric layer 53 and a second layer of field plate 54, wherein the first layer of field plate in fig. 2 is a floating field plate, and the second layer of field plate is a source field plate; the enhancement mode field effect transistor shown in fig. 3 comprises a three-layer preset structure, which comprises a first layer of insulating dielectric layer 51, a first layer of field plate 52, a second layer of insulating dielectric layer 53, a second layer of field plate 54, a third layer of insulating dielectric layer 55 and a third layer of field plate 56, wherein the first layer of field plate, the second layer of field plate and the third layer of field plate in fig. 3 are all floating field plates. The preset structure 50 may be located between the source electrode 60 and the drain electrode 70.

The enhancement mode field effect transistor may further include a multilayer predetermined structure. The thickness of the insulating medium layer of each layer can be the same or different. The field plate type of each layer can be any one of a source field plate, a floating field plate and a drain field plate, and can also be a combination of the above types.

It should be noted that, in order to distinguish between different layers of insulating dielectric layers and different layers of field plates, different numbers are used for the different layers of insulating dielectric layers and the different layers of field plates, but 51, 53 and 55 are all insulating dielectric layers, and 52, 54 and 56 are all field plates.

A carrier-free region (AB region) and a carrier region (CA region and BD region) are present in the channel layer 20 between the source electrode 60 and the drain electrode 70. A carrier region exists in the channel layer 20 directly below the gate electrode 80, that is, carriers exist in the corresponding channel layer 20 directly below the gate electrode 80, and may partially or entirely exist. For example, carriers are all present in the channel layer 20 directly below the gate electrode 80 on the left in FIG. 1, i.e., a carrier region is present in the channel layer 20 directly below the gate electrode 80 on the left in FIG. 1; the portion of the channel layer 20 directly below the gate electrode 80 on the right in FIG. 1 is carrier-containing, i.e., the portion of the channel layer 20 directly below the gate electrode 80 on the right in FIG. 1 includes both a carrier region and a carrier-free region.

A carrier-free region is present in the channel layer 20 outside directly below the gate electrode 80. That is, a carrier-free region may exist in the channel layer 20 directly below the gate electrode 80, and a carrier-free region may exist in the channel layer 20 other than directly below the gate electrode 80, i.e., the FD region, the CE region, and the channel layer between the two gate electrodes 80 in fig. 1. The carrier-free region AB in fig. 1 is located partially in the channel layer 20 directly below the gate electrode 80 and partially in the channel layer 20 beyond the region directly below the gate electrode 80. In addition, there is a metal field plate over the non-carrier region.

It should be noted that the dashed lines in fig. 1 and 2 are drawn only for determining the positions of E and F, and do not exist actually.

As can be seen from the above description, the enhancement mode fet provided in the embodiment of the present invention utilizes lateral energy band engineering to implement an enhancement mode device, and includes a field plate structure, and has a metal field plate above a non-carrier region, so as to improve breakdown voltage and reliability of the device. In addition, the potential barrier height of the no-carrier area has small influence on the threshold voltage of the device, the threshold controllability can be enhanced, the method can be used for a digital circuit, the speed is improved, the energy consumption is reduced, the device is started and shut off only by controlling the charging and discharging of a small amount of electrons in the no-carrier area, the switching speed is high, when the device is started, the influence of the width of the no-carrier area on the threshold voltage is large, and the controllability of an ultra-wide area of the threshold voltage can.

In one embodiment of the invention, the carrier-free region is free of carriers, the carrier region having carriers;

the carrier is bulk doping or two-dimensional electron gas or two-dimensional hole gas or two-dimensional material.

In the embodiment of the present invention, no channel carrier 21 exists in the carrier-free region, and channel carrier 21 exists in the carrier region. The channel carriers 21 may be electrons or holes. The channel carriers 21 are either bulk doped or two-dimensional electron gas or two-dimensional hole gas or two-dimensional material. For example, the carrier 21 in fig. 1 and 2 is a two-dimensional electron gas; the carriers 21 in fig. 3 are two-dimensional materials; carrier 21 in fig. 4 is N-type body doped.

In one embodiment of the invention, the field plate is entirely located on the insulating dielectric layer, or the field plate is partially located on the insulating dielectric layer to form an air bridge field plate.

Illustratively, the field plates in fig. 1, 2 and 3 are all located on the insulating dielectric layer, and may be source field plates, drain field plates or floating field plates. The field plate 52 in fig. 4 is partially on the insulating dielectric layer 51, and the field plate 52 is an air bridge field plate.

Wherein the field plate may be located between the source electrode 60 and the drain electrode 70.

In one embodiment of the present invention, the thickness of the insulating dielectric layer is greater than or equal to 1nm, and the thickness of the insulating dielectric layer is less than or equal to 10 μm.

In one embodiment of the present invention, the thickness of the insulating dielectric layer is greater than or equal to 2nm, and the thickness of the insulating dielectric layer is less than or equal to 20 nm.

In the embodiment of the present invention, the thickness of the insulating dielectric layer ranges from 1nm to 10 μm, and preferably, the thickness of the insulating dielectric layer ranges from 2nm to 20 nm. The thickness of each insulating dielectric layer can be the same or different.

Optionally, the insulating medium layer is SiN or SiO₂Or Al₂O₃Or HfO₂Or other insulating medium or a combination of the above.

In one embodiment of the present invention, the number of carrier-free regions is greater than or equal to 1.

The number of the carrier-free regions may be 1, 2, or more. The carrier-free regions shown in fig. 1 to 4 are each 1. The carrier-free region can be realized by a groove or fluorine plasma treatment or a P-type cap layer and the like.

In one embodiment of the present invention, the width of the non-carrier region is greater than or equal to 1nm, and the width of the non-carrier region is less than or equal to 10 μm.

In one embodiment of the present invention, the width of the carrier-free region is greater than or equal to 50nm, and the width of the carrier-free region is less than or equal to 800 nm.

In the embodiment of the present invention, the width of the carrier-free region is in the range of 1nm to 10 μm, and preferably, the width of the carrier-free region is in the range of 50nm to 800 nm. The width of each of the non-carrier regions may be the same or different.

In one embodiment of the present invention, the number of gate electrodes 80 is greater than or equal to 1.

The number of the gate electrodes 80 may be 1, 2, or more. The number of the gate electrodes 80 shown in fig. 1 to 4 is 2 in each case.

When the number of the gate electrodes 80 is greater than 1, the lengths of the gate electrodes 80 may be equal to each other, may not be equal to each other, may be partially equal to each other, and may not be equal to each other. The length of the gate electrode 80 is the contact length between the gate electrode 80 and the layer below the gate electrode 80, for example, the contact length between the gate electrode 80 and the barrier layer 30 in fig. 1, and the lengths of the two gate electrodes 80 shown in fig. 1 are equal.

The topography of the gate electrode 80 includes one or more of straight gates, T-gates, TT-gates, TTT-gates, V-gates, U-gates, and Y-gates.

When the number of the gate electrodes 80 is 1, the shape of the gate electrode 80 may be any one of a straight gate, a T-shaped gate, a TT-shaped gate, a TTT-shaped gate, a V-shaped gate, a U-shaped gate, and a Y-shaped gate. When the number of the gate electrodes 80 is greater than 1, the shape of each gate electrode 80 may be any one of a straight gate, a T-shaped gate, a TT-shaped gate, a TTT-shaped gate, a V-shaped gate, a U-shaped gate and a Y-shaped gate, and the shape of each gate electrode 80 may be the same or different, or may be partially the same, and the remaining portions are different. In fig. 1 to 4, the gate electrode 80 is a straight gate.

In one embodiment of the present invention, the enhancement mode field effect transistor further comprises a gate insulating dielectric layer 90 between the barrier layer 30 and the passivation layer 40;

a gate insulating dielectric layer 90 is provided under at least one gate electrode 80.

When the number of the gate electrodes 80 is 1, the gate insulating dielectric layer 90 may be present under the gate electrode 80, or the gate insulating dielectric layer 90 may not be present. When the number of the gate electrodes 80 is greater than 1, a gate insulating dielectric layer 90 may be provided below each gate electrode 80, or none of the gate insulating dielectric layers 90 may be provided, or a part of the gate insulating dielectric layer 90 may be provided, and the remaining part of the gate insulating dielectric layer 90 is not provided. Neither of the two gate electrodes 80 shown in fig. 1 has a gate insulating dielectric layer 90 thereunder, and both of the two gate electrodes 80 shown in fig. 2 to 4 have a gate insulating dielectric layer 90 thereunder.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; for example, the carrier-free region is formed by a method other than the method recited in the embodiment of the present invention, the barrier layer, the channel layer and the substrate are made of materials other than the materials described in the embodiment of the present invention, the barrier layer is made of one or more of a multi-layer composite material and the like, the channel layer is made of a multi-layer composite material, a back barrier structure, a multi-layer buffer layer and the like, the substrate is made of a substrate of SiC, Si, diamond, sapphire, GaN and the like, or a multilayer composite substrate is selected, an epitaxial layer directly extends to the substrate or is transferred to other substrates, the shape of the gate is selected from shapes other than those listed in the embodiment of the invention, the insulating medium is of a medium type not listed in the invention, the field plate is made of a plurality of annular metals, the number and the shape of the field plate are changed, and the like, such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.