Semiconductor device and manufacturing method thereof
阅读说明:本技术 一种半导体器件及其制造方法 (Semiconductor device and manufacturing method thereof ) 是由 黎子兰 于 2019-11-14 设计创作,主要内容包括:本公开内容提供一种半导体器件及其制作方法,所述器件包括衬底;在所述衬底上形成的第一绝缘层;在所述第一绝缘层上形成的第一半导体层;所述第一半导体层的侧表面与所述第一绝缘层的上表面斜相交;在所述第一半导体层的侧表面上形成的第二半导体层,在所述第二半导体层的侧表面上形成的第三半导体层,在所述第一至第三半导体层上形成的第四半导体层,所述第四半导体层与第一至第三半导体层的界面处形成二维电荷载流子气。本公开内容有助于实现如下效果之一:器件结构简单、工艺简单、成本低廉以及电性能优良。(The present disclosure provides a semiconductor device and a method of fabricating the same, the device including a substrate; a first insulating layer formed on the substrate; a first semiconductor layer formed on the first insulating layer; the side surface of the first semiconductor layer obliquely intersects with the upper surface of the first insulating layer; a second semiconductor layer formed on a side surface of the first semiconductor layer, a third semiconductor layer formed on a side surface of the second semiconductor layer, a fourth semiconductor layer formed on the first to third semiconductor layers, and a two-dimensional charge carrier gas formed at interfaces of the fourth semiconductor layer and the first to third semiconductor layers. The present disclosure helps to achieve one of the following effects: the device has simple structure, simple process, low cost and excellent electrical property.)
1. A semiconductor device, comprising:
a substrate;
a first insulating layer formed on the first surface of the substrate;
forming the substrate with an exposed opening portion on the first insulating layer;
forming a monocrystalline nucleation layer on the substrate exposed by the opening, and forming a polycrystalline or amorphous nucleation material on the first insulating layer;
and taking the single crystal nucleating layer as a nucleation center, and growing a first semiconductor layer in a lateral epitaxial mode.
2. A semiconductor device, comprising:
a silicon substrate;
forming a first insulating layer on a first surface of the silicon substrate;
forming the substrate with an exposed opening portion on the first insulating layer;
forming a groove on the substrate corresponding to the opening;
forming a single crystal nucleation layer within the trench;
forming a polycrystalline or amorphous nucleation material on the first insulating layer;
and taking the single crystal nucleating layer as a nucleation center, and growing a first semiconductor layer in a lateral epitaxial mode.
3. The semiconductor device according to claim 1 or 2, wherein the semiconductor device is a high mobility transistor, and the opening corresponds to a drain of the high mobility transistor.
4. A semiconductor device, comprising:
a substrate;
a first insulating layer formed on the first surface of the substrate;
forming the substrate with an exposed opening portion on the first insulating layer;
forming a nucleation layer on the substrate exposed by the opening;
forming a polycrystalline or amorphous nucleation material on the first insulating layer; or forming no nucleation material on the first insulating layer;
a first semiconductor layer which is grown in a lateral epitaxial mode by taking the nucleation layer as a nucleation center;
the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer;
forming a second semiconductor layer on the first semiconductor layer second surface and the third surface;
forming a third semiconductor layer on the second semiconductor layer second surface and the third surface;
a fourth semiconductor layer formed on the first surfaces of the first, second, and third semiconductor layers.
5. A semiconductor device, comprising:
a silicon substrate;
forming a first insulating layer on a first surface of the silicon substrate;
forming the substrate with an exposed opening portion on the first insulating layer;
a groove formed on the substrate corresponding to the opening;
a single crystal nucleation layer formed within the trench;
forming a polycrystalline or amorphous nucleation material on the first insulating layer; or forming no nucleation material on the first insulating layer;
taking the single crystal nucleating layer as a nucleation center, and growing a first semiconductor layer in a lateral epitaxial mode;
the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer;
forming a second semiconductor layer on the first semiconductor layer second surface and the third surface;
forming a third semiconductor layer on the second semiconductor layer second surface and the third surface;
a fourth semiconductor layer formed on the first surfaces of the first, second, and third semiconductor layers.
6. A semiconductor device, comprising:
a substrate;
a nucleation layer formed on the first surface of the substrate in a full-covering mode;
a first insulating layer formed on a first surface of the nucleation layer;
forming the nucleation layer with an exposed portion of an opening on the first insulating layer;
a first semiconductor layer which is grown in a lateral epitaxial mode by taking the nucleation layer as a nucleation center;
the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer;
forming a second semiconductor layer on the first semiconductor layer second surface and the third surface;
forming a third semiconductor layer on the second semiconductor layer second surface and the third surface;
a fourth semiconductor layer formed on the first surfaces of the first, second, and third semiconductor layers.
7. A method of manufacturing a semiconductor device, comprising:
step 100: providing a substrate;
step 200: forming a first insulating layer on a first surface of the substrate;
step 300: forming an opening in the first insulating layer to expose a portion of the substrate;
step 400: depositing a nucleation material to fill the opening to form a nucleation layer;
step 500: taking the nucleation layer as a nucleation center, growing a first semiconductor layer in a lateral epitaxial mode, wherein the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer;
step 600: doping P-impurities into the lateral epitaxy by taking the first semiconductor layer as a nucleation center to form a second semiconductor material layer;
step 700: continuing to grow a third semiconductor material layer in a lateral epitaxial mode, and removing the second semiconductor material layer and the third semiconductor material layer on the first surface of the first semiconductor layer to form a second semiconductor layer and a third semiconductor layer;
step 800: forming a fourth semiconductor layer on the first to third semiconductor layers, and forming a two-dimensional charge carrier gas at interfaces of the fourth semiconductor layer and the first to third semiconductor layers.
8. A method of manufacturing a semiconductor device, comprising:
step 100: providing a substrate;
step 200: forming a nucleation layer on the first surface of the substrate in a covering mode;
step 300: forming a first insulating layer on the nucleation layer;
step 400: forming an opening in the first insulating layer to expose a portion of the nucleation layer;
step 500: taking the nucleation layer as a nucleation center, growing a first semiconductor layer in a lateral epitaxial mode, wherein the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer;
step 600: doping P-impurities into the lateral epitaxy by taking the first semiconductor layer as a nucleation center to form a second semiconductor material layer;
step 700: continuing to grow a third semiconductor material layer in a lateral epitaxial mode, and removing the second semiconductor material and the third semiconductor material on the first surface of the first semiconductor layer to form a second semiconductor layer and a third semiconductor layer;
step 800: forming a fourth semiconductor layer on the first to third semiconductor layers, and forming a two-dimensional charge carrier gas at interfaces of the fourth semiconductor layer and the first to third semiconductor layers.
9. A method of manufacturing a semiconductor device, comprising:
step 100: providing a silicon substrate;
step 200: forming a first insulating layer on a first surface of the silicon substrate;
step 300: forming an opening in the first insulating layer to expose a portion of the silicon substrate;
step 400: etching the exposed silicon substrate to form a groove on the silicon substrate;
step 500: depositing a nucleation material to fill the trench to form a nucleation layer;
step 600: taking the nucleation layer as a nucleation center, growing a first semiconductor layer in a lateral epitaxial mode, wherein the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer;
step 700: doping P-impurities into the lateral epitaxy by taking the first semiconductor layer as a nucleation center to form a second semiconductor material layer;
step 800: continuing to grow a third semiconductor material layer in a lateral epitaxial mode, and removing the second semiconductor material layer and the third semiconductor material layer on the first surface of the first semiconductor layer to form a second semiconductor layer and a third semiconductor layer;
step 900: forming a fourth semiconductor layer on the first to third semiconductor layers, and forming a two-dimensional charge carrier gas at interfaces of the fourth semiconductor layer and the first to third semiconductor layers.
10. An electronic device comprising the semiconductor device according to any one of claims 1 to 9.
Technical Field
The present disclosure relates to the field of power semiconductor devices, and more particularly, to a transistor having high electron mobility and a method of fabricating the same.
Background
Group III nitride semiconductors are an important new semiconductor material, mainly including AlN, GaN, InN, and compounds of these materials such as AlGaN, InGaN, AlInGaN, and the like. The III nitride semiconductor has great prospect in the field of power semiconductors by utilizing the advantages of direct band gap, wide forbidden band, high breakdown electric field intensity and the like of the III nitride semiconductor and optimizing the design of device structures and processes. One important device type of the group III nitride semiconductor is a high electron mobility transistor, and it is desirable to develop a high electron mobility transistor having high performance such as high withstand voltage, high power, and low on-resistance.
The existing high electron mobility transistor has the problems of complex structure, complex process, high cost and the like, and the structure in the high electron mobility transistor, such as a nucleating layer, can be strip-shaped, and the strip-shaped structure is easy to have some gaps or uneven surface in the growth process; the epitaxial semiconductor layer structure of the high electron mobility transistor is generally layered, and the problems of overlarge internal stress and the like easily exist; and such a layered structure is disadvantageous for realizing a device structure having a specific function. In view of the above, the present disclosure provides a novel semiconductor device structure and a method for manufacturing the same, which aims to overcome the above-mentioned drawbacks and provide a semiconductor device with simple structure, simple process, low cost and excellent electrical performance.
Disclosure of Invention
A brief summary of the disclosure is provided below in order to provide a basic understanding of some aspects of the disclosure. It should be understood that this summary is not an exhaustive overview of the disclosure. It is not intended to identify key or critical elements of the disclosure or to delineate the scope of the disclosure. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
According to an aspect of the present disclosure, there is provided a semiconductor device including: a substrate; a first insulating layer formed on the first surface of the substrate; forming the substrate with an exposed opening portion on the first insulating layer; forming a monocrystalline nucleation layer on the substrate exposed by the opening, and forming a polycrystalline or amorphous nucleation material on the first insulating layer; and taking the single crystal nucleating layer as a nucleation center, and growing a first semiconductor layer in a lateral epitaxial mode.
According to another aspect of the present disclosure, there is provided a semiconductor device including: a silicon substrate; forming a first insulating layer on a first surface of the silicon substrate; forming the substrate with an exposed opening portion on the first insulating layer; forming a groove on the substrate corresponding to the opening; forming a single crystal nucleation layer within the trench; forming a polycrystalline or amorphous nucleation material on the first insulating layer; and taking the single crystal nucleating layer as a nucleation center, and growing a first semiconductor layer in a lateral epitaxial mode.
Further, the single crystal nucleation layer is single crystal AlN and the polycrystalline or amorphous nucleation material is polycrystalline or amorphous AlN.
Further, the first insulating layer is SiO2Layer or Si3N4And (3) a layer.
Further, the first semiconductor layer is a nitride semiconductor layer.
Further, the substrate is selected from sapphire, ZnO, SiC, AlN, GaAs, LiAlO, GaAlLiO, GaN, Al2O3Or monocrystalline silicon.
Further wherein the depth of the trench is 0.2-10 microns deep.
Further wherein the depth of the trench is about 1 micron.
Further, an insulating protection layer is formed on the two side walls of the groove and the opening.
Further, wherein the insulating protective layer is SiO2And an insulating protective layer.
Further wherein the semiconductor device is a high mobility transistor, the opening corresponds to a drain of the high mobility transistor.
According to another aspect of the present disclosure, there is provided a semiconductor device including: a substrate; a first insulating layer formed on the first surface of the substrate; forming the substrate with an exposed opening portion on the first insulating layer; forming a nucleation layer on the substrate exposed by the opening; forming a polycrystalline or amorphous nucleation material on the first insulating layer; or forming no nucleation material on the first insulating layer; a first semiconductor layer which is grown in a lateral epitaxial mode by taking the nucleation layer as a nucleation center; the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer; forming a second semiconductor layer on the first semiconductor layer second surface and the third surface; forming a third semiconductor layer on the second semiconductor layer second surface and the third surface; a fourth semiconductor layer formed on the first surfaces of the first, second, and third semiconductor layers.
According to another aspect of the present disclosure, there is provided a semiconductor device including: a silicon substrate; forming a first insulating layer on a first surface of the silicon substrate; forming the substrate with an exposed opening portion on the first insulating layer; a groove formed on the substrate corresponding to the opening; a single crystal nucleation layer formed within the trench; forming a polycrystalline or amorphous nucleation material on the first insulating layer; or forming no nucleation material on the first insulating layer; taking the single crystal nucleating layer as a nucleation center, and growing a first semiconductor layer in a lateral epitaxial mode; the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer; forming a second semiconductor layer on the first semiconductor layer second surface and the third surface; forming a third semiconductor layer on the second semiconductor layer second surface and the third surface; a fourth semiconductor layer formed on the first surfaces of the first, second, and third semiconductor layers.
According to another aspect of the present disclosure, there is provided a semiconductor device including: a substrate; a nucleation layer formed on the first surface of the substrate in a full-covering mode; a first insulating layer formed on a first surface of the nucleation layer; forming the nucleation layer with an exposed portion of an opening on the first insulating layer; a first semiconductor layer which is grown in a lateral epitaxial mode by taking the nucleation layer as a nucleation center; the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer; forming a second semiconductor layer on the first semiconductor layer second surface and the third surface; forming a third semiconductor layer on the second semiconductor layer second surface and the third surface; a fourth semiconductor layer formed on the first surfaces of the first, second, and third semiconductor layers.
Further wherein a two-dimensional charge carrier gas is formed at interfaces between the fourth semiconductor layer and the first, second, and third semiconductor layers.
Further wherein a fifth semiconductor layer that is either unintentionally doped or lowly doped is further included between the fourth semiconductor layer and the first, second and third semiconductor layers, a two-dimensional charge carrier gas being formed at the interface between the fourth semiconductor layer and the fifth semiconductor layer.
Further, the doping concentration of the low-doped fifth semiconductor layer is<2E18/cm3。
Further wherein the angle is between 30-75 degrees.
Further wherein the second semiconductor layer is a P-type buried layer.
Further, the doping concentration of the P-type buried layer is 1E17-5E19/cm3。
Further, wherein the first surface of the first semiconductor layer, the first surface of the second semiconductor layer, and the first surface of the third semiconductor layer are approximately in the same plane.
Further wherein the fourth semiconductor is selected from AlGaN, InAlGaN, or InAlN.
Further, a first electrode, a second electrode, and a third electrode are formed on the first surface of the fourth semiconductor.
Further, the range of the first end of the second semiconductor layer projected onto the first surface of the substrate is overlapped with the range of the second electrode projected onto the substrate; or the range of the first end of the second semiconductor layer projected to the substrate is positioned in the range of the second electrode projected to the first surface of the substrate.
Further, the range of the second end of the second semiconductor layer projected onto the first surface of the substrate is overlapped with the range of the first electrode projected onto the substrate; or the projection range of the second end of the second semiconductor layer to the substrate is positioned in the projection range of the first electrode to the first surface of the substrate.
Further, the semiconductor device further comprises a fourth electrode which forms ohmic contact with the second semiconductor layer.
Further, there is a second insulating layer formed over the fourth semiconductor and under the second electrode.
Further, the nucleation layer is formed on the substrate, and the buffer layer is formed on the nucleation layer.
Further, the second semiconductor layer includes at least two sub-layers, wherein the first sub-layer has a weak P-type doping concentration relative to the second sub-layer, and the second sub-layer has a strong P-type doping concentration relative to the first sub-layer.
Further, the first sublayer is closer to the third electrode than the second sublayer.
Further wherein the second semiconductor layer has a doping concentration sufficient to deplete 95% to 100% of the two-dimensional charge carrier gas in at least a portion of the region overlapping the projected area of the second electrode in the absence of a device bias voltage.
Further, when the bias voltage of the second electrode is 0, the two-dimensional charge carrier gas corresponding to at least a partial region of the second electrode is lower than 5E +11/cm2。
Further, the doping concentration of the second semiconductor layer is uniform, or the doping concentration of the second semiconductor layer is gradually decreased or is gradually decreased along the direction from the second electrode to the third electrode; or the doping concentrations in the first sublayer and the second sublayer are uniform, or the doping concentrations in the first sublayer and the second sublayer decrease in a gradient or step-wise manner along the direction from the second electrode to the third electrode.
According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: step 100: providing a substrate; step 200: forming a first insulating layer on a first surface of the substrate; step 300: forming an opening in the first insulating layer to expose a portion of the substrate; step 400: depositing a nucleation material to fill the opening to form a nucleation layer; step 500: taking the nucleation layer as a nucleation center, growing a first semiconductor layer in a lateral epitaxial mode, wherein the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer; step 600: doping P-impurities into the lateral epitaxy by taking the first semiconductor layer as a nucleation center to form a second semiconductor material layer; step 700: continuing to grow a third semiconductor material layer in a lateral epitaxial mode, and removing the second semiconductor material layer and the third semiconductor material layer on the first surface of the first semiconductor layer to form a second semiconductor layer and a third semiconductor layer; step 800: forming a fourth semiconductor layer on the first to third semiconductor layers, and forming a two-dimensional charge carrier gas at interfaces of the fourth semiconductor layer and the first to third semiconductor layers.
According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: step 100: providing a substrate; step 200: forming a nucleation layer on the first surface of the substrate in a covering mode; step 300: forming a first insulating layer on the nucleation layer; step 400: forming an opening in the first insulating layer to expose a portion of the nucleation layer; step 500: taking the nucleation layer as a nucleation center, growing a first semiconductor layer in a lateral epitaxial mode, wherein the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer; step 600: doping P-impurities into the lateral epitaxy by taking the first semiconductor layer as a nucleation center to form a second semiconductor material layer; step 700: continuing to grow a third semiconductor material layer in a lateral epitaxial mode, and removing the second semiconductor material and the third semiconductor material on the first surface of the first semiconductor layer to form a second semiconductor layer and a third semiconductor layer; step 800: forming a fourth semiconductor layer on the first to third semiconductor layers, and forming a two-dimensional charge carrier gas at interfaces of the fourth semiconductor layer and the first to third semiconductor layers.
According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: step 100: providing a silicon substrate; step 200: forming a first insulating layer on a first surface of the silicon substrate; step 300: forming an opening in the first insulating layer to expose a portion of the silicon substrate; step 400: etching the exposed silicon substrate to form a groove on the silicon substrate; step 500: depositing a nucleation material to fill the trench to form a nucleation layer; step 600: taking the nucleation layer as a nucleation center, growing a first semiconductor layer in a lateral epitaxial mode, wherein the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer; step 700: doping P-impurities into the lateral epitaxy by taking the first semiconductor layer as a nucleation center to form a second semiconductor material layer; step 800: continuing to grow a third semiconductor material layer in a lateral epitaxial mode, and removing the second semiconductor material layer and the third semiconductor material layer on the first surface of the first semiconductor layer to form a second semiconductor layer and a third semiconductor layer; step 900: forming a fourth semiconductor layer on the first to third semiconductor layers, and forming a two-dimensional charge carrier gas at interfaces of the fourth semiconductor layer and the first to third semiconductor layers.
Further wherein the angle is between 30-75 degrees.
Further, the doping concentration of the P-impurity is 1E17-5E19/cm 3.
Further, the method also comprises the step 1000: forming a first region and a second region doped with N + by a doping process, which form ohmic contact with the two-dimensional charge carrier gas and simultaneously form ohmic contact with the second semiconductor layer, and then forming a first electrode and a third electrode on the fourth semiconductor layer corresponding to the first and second regions, respectively, and forming a second electrode between the first electrode and the third electrode.
Further, the range of the first end of the second semiconductor layer projected to the first surface of the substrate is overlapped with the range of the second electrode projected to the first surface of the substrate; or the projection range of the first end of the second semiconductor layer to the substrate is positioned in the projection range of the second electrode to the first surface of the substrate.
Further, the range of the second end of the second semiconductor layer projected to the first surface of the substrate is overlapped with the range of the first electrode projected to the first surface of the substrate; or the range of the second end of the second semiconductor layer projected to the first surface of the substrate is positioned in the range of the first electrode projected to the first surface of the substrate.
Further, wherein the opening is formed at a position corresponding to the formation of the third electrode.
And further forming an insulating protection layer on the side walls of the groove and the opening and the bottom surface of the groove through a deposition process, and removing the insulating protection layer on the bottom surface of the groove through an anisotropic etching process to expose the substrate.
Further, the nucleated AlN material is filled in the growth atmosphere of the chlorine-containing gas, so that the nucleating material AlN is hardly deposited on the first surface of the first insulating layer, and the nucleating layer is formed only at the openings and/or the grooves.
And further, etching a through hole reaching the second part of the second semiconductor layer on the second surface of the substrate, and depositing an electrode material in the through hole to form a fourth electrode.
And further etching the first surface of the fourth semiconductor layer to form a through hole reaching the second part of the second semiconductor layer, and depositing an electrode material in the through hole to form a fourth electrode.
Further, a second insulating material layer is formed on the fourth semiconductor layer in a covering mode, or a second insulating material layer is formed on the fourth semiconductor layer and then the second insulating material at the second electrode area is reserved.
Further, the method also comprises the step of depositing a buffer layer on the nucleation layer before forming the first semiconductor layer.
And further adjusting the doping amount of introduced P-type impurities on the second surface and the third surface of the first semiconductor layer, and sequentially epitaxially forming a first sublayer with weak P-type doping concentration and a second sublayer with strong P-type doping concentration of the second semiconductor layer.
Further wherein the doping concentration of the first sublayer is <5E18/cm 3; the doping concentration of the second sublayer is 1E17-5E19/cm 3.
Further, the doping concentration in each of the first sublayer and the second sublayer is uniform, or decreases in a gradient along the direction from the second electrode to the third electrode or decreases in a step along the direction from the second electrode to the third electrode.
According to another aspect of the present disclosure, there is provided an electronic device including the semiconductor device in the present disclosure.
Further, the electronic device is a power supply device, a mobile phone, or a power amplifier in a communication system.
The scheme of the disclosure can at least help to realize one of the following effects: the semiconductor device can reduce grid leakage current, has high threshold voltage, high power and high reliability, can realize low on-resistance and normally-off state of the device, and can provide stable threshold voltage, so that the semiconductor device has good switching characteristic and is safer in use.
The structure and the preparation process of the semiconductor device are simple, and the production cost can be effectively reduced.
Drawings
The above and other objects, features and advantages of the present disclosure will be more readily understood from the following detailed description of the present disclosure with reference to the accompanying drawings. The drawings are only for the purpose of illustrating the principles of the disclosure. The dimensions and relative positioning of the elements in the figures are not necessarily drawn to scale. In the drawings:
fig. 1-2 show a schematic cross-sectional view of a semiconductor device structure according to a first embodiment;
fig. 3 shows a schematic cross-sectional view of a semiconductor device structure according to a second embodiment;
fig. 4 shows a schematic cross-sectional view of a semiconductor device structure according to a third embodiment;
fig. 5 shows a schematic cross-sectional view of a semiconductor device structure according to a fourth embodiment;
fig. 6 shows a schematic cross-sectional view of a semiconductor device structure according to a fifth embodiment;
fig. 7 shows a schematic cross-sectional view of a semiconductor device structure according to a sixth embodiment;
fig. 8 to 15 show schematic cross-sectional views of a method of manufacturing a semiconductor device according to a seventh embodiment;
fig. 16 to 19 are schematic cross-sectional views showing a method of manufacturing a semiconductor device of an eighth embodiment.
Detailed Description
Exemplary disclosures of the present disclosure will be described hereinafter with reference to the accompanying drawings. In the interest of clarity and conciseness, not all features of an implementation of the present disclosure are described in the specification. It will be appreciated, however, that in the development of any such actual implementation of the disclosure, numerous implementation-specific decisions may be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another.
Here, it should be further noted that, in order to avoid obscuring the present disclosure by unnecessary details, only device structures closely related to the scheme according to the present disclosure are shown in the drawings, and other details not so related to the present disclosure are omitted.
It is to be understood that the disclosure is not limited to the described embodiments, as described below with reference to the drawings. Herein, features between different implementations may be replaced or borrowed where feasible, and one or more features may be omitted in one implementation.
Specifically, the semiconductor device of the present disclosure is a compound semiconductor device including a nitride semiconductor material, also referred to as a nitride semiconductor device. The nitride semiconductor device includes a transistor in which a nitride semiconductor material is used. Further, the transistor is a GaN transistor including a GaN semiconductor material. In particular, the GaN transistor is a normally-off transistor GaN-HEMT.
First embodiment
A semiconductor device according to a first embodiment is described with reference to fig. 1 to 2.
As shown in fig. 1, in the first embodiment, the semiconductor device, such as an exemplary normally-off HEMT device, includes a
Preferably, when an opening on the first insulating
Alternatively, as shown in fig. 2, a nucleation layer 103 'is blanket formed on a
Wherein the
A
A
A
A
The
The
A
In this embodiment mode, it is preferable that the nucleation layer is formed at a position corresponding to formation of a drain electrode of a subsequent semiconductor device, with respect to a position corresponding to formation of a source electrode of a subsequent semiconductor device where the nucleation layer is formed. In this embodiment, the
Second embodiment
As shown in fig. 3, in a second embodiment, the semiconductor device, an exemplary, e.g., normally-off HEMT device, includes a
In this embodiment, the groove is formed in the
Third embodiment
Referring to fig. 4, on the basis of the first embodiment or the second embodiment, there is further provided a
Fourth embodiment
Referring to fig. 5, on the basis of the first to third embodiments, the second insulating
Fifth embodiment
Referring to fig. 6, on the basis of the first embodiment or the second embodiment, before forming the first semiconductor layer, a
Sixth embodiment
Referring to fig. 7, on the basis of the first embodiment or the second embodiment, the
Further alternatively, the
Seventh embodiment
A manufacturing method for manufacturing the semiconductor device of the first embodiment will now be exemplarily described with reference to fig. 8 to 15.
A
When the opening on the first insulating
When the opening on the first insulating
Specifically, a
Alternatively, a nucleation layer 103 'is blanket formed on the
A first semiconductor layer 104 (e.g., intrinsic i-GaN or unintentionally doped GaN layer) is formed by lateral epitaxy on the first surface of the first insulating
A second semiconductor layer is formed on the second surface and the third surface of the
And continuing to form a third semiconductor material on the second semiconductor layer in a lateral epitaxy mode through a lateral epitaxy process. The third semiconductor material covers the first to third surfaces of the second semiconductor layer. Portions of the upper surfaces of the third semiconductor material and the second semiconductor layer are removed to form the discrete
A
Illustratively, a first region and a second region (source/drain region) doped with N + are formed at corresponding positions by a doping process such as ion implantation, which form ohmic contact with the two-dimensional charge carrier gas and then form a first electrode on the first region by a process such as sputtering, evaporation, etc., and form a third electrode on the second region by a process such as sputtering, evaporation, etc. The first and third electrode materials may be TiN, Ni, ITO, Au, etc., and a second electrode is formed on the fourth semiconductor layer between the first and third electrodes.
Eighth embodiment
A manufacturing method for manufacturing the semiconductor device of the second embodiment will now be exemplarily described with reference to fig. 16 to 19.
A
Alternatively, a nucleation layer 103 'is blanket formed on the
The following formation of the respective structural features is performed with reference to the seventh embodiment, and is not described in detail here.
Ninth embodiment
On the basis of the seventh and eighth embodiments, a through hole reaching the second portion of the
Alternatively, a via hole is etched in the first surface of the
It is to be understood that the fourth electrode is not limited to this, and may be drawn out from the side of the
Tenth embodiment
In the seventh embodiment or the eighth embodiment, a second insulating material is formed over the
Eleventh embodiment
On the basis of the seventh or eighth embodiment, a buffer layer is deposited on the nucleation layer before the first semiconductor layer is formed.
Twelfth embodiment
The
It is understood that the sub-layers may be provided as multiple layers without being limited to two layers by adjusting the concentration of dopants during epitaxy.
The doping concentration in the further individual sub-layers may also be adjusted during epitaxy to provide a uniform, regular or irregular, e.g. a unilateral gradient decreasing or a step change between the individual sub-layers, within the individual sub-layers along the direction from the
The processes of the rest parts refer to the seventh or eighth embodiment, and are not described herein again.
Thirteenth embodiment
A power supply device comprising any one of the semiconductor devices in the above embodiments. The power supply device includes a primary circuit, a secondary circuit, a transformer, and the like, wherein each of the primary circuit and the secondary circuit includes a switching element, and the switching element includes any one of the semiconductor devices in the above-described embodiments.
Fourteenth embodiment
A cellular phone comprising any of the semiconductor devices in the above embodiments. The mobile phone includes a display screen, a charging unit, and the like, wherein the charging unit includes any of the semiconductor devices in the above embodiments.
Fifteenth embodiment
An amplifier which can be used for a power amplifier in the field of a mobile phone base station, an optical communication system, or the like, may include any of the semiconductor devices in the above embodiments.
While the disclosure has been described with reference to specific embodiments, it will be apparent to those skilled in the art that these descriptions are intended in an illustrative rather than in a limiting sense. Various modifications and alterations of this disclosure will become apparent to those skilled in the art from the spirit and principles of this disclosure, and such modifications and alterations are also within the scope of this disclosure.
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