阅读说明：本技术 一种无频率过冲的数字锁相环 (Digital phase-locked loop without frequency overshoot ) 是由 不公告发明人 于 2019-08-16 设计创作，主要内容包括：本发明公开了一种无频率过冲的数字锁相环,包括频率量化器、过冲抑制滤波器以及数控振荡器；所述压控振荡器输出时钟信号至频率量化器；频率量化器用于直接量化压控振荡器所输出时钟信号的频率；过冲抑制滤波器根据所得到的频率信息和预期的频率信息的差异,以动态地调整滤波器的环路参数,输出无过冲的频率控制信息给到数控振荡器,数控振荡器根据接收到的频率控制信息来输出对应频率的时钟信号,该时钟信号作为数字锁相环的输出供给数字电路使用。本发明的频率量化器直接量化压控振荡器输出的频率,得到的频率信息送入过冲抑制滤波器中,动态并且无频率过冲地产生控制信号,给到数控振荡器调整其频率,借此实现无频率过冲的数字锁相环。(The invention discloses a digital phase-locked loop without frequency overshoot, which comprises a frequency quantizer, an overshoot suppression filter and a numerical control oscillator; the voltage-controlled oscillator outputs a clock signal to a frequency quantizer; the frequency quantizer is used for directly quantizing the frequency of the clock signal output by the voltage-controlled oscillator; the overshoot suppression filter dynamically adjusts the loop parameters of the filter based on the difference between the obtained frequency information and the expected frequency information, outputs frequency control information without overshoot to the numerically controlled oscillator, and the numerically controlled oscillator outputs a clock signal of a corresponding frequency based on the received frequency control information, and the clock signal is supplied to the digital circuit as the output of the digital phase locked loop. The frequency quantizer directly quantizes the frequency output by the voltage-controlled oscillator, the obtained frequency information is sent to the overshoot suppression filter, a control signal is generated dynamically without frequency overshoot, and the frequency is adjusted to the digital-controlled oscillator, so that the digital phase-locked loop without frequency overshoot is realized.)

1. A digital phase locked loop without frequency overshoot is characterized by comprising a frequency quantizer, an overshoot suppression filter and a numerical control oscillator; the digitally controlled oscillator comprises a voltage controlled oscillator; the overshoot suppression filter comprises a filter;

the voltage-controlled oscillator outputs a clock signal to a frequency quantizer;

the frequency quantizer is used for directly quantizing the frequency of the clock signal output by the voltage-controlled oscillator to obtain frequency information corresponding to the clock signal and transmitting the frequency information to the overshoot suppression filter;

the overshoot suppression filter dynamically adjusts the loop parameters of the filter based on the difference between the obtained frequency information and the expected frequency information, outputs frequency control information without overshoot to the numerically controlled oscillator, and the numerically controlled oscillator outputs a clock signal of a corresponding frequency based on the received frequency control information, and the clock signal is supplied to the digital circuit as the output of the digital phase locked loop.

2. The digital phase locked loop without frequency overshoot as claimed in claim 1, wherein the loop parameter of the filter is adjusted to be over-damped when the frequency deviation of the frequency information obtained by the overshoot suppression filter and the expected frequency information is larger than a preset value.

3. The digital phase locked loop without frequency overshoot as claimed in claim 1, wherein the loop parameters of the filter are adjusted to be critically damped or to remain over-damped when the frequency deviation between the frequency information obtained by the overshoot suppression filter and the expected frequency information is less than a predetermined value.

4. The digital phase locked loop without frequency overshoot of claim 1, wherein the current phase error information needs to be reset at a time when a predetermined value is exceeded during a process of decreasing a frequency deviation between the frequency information obtained by the overshoot suppression filter and the expected frequency information.

5. The digital phase locked loop without frequency overshoot as defined in claim 1, wherein the frequency quantizer comprises a counter and a synchronizer; the counter is used for quantizing the frequency of the clock signal output from the voltage-controlled oscillator to obtain frequency information corresponding to the clock signal, and transmitting the frequency information to the synchronizer, and the synchronizer is used for synchronizing the received frequency information to the reference clock domain.

6. The digital phase locked loop without frequency overshoot as defined in claim 1, wherein the overshoot suppression filter further comprises a state machine for dynamically adjusting loop parameters of the filter based on a difference between the obtained frequency information and the expected frequency information.

7. A digital phase locked loop without frequency overshoot according to any of the claims 1-7, characterized in that the expected frequency information is the product of an input reference clock and an input division factor.

Technical Field

The invention relates to a digital phase-locked loop, in particular to a digital phase-locked loop without frequency overshoot.

Background

A Phase Lock Loop (PLL) is a very common circuit unit used to provide an accurate configurable clock source. Modern large-scale digital circuit designs typically use one or more PLLs to generate the desired clock for synchronizing the digital circuits, and existing phase-locked loops are shown in detail in fig. 1.

Generally, the faster the clock frequency, the better the performance of the digital circuit, but is limited by the physical characteristics of the devices and interconnects, and when the clock frequency is too fast, the digital circuit using the clock source may experience errors due to timing violations. Therefore, the PLL that provides the clock source for the digital circuit needs to be supplied to the digital circuit module after the clock is stabilized. While a typical PLL may have a small frequency overshoot (frequency overshoot) during locking or re-locking during a start-up process or when a low frequency clock is switched to a high frequency clock, such a clock may cause an error if the clock is directly supplied to a digital circuit without limitation. In large-scale circuit design, performance and power consumption are usually the key points of compromise. Dynamic Frequency Scaling (DFS) can achieve performance and power optimization by frequently switching clock frequencies. However, in the process of switching the frequency, the digital circuit needs to be suspended, so as to avoid timing violation caused by small frequency overshoot generated in the switching process.

In a conventional phase-locked loop design, during a start-up process or when a low-frequency clock is switched to a high-frequency clock, a small frequency overshoot occurs during a clock locking or re-locking process. Therefore, it is still necessary to suspend the digital circuit during the pll start-up or frequency switching process to avoid timing violations.

Disclosure of Invention

In order to solve the problem that the traditional phase-locked loop has small frequency overshoot in the process of clock locking or re-locking when the traditional phase-locked loop is started or switched from a low-frequency clock to a high-frequency clock, the invention provides the digital phase-locked loop without frequency overshoot, so that the frequency overshoot is completely avoided in the process of frequency switching, the normal work of a digital circuit is not required to be suspended, and the work efficiency can be further improved.

In order to achieve the purpose, the technical scheme of the invention is as follows:

a digital phase locked loop without frequency overshoot comprises a frequency quantizer, an overshoot suppression filter and a numerical control oscillator; the digitally controlled oscillator comprises a voltage controlled oscillator; the overshoot suppression filter comprises a filter;

the voltage-controlled oscillator outputs a clock signal to a frequency quantizer;

the frequency quantizer is used for directly quantizing the frequency of the clock signal output by the voltage-controlled oscillator to obtain frequency information corresponding to the clock signal and transmitting the frequency information to the overshoot suppression filter;

the overshoot suppression filter dynamically adjusts the loop parameters of the filter based on the difference between the obtained frequency information and the expected frequency information, outputs frequency control information without overshoot to the numerically controlled oscillator, and the numerically controlled oscillator outputs a clock signal of a corresponding frequency based on the received frequency control information, and the clock signal is supplied to the digital circuit as the output of the digital phase locked loop.

Further, when the frequency deviation between the frequency information obtained by the overshoot suppression filter and the expected frequency information is larger than a preset value, the loop parameter of the filter is adjusted to be over-damped.

Further, when the frequency deviation between the frequency information obtained by the overshoot suppression filter and the expected frequency information is smaller than a preset value, the loop parameter of the filter is adjusted to be critical damping or still keep over-damping.

Further, when the frequency deviation between the frequency information obtained by the overshoot suppression filter and the expected frequency information is decreased, the current phase error information needs to be reset at the time when the preset value is exceeded.

Further, the frequency quantizer comprises a counter and a synchronizer; the counter is used for quantizing the frequency of the clock signal output from the voltage-controlled oscillator to obtain frequency information corresponding to the clock signal, and transmitting the frequency information to the synchronizer, and the synchronizer is used for synchronizing the received frequency information to the reference clock domain.

Further, the overshoot suppression filter further comprises a state machine for dynamically adjusting the loop parameters of the filter based on a difference between the obtained frequency information and the expected frequency information.

Further, the expected frequency information is a product of an input reference clock and an input division coefficient.

Compared with the prior art, the invention has the beneficial effects that:

different from the traditional PLL design, the frequency quantizer directly quantizes the frequency output by the voltage-controlled oscillator, the obtained frequency information is sent into an overshoot suppression filter, a control signal is generated dynamically without frequency overshoot, the frequency is adjusted to the digital-controlled oscillator, and therefore the digital phase-locked loop without frequency overshoot is achieved.

Drawings

FIG. 1 is a prior art digital phase locked loop;

fig. 2 is a first schematic diagram illustrating a digital phase-locked loop without frequency overshoot according to an embodiment of the present invention;

fig. 3 is a schematic diagram illustrating a digital phase-locked loop without frequency overshoot according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating the variation of the output clock frequency of a conventional phase-locked loop with time during the locking process;

FIG. 5 is a schematic diagram of the output clock frequency of the digital PLL without frequency overshoot according to the present invention varying with time during the locking process;

in the figure: 1. a frequency quantizer; 2. an overshoot suppression filter; 3. a numerically controlled oscillator; 11. a counter; 12. a synchronizer; 21. a filter; 22. a state machine; 31. a voltage controlled oscillator; 32. an analog-to-digital converter.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and detailed description.