阅读说明：本技术 垂直晶体管自对准触点工艺形成的嵌入式底部金属触点 (Embedded bottom metal contact formed by vertical transistor self-aligned contact process ) 是由 刘作光 范淑贞 吴恒 山下典洪 于 2018-04-19 设计创作，主要内容包括：实施例涉及用于具有嵌入式底部金属触点的垂直场效应晶体管(VFET)的方法和所得结构。在衬底的掺杂区域上形成半导体鳍片。使与半导体鳍片相邻的掺杂区域的一部分凹陷,并且在凹陷部分上形成嵌入式触点。选择导电轨道的材料使得嵌入式触点的导电率高于掺杂区域的导电率。(Embodiments relate to methods and resulting structures for Vertical Field Effect Transistors (VFETs) with embedded bottom metal contacts. A semiconductor fin is formed on a doped region of a substrate. A portion of the doped region adjacent to the semiconductor fin is recessed and an embedded contact is formed on the recessed portion. The material of the conductive tracks is chosen such that the electrical conductivity of the embedded contacts is higher than the electrical conductivity of the doped regions.)

1. A method of forming a semiconductor device, the method comprising:

forming a semiconductor fin on the doped region of the substrate;

recessing a portion of the doped region; and

forming an embedded contact on the recessed portion of the doped region;

wherein the embedded contact has a conductivity higher than a conductivity of the doped region.

2. The method of claim 1, further comprising forming a conductive gate over a channel region of the semiconductor fin.

3. The method of claim 2, further comprising forming a bottom spacer between the doped region and the conductive gate.

4. The method of claim 3, further comprising forming a top spacer over the conductive gate and the bottom spacer.

5. The method of claim 1, further comprising forming a conductive contact on a surface of the semiconductor fin.

6. The method of claim 1, further comprising forming a conductive contact on a surface of the embedded contact.

7. The method of claim 1, wherein the embedded contact is wrapped around three sides of the semiconductor fin.

8. The method of claim 1, wherein the embedded contact comprises a metal.

9. The method of claim 1, wherein the embedded contact comprises titanium.

10. The method of claim 1, wherein forming the recessed contact comprises conformally depositing a conductive material over the recessed portion of the doped region and over sidewalls of the conductive gate.

11. The method of claim 10, wherein forming the recessed contact further comprises removing the portion of the recessed contact deposited on a sidewall of the conductive gate.

12. The method of claim 1, wherein the recessed portion of the doped region is recessed by about 10 to about 15 nm.

13. A method for forming a semiconductor device, the method comprising:

forming a semiconductor fin on the doped region of the substrate;

forming a conductive gate over a channel region of the semiconductor fin;

recessing a portion of the doped region adjacent to the semiconductor fin;

forming a conductive track on a recessed portion of the doped region;

forming a dielectric layer between the conductive track and the conductive gate;

forming a first conductive contact on a surface of the conductive track; and

forming a second conductive contact on a surface of the semiconductor fin;

wherein the conductive track has a conductivity higher than the conductivity of the doped region.

14. The method of claim 13, wherein the conductive track is wrapped around three sides of the semiconductor fin.

15. The method of claim 13, wherein the conductive track comprises a metal.

16. The method of claim 15, wherein forming the conductive track comprises depositing the metal over the recessed portion of the doped region and over a sidewall of the conductive gate.

17. The method of claim 16, wherein forming the conductive track further comprises removing the portion of the conductive track deposited on a sidewall of the conductive gate.

18. The method of claim 13, wherein the conductive track comprises a thickness of about 7 to about 12 nm.

19. A semiconductor device, comprising:

a semiconductor fin on a doped region of a substrate; and

embedded bottom contacts formed on recessed portions of the doped regions along three sides of the semiconductor fin;

wherein the embedded bottom contact has a conductivity higher than a conductivity of the doped region.

20. The semiconductor device of claim 19, wherein the embedded bottom contact comprises a thickness of about 7 to about 12 nm.

21. A semiconductor device, comprising:

a semiconductor fin on a doped region of a substrate;

a conductive gate formed over a channel region of the semiconductor fin;

a bottom spacer between the conductive gate and the doped region;

a conductive track on a recessed portion of the doped region;

a dielectric layer between the conductive track and the conductive gate;

a first conductive contact on a surface of the conductive track; and

a second conductive contact on a surface of the semiconductor fin;

wherein the conductive track has a conductivity higher than the conductivity of the doped region.

22. The semiconductor device of claim 19, wherein said embedded bottom contact is recessed about 3 to about 5nm below said bottom spacer.

23. A method of operating a semiconductor device, the method comprising:

provided is a semiconductor device including:

a semiconductor fin on a bottom doped region of a substrate;

a conductive gate formed over a channel region of the semiconductor fin;

a top doped region on a surface of the semiconductor fin;

a top source/drain (S/D) contact on a surface of the top doped region;

a conductive track on a recessed portion of the doped region; and

a bottom S/D contact on the surface of the conductive track; and

passing current from the top S/D contact to the bottom S/D contact through a portion of a conductive track.

24. The method of claim 23, further comprising a first conductive path through a first portion of the semiconductor fin and a second conductive path through a second portion of the semiconductor fin.

25. The method of claim 24, wherein the first and second conductive paths comprise the same distance through the bottom doped region.

Background

The present invention relates generally to fabrication methods for semiconductor devices and resulting structures. More particularly, the present invention relates to embedded bottom metal contacts formed by a self-aligned (SAC) process for Vertical Field Effect Transistors (VFETs).

In contemporary semiconductor device manufacturing processes, a large number of semiconductor devices, such as Field Effect Transistors (FETs), are manufactured on a single wafer. Some non-planar transistor architectures, such as VFETs, employ semiconductor fins and side gates that can be contacted outside the active region, resulting in increased device density and improved performance compared to lateral devices. In VFET, the drain current source flows in a direction perpendicular to the main surface of the substrate. For example, in known VFET configurations, the main substrate surface is horizontal and the vertical fins or nanowires extend upward from the substrate surface. The fin or nanowire forms the channel region of the transistor. Source and drain regions are in electrical contact with the top and bottom ends of the channel region, and a gate is disposed on one or more of the fin or nanowire sidewalls.

Disclosure of Invention

Embodiments of the present invention relate to a method for manufacturing a semiconductor device. A non-limiting example of the method includes forming a semiconductor fin on a doped region of a substrate. A portion of the doped region adjacent to the semiconductor fin is recessed and an embedded contact is formed on the recessed portion. The material of the embedded contact is selected such that the conductivity of the embedded contact is higher than the conductivity of the doped region.

Embodiments of the present invention relate to a method for manufacturing a semiconductor device. A non-limiting example of the method includes forming a semiconductor fin on a doped region of a substrate. A conductive gate is formed over a channel region of the semiconductor fin. A portion of the doped region adjacent to the semiconductor fin is recessed, and a conductive track is formed on the recessed portion. A dielectric layer is formed between the conductive tracks and the conductive gate. A first conductive contact is formed on a surface of the conductive track and a second conductive contact is formed on a surface of the semiconductor fin. The material of the conductive tracks is chosen such that the electrical conductivity of the embedded contacts is higher than the electrical conductivity of the doped regions.

Embodiments of the invention relate to a semiconductor device. Non-limiting examples of semiconductor devices include semiconductor fins formed on a substrate. Embedded bottom contacts formed on recessed portions of the doped regions along three sides of the semiconductor fin. The material of the embedded bottom contact is selected such that the conductivity of the embedded bottom contact is higher than the conductivity of the doped region.

Embodiments of the invention relate to a semiconductor device. Non-limiting examples of semiconductor devices include: a semiconductor fin formed on a substrate; a conductive gate formed over a channel region of the semiconductor fin; forming a bottom spacer between the conductive gate and the doped region; a conductive track formed on the recessed portion of the doped region; and a dielectric layer formed between the conductive track and the conductive gate; forming a first conductive contact on a surface of a conductive track; forming a second conductive contact on a surface of the semiconductor fin; the material of the conductive track is chosen such that the conductivity of the conductive track is higher than the conductivity of the doped region.

Embodiments of the present invention relate to a method for operating a semiconductor device. A non-limiting example of the method includes providing a semiconductor device. The device includes a semiconductor fin formed on a bottom doped region of a substrate. A conductive gate formed over a channel region of the semiconductor fin. A top doped region formed on a surface of the semiconductor fin, and a top source/drain contact formed on a surface of the top doped region. A conductive track is formed on the recessed portion of the doped region and a bottom S/D contact is formed on the surface of the conductive track. The current passes from the top S/D contact to the bottom S/D contact through a portion of the conductive track.

Other technical features and benefits are realized through the techniques of the present invention. Embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, refer to the detailed description and to the drawings.

Drawings

The details of the exclusive rights herein are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of embodiments of the invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 depicts a cross-sectional view of a semiconductor structure after a processing operation in accordance with one or more embodiments of the present invention;

FIG. 2 depicts a cross-sectional view of a semiconductor structure after a processing operation in accordance with one or more embodiments of the present invention;

FIG. 3 depicts a cross-sectional view of a semiconductor structure after a processing operation in accordance with one or more embodiments of the present invention;

FIG. 4 depicts a cross-sectional view of a semiconductor structure after a processing operation in accordance with one or more embodiments of the present invention;

FIG. 5 depicts a cross-sectional view of a semiconductor structure after a processing operation in accordance with one or more embodiments of the invention;

FIG. 6 depicts a cross-sectional view of a semiconductor structure after a processing operation in accordance with one or more embodiments of the invention;

FIG. 7 depicts a cross-sectional view of a semiconductor structure after a processing operation in accordance with one or more embodiments of the invention;

FIG. 8 depicts a cross-sectional view of a semiconductor structure after a processing operation in accordance with one or more embodiments of the invention;

FIG. 9 depicts a cross-sectional view of a semiconductor structure after a processing operation in accordance with one or more embodiments of the invention;

FIG. 10 depicts a cross-sectional view of a semiconductor structure after a processing operation in accordance with one or more embodiments of the invention;

FIG. 11 depicts a cross-sectional view of a semiconductor structure after a processing operation in accordance with one or more embodiments of the invention; and

FIG. 12 depicts a flow diagram showing a method in accordance with one or more embodiments of the invention.

The drawings described herein are illustrative. Many changes may be made to the drawings or to the operations described therein without departing from the spirit of the invention. For instance, the acts may be performed in a differing order, or acts may be added, deleted or modified.

In the drawings and the following detailed description of embodiments of the invention, various elements shown in the drawings have reference numerals with two or three digits. With a few exceptions, the left-most digit of each reference number corresponds to the figure in which the element is first shown.

Detailed Description

For the sake of brevity, conventional techniques related to semiconductor device and Integrated Circuit (IC) fabrication may or may not be described in detail herein. In addition, various tasks and processing steps described herein may be incorporated into a more comprehensive procedure or process having additional steps or functions not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, and thus, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well known process details.

Turning now to an overview of the technology more particularly relevant to various aspects of the present invention, as previously described, some non-planar transistor device architectures, such as VFETs, employ semiconductor fins and side gates that can be contacted outside the active area, resulting in increased device density on the lateral devices. However, there are challenges beyond scaling VFETs to the 10nm node. For example, the aggressive scaling of VFET architectures imposes practical limitations on the minimum resistance and uniformity of current through the bottom source/drain (S/D). In particular, current through a conventional VFET travels along a variable length path through the bottom S/D before reaching the channel. The shortest distance path, i.e., the path through the edge of the fin closest to the bottom S/D contact, is highly preferred because the current travels along the path of least resistance. Thus, activating the VFET preferentially utilizes a portion of the channel at the edge of the fin closest to the bottom S/D contact. The distal portion of the channel away from the bottom S/D contact is rarely utilized and, therefore, device performance suffers.

Further, in VFETs, contacts are formed near (i.e., adjacent to) the gate to the bottom S/D. This configuration, in combination with the reduced footprint (footing) of the VFET, results in a large parasitic capacitance between the gate and the bottom S/D contact. The parasitic capacitance between two conductors (also referred to as conductor-to-conductor capacitance) is a function of the length and thickness of the conductors and the distance separating the conductors. Parasitic capacitances can lead to undesirable device effects such as resistance-capacitance (RC) delay, power consumption, and crosstalk. RC delay refers to the delay in the speed or propagation of a signal passing through a circuit as a function of the product of the resistance and capacitance of the circuit element. Unfortunately, as device dimensions and component pitches shrink to meet the ever-increasing demand for smaller electronic devices, parasitic capacitances continue to increase. Conventional methods of reducing the parasitic capacitance between the gate and the bottom S/D contact have not been completely successful. For example, in a conventional VFET, the bottom S/D contact may be further formed from the gate to mitigate this parasitic capacitance somewhat. However, doing so represents an area penalty that severely limits the overall scaling factor of the VFET architecture.

Turning now to an overview of various aspects of the present invention, one or more embodiments of the present invention provide methods and structures configured to reduce bottom S/D resistance and improve current uniformity in a VFET. A highly conductive (e.g., metal) buried contact rail is formed adjacent the bottom S/D along the entire channel of the vertical fin. The buried tracks are in ohmic contact with the bottom S/D and bottom S/D contacts and are positioned so that all circuits passing through the bottom S/D travel an equal distance before reaching the buried tracks. In this way, the effective resistance of the bottom S/D is greatly reduced and current uniformity is improved. Also, the buried contact rails may be embedded in a dielectric layer. The embedded contact rails advantageously allow for a reduction in bottom S/D resistance without increasing bottom S/D to gate parasitic capacitance.

Turning now to a more detailed description of aspects of the invention, fig. 1 depicts a cross-sectional view of a simplified conventional VFET structure 100 having a vertical semiconductor fin 102 formed between a bottom S/D region 104 and a top S/D region 106. A conductive gate 108 is formed over the channel region of the fin 102. A bottom S/D contact 110 and a gate contact 112 are also provided. As previously described, the current preferentially travels along the least resistive conductive path. Thus, in a conventional VFET 100, the current 114 preferably travels the shortest path through the resistive bottom S/D region 104. Thus, a majority of the current 114 passes through the edge region 116 of the fin 102 closest to the bottom S/D contact 110, and the remote region 118 of the fin 102 is rarely utilized.

Figure 2 depicts a cross-sectional view of a structure 200 having a vertical semiconductor fin 202 formed over a bottom doped region 204 of a substrate 206 during an intermediate operation of a method of fabricating a semiconductor device in accordance with one or more embodiments of the present invention. Vertical semiconductor fins 202 (hereinafter fins 202) may be formed on substrate 206 using known front end of line (FEOL) VFET fabrication techniques. For example, in some embodiments of the present invention, hard mask 208 is patterned to expose portions of substrate 206. The exposed portions of the substrate 206 may then be removed using an etching process, which may be a wet etching process, a dry etching process, or a combination thereof, to form a plurality of vertical semiconductor fins. Each fin 202 may have a height of 1nm to 150 nm. Each fin 202 may have a width of 5nm to 40 nm. Adjacent fins 202 may be separated by a pitch of 10nm to 100 nm.

Substrate 206 can be any suitable substrate material, such as single crystal silicon, SiGe, SiC, III-V compound semiconductors, II-VI compound semiconductors, or semiconductor-on-insulator (SOI). In some embodiments, substrate 206 includes a buried oxide layer (not shown). The fins 202 may be electrically isolated from other regions of the substrate 206 by shallow trench isolation (not shown). The shallow trench isolation may be any suitable dielectric material, such as silicon oxide.

The bottom doped region 204 may be a source or drain region formed on the substrate 206 by various methods. In some embodiments of the present invention, the bottom doped region 204 is formed by selective epitaxial growth on the substrate 206. The bottom doped region 204 may comprise an epitaxial semiconductor material grown from a gaseous or liquid precursor. For example, epitaxial semiconductor materials may be grown using Vapor Phase Epitaxy (VPE), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), or other suitable processes.

In some embodiments of the present invention, the gas source used for depositing the epitaxial semiconductor material comprises a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, the epitaxial Si layer may be deposited from a silicon gas source selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane, and combinations thereof. The epitaxial germanium layer may be deposited from a germanium gas source selected from the group consisting of germane, digermane, halo germane, dichloro germane, trichlorogermane, tetrachlorogermane, and combinations thereof. Combinations of these gas sources may be utilized to form the epitaxial sige alloy layer. Carrier gases such as hydrogen, nitrogen, helium and argon may be used.

Epitaxial silicon, silicon germanium (SiGe) and/or carbon doped silicon (Si: C) can be doped during deposition (in-situ doping) or after epitaxy by adding n-type dopants (e.g., As, P, Sb) or P-type dopants (e.g., Ga, B, BF2, Al), depending on the type of transistor (i.e., n-type dopants for nfets and P-type dopants for pfets). The dopant concentration may be 1 × 10¹⁹cm^-3To 2X 10²¹cm^-3Or 1X 10²⁰cm^-3To 1X 10²¹cm^-3。

A conductive gate 210 is formed over the channel region of fin 202 using a known VFET process. In some embodiments of the present invention, the conductive gate 210 is overfilled above the surface of the fin 202 and then recessed below the surface of the semiconductor fin 202 using, for example, a wet or dry etch.

The conductive gate 210 may be a high-k metal gate (HKMG) and may include, for example, one or more high-k dielectric films 212 and one or more work function metals (WFM, not shown). The one or more high-k dielectric films 212 can be a dielectric material with a dielectric constant greater than, for example, 3.9, 7.0, or 10.0. Non-limiting examples of suitable materials for the high-k dielectric film 212 include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k materials having a dielectric constant greater than 7.0 include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, scandium lead strontium oxide, and lead zinc niobate. The high-k dielectric film 212 may also include dopants such as lanthanum and aluminum. The high-k dielectric film 212 may be formed by a suitable deposition process, such as CVD, plasma enhanced CVD (pecvd), ALD, evaporation, PVD, chemical solution deposition, or other similar processes. The thickness of the high-k dielectric film 212 may vary depending on the deposition process and the composition and amount of high-k dielectric material used. The thickness of the high-k dielectric film 212 is in the range of about 0.5 to about 20 nm.

WFM may be disposed on the high-k dielectric film 212. The type of workfunction metal depends on the type of transistor and may vary between nFET and pFET devices. P-type work function metals include compositions such as ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, or any combination thereof. N-type workfunction metals include metals such as hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminides, or any combination thereof. The WFM may be deposited by a suitable deposition process, for example, CVD, PECVD, PVD, electroplating, thermal or e-beam evaporation and sputtering.

Bulk material for the conductive gate 210 (gate conductor material) may be deposited on the high-k dielectric film 212 and WFM to form HKMG. Non-limiting examples of suitable conductive materials include aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The gate conductor material may be deposited by a suitable deposition process, such as CVD, PECVD, PVD, electroplating, thermal or e-beam evaporation and sputtering.

A bottom spacer 214 is formed between the conductive gate 210 and the substrate 206. The bottom spacer 214 may comprise a dielectric material, such as SiN, SiC, SiOC, SiCN, BN, SiBN, SiBCN, SiOCN, SiO_xN_yAnd combinations thereof. The dielectric material may be a low-k material having a dielectric constant of less than about 7, less than about 5, or even less than about 2.5. Bottom spacers 214 may be formed using known deposition processes, such as CVD, PECVD, ALD, PVD, chemical solution deposition, or other similar processes. In some embodiments of the present invention, the bottom spacers 214 are formed by performing a directional deposition process, such as a Gas Cluster Ion Beam (GCIB) process. The GCIB process isA deposition process may be highly directional in nature. For example, a directional deposition process may result in the deposition of a dielectric material on horizontally oriented surfaces of the device (e.g., the surfaces of the bottom doped regions 204) while avoiding any substantial deposition of dielectric material on vertically oriented surfaces of the device (e.g., the sidewalls of the fins 202).

Top spacers 216 are formed over conductive gate 210 and bottom spacers 214. The top spacers 216 may be formed in a similar manner as the bottom spacers 214 and may include a dielectric material, such as SiN, SiC, SiOC, SiCN, BN, SiBN, SiBCN, SiOCN, SiOxNy, and combinations thereof.

An interlayer dielectric (ILD)218 is formed over the bottom spacer 214 and the conductive gate 210. ILD218 may be any suitable dielectric material, such as silicon oxide, and may be formed using any suitable process. In some embodiments of the present invention, ILD218 is planarized to the surface of the top spacers (not shown) using, for example, CMP. The trenches 220 are formed by removing portions of the ILD218 using, for example, a wet etch, a dry etch, or a combination thereof. The trench 220 exposes a surface of the hard mask 208.

Fig. 3 depicts a cross-sectional view of the structure 200 after a top doped region 300 is formed on the surface of the fin 202 during an intermediate operation of a method of fabricating a semiconductor device in accordance with one or more embodiments of the present invention. In some embodiments of the present invention, after the hard mask 208 is removed, a top doped region 300 is epitaxially grown on the surface of the fin 202. Portions of hard mask 208 in trenches 220 may be removed using, for example, wet etching, dry etching, or a combination thereof to expose the surface of fins 202. A top doped region 300 may then be formed on the exposed surface of the fin 202.

The top doped region 300 may be a source or drain region that is epitaxially grown in a similar manner as the bottom doped region 204. For example, VPE, MBE or LPE may be used to grow epitaxial material from gaseous or liquid precursors. Depending on the type of transistor, the top doped region 300 may be doped during deposition (in-situ doping) by adding a dopant, either an n-type dopant (e.g., phosphorus or arsenic) or a p-type dopant (e.g., boron or gallium). Concentration of dopantThe degree may be about 1 × 10¹⁹cm^-3To about 2X 10²¹cm^-3E.g. about 2X 10²⁰cm^-3To about 1X 10²¹cm^-3。

Figure 4 depicts a cross-sectional view of the structure 200 after the ILD218 is refilled on the surface of the top doped region 300 during an intermediate operation of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. ILD218 may be refilled with the same dielectric material as used in the initial ILD218 deposition or a different dielectric material (as shown in fig. 2). In some embodiments of the present invention, ILD218 is planarized using, for example, CMP.

Fig. 5 depicts a cross-sectional view of the structure 200 after forming a trench 500 exposing a portion of the bottom doped region 204 during an intermediate operation of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. The trench 500 surrounds the fin 202 on three sides and may be formed using, for example, wet etching, dry etching, or a combination thereof. In some embodiments of the present invention, a series of RIE etches are used to expose portions of the bottom doped region 204. For example, a first RIE may remove portions of ILD 118 selective to top spacers 216 to form trenches 500. In this manner, trench 500 may be formed self-aligned to top spacer 216. The second RIE may remove portions of top spacers 216 in trench 500. The third RIE may remove bottom spacers 214 in trenches 500 selective to bottom doped regions 204.

Fig. 6 depicts a cross-sectional view of the structure 200 after recessing a portion of the bottom doped region 204 in the trench 500 during an intermediate operation of a method of manufacturing a semiconductor device in accordance with one or more embodiments of the present invention. The bottom doped region 204 may be recessed using, for example, wet etching, dry etching, or a combination thereof. In some embodiments of the present invention, the bottom doped region 204 is recessed by about 10 to about 15nm, although other recess depths are within the contemplated scope of the present invention. The bottom doped region 204 is recessed so that the conductive tracks 800 can be buried under the dielectric layer (as shown in fig. 9).

Fig. 7 depicts a cross-sectional view of the structure 200 after forming a conductive layer 700 over the bottom doped region 204 and sidewalls of the trench 500 during an intermediate operation of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. The conductive layer 700 may be made of any suitable conductive material, such as a metal (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold), a conductive metal compound material (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, aluminum carbide, tungsten silicide, tungsten nitride, ruthenium oxide, cobalt silicide, nickel silicide), carbon nanotubes, conductive carbon, graphene, or any suitable combination of these materials. The material of the conductive layer 700 is selected such that the conductivity of the conductive track 800 (as shown in fig. 8) is much higher (e.g., more than twice) than the conductivity of the bottom doped region 204.

Conductive layer 700 can be conformally formed using, for example, CVD, PECVD, ALD, PVD, chemical solution deposition, or other similar process. In some embodiments of the present invention, conductive layer 700 is Ti formed using PVD. PVD deposition advantageously deposits a thicker layer (e.g., about 10 to about 15nm) at the bottom of the trench 500 and a thin layer (e.g., less than about 2nm) on the sidewalls of the trench 500.

Fig. 8 depicts a cross-sectional view of the structure 200 after recessing the conductive layer 700 from the sidewalls of the trench 500 during an intermediate operation of a method of manufacturing a semiconductor device in accordance with one or more embodiments of the present invention. Conductive layer 700 may be recessed using, for example, wet etching, dry etching, or a combination thereof. In some embodiments of the invention, SC1 (H) is used₂O₂/NH₄OH) causes the conductive layer 700 to recess. The removal process exposes the sidewalls of top spacers 216 and recessed portions of conductive layer 700 at the bottom of trench 500. In some embodiments of the present invention, the remaining portion of conductive layer 700 at the bottom of trench 500 is recessed about 3nm to about 5nm below the surface of bottom spacers 214. These remaining portions of the conductive layer 700 define conductive tracks 800 (also referred to as buried or embedded bottom contacts) that wrap around three sides of the fins 202. The conductive tracks 800 may have a thickness of about 7 to about 12nm, although other thicknesses are within the contemplated scope of the present invention.

Fig. 9 depicts a cross-sectional view of the structure 200 after filling the trenches 500 with a dielectric material during an intermediate operation of a method of manufacturing a semiconductor device according to one or more embodiments of the invention. The trenches 500 may be filled with the same dielectric material as used in the initial ILD218 deposition (as shown in fig. 2) or a different dielectric material. In some embodiments of the present invention, ILD218 is planarized using, for example, CMP.

Fig. 10 depicts a cross-sectional view of the structure 200 after forming a trench 1000 exposing a surface of the top doped region 300 during an intermediate operation of a method of fabricating a semiconductor device according to one or more embodiments of the present invention. Trenches 1002 are also formed exposing the surface 1100 of conductive traces 800 (as shown in fig. 11). ILD218 may be patterned using, for example, a wet etch, a dry etch, or a combination thereof.

The trenches 1000 and 1002 are then filled with conductive contacts (not shown) using known VFET metallization techniques. For example, in some embodiments of the present invention, ILD218 is extended and contacts are deposited into trenches 1000 and 1002. In some embodiments of the present invention, the contacts are overfilled into the trenches, forming a blanket layer over the surface of ILD 218. CMP may be used to remove the capping layer.

The contacts may be made of any suitable conductive material, such as a metal (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold), a conductive metal composite (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, aluminum carbide, tungsten silicide, tungsten nitride, ruthenium oxide, cobalt silicide, nickel silicide), carbon nanotubes, conductive carbon, graphene, or a suitable combination of these materials. The conductive material may also include dopants that are incorporated during or after deposition. In some embodiments of the invention, the contacts may be copper or tungsten, and may include a barrier metal liner (not shown). The barrier metal liner prevents copper or tungsten from diffusing or doping into the surrounding material, which can degrade its performance. For example, silicon forms deep traps when doped with copper. The ideal barrier metal liner must be sufficiently diffusive to confine the bulk metal to chemically isolate the conductor from the surrounding materials, and should be highly conductive, e.g., tantalum nitride, titanium nitride, cobalt, ruthenium, manganese, or titanium carbide.

In some embodiments of the present invention, the contact includes a metal (e.g., titanium) that reacts with the semiconductor material (e.g., the top doped region 300) to form a silicide film (not shown) between the top doped region 300 and the contact. Since the silicide film is formed only at the interface between the contact and the top doped region 300, the silicide film can be said to be self-aligned to the top doped region 300 (self-aligned silicide is also referred to as salicide).

Fig. 11 depicts a cross-sectional view of a structure 200 having a conductive path 1102 (also referred to as an electrical path or channel path) during an ON state in accordance with one or more embodiments of the present invention. Fig. 11 shows another view of the structure 200 as shown in fig. 10, except that it is a cross-sectional view of the structure 200 taken along the edge of the trench 1002. As can be clearly seen from this view, the trench 1002 exposes a surface of the conductive track 800.

A conductive path 1102 begins at the top doped region 300, passes through the channel region of the fin 202, and passes through the bottom doped region 204 to the conductive track 800. As previously described, the conductive traces 800 use a conductive material (e.g., from a metal) having a higher conductivity than the bottom doped regions 204. Thus, current passing through the fins 202 to the conductive tracks 800 will preferentially travel through the shortest available path of the bottom doped region 204. The shortest available path through the bottom doped region 204 along the length of the entire channel is constant and is the linear distance between the fin 202 and the conductive track 800. In other words, all electrical paths are equidistant through the bottom doped region 204 before reaching the conductive track 800. In this manner, the effective resistance of the bottom doped region 204 is reduced and the uniformity of the current through the bottom doped region 204 is improved.

Fig. 12 depicts a flow diagram 1200 of a method for forming a semiconductor device in accordance with one or more embodiments of the present invention. A semiconductor fin is formed on a doped region of a substrate, as shown in block 1202. In accordance with one or more embodiments, the semiconductor fins can be formed in a similar manner as fins 202 shown in fig. 2.

A portion of the doped region adjacent to the semiconductor fin is recessed, as shown in block 1204. In accordance with one or more embodiments, the doped regions may be recessed in a similar manner as the bottom doped regions 204 depicted in fig. 6.

As shown in block 1206, an embedded contact is formed on the recessed portion of the doped region. In accordance with one or more embodiments, the embedded contacts may be formed in a similar manner to the conductive tracks 800 shown in fig. 7 and 8. As previously discussed herein, the material of the recessed contact is selected such that the conductivity of the recessed contact is higher than the conductivity of the doped region of the substrate.

Various embodiments of the present invention are described herein with reference to the accompanying drawings. Alternate embodiments may be devised without departing from the scope of the invention. Although various connections and positional relationships (e.g., above, below, adjacent, etc.) are set forth between elements in the following description and drawings, those skilled in the art will recognize that many of the positional relationships described herein are directionally independent-even if the direction changes, the function described is preserved. These connections and/or positional relationships may be direct or indirect unless otherwise specified, and the invention is not intended to be limited in this respect. Similarly, the term "coupled" and variations thereof describe having a communication path between two elements and does not imply a direct connection between the elements nor an intervening element/connection therebetween. All such variations are considered a part of the specification. Thus, the coupling of entities may refer to direct or indirect coupling, and the positional relationship between entities may be a direct or indirect positional relationship. As an example of an indirect positional relationship, references in this specification to forming layer "a" on layer "B" include the case where one or more intervening layers (e.g., layer "C") are between layer "a" and layer "B" so long as the relevant properties and functions of layer "a" and layer "B" are not substantially changed by the intervening layers.

The following definitions and abbreviations are used to interpret the claims and the specification. As used herein, the terms "comprises," "comprising," "includes" and "including," when used in this specification, are intended to cover a non-exclusive inclusion, such that "includes" when used, includes "including" when used, includes "when used, has" when used, includes "when used, or includes any other variation thereof. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

Additionally, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" should be understood to include any integer greater than or equal to 1, i.e., one, two, three, four, etc. The term "plurality" should be understood to include any integer number greater than or equal to 2, i.e., two, three, four, five, etc. The term "coupled" can include both indirect "coupled" and direct "coupled".

References in the specification to "one embodiment," "an example embodiment," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

For purposes of the following description, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof shall relate to the described structures and methods as illustrated in the drawing figures. The terms "overlying," "atop," "top," "positioned at" or "positioned at top" mean that a first element (e.g., a first structure) is present on a second element (e.g., a second structure), where intermediate elements, such as interface structures, may be present between the first and second elements. The term "directly contacting" means that a first element (e.g., a first structure) and a second element (e.g., a second structure) are connected without any intervening conductive, insulating, or semiconductive layer at the interface of the two elements.

The terms "about," "substantially," "about," and variations thereof are intended to encompass the degree of error associated with measuring a particular quantity based on the available equipment at the time of filing the application. For example, "about" may include a range of ± 8% or 5%, or 2% of a given value.

The phrase "selective to … …," such as "a first element selective to a second element," means that the first element can be etched and the second element can act as an etch stop.

The term "conformal" (e.g., a conformal layer) means that the thickness of the layer is substantially the same across all surfaces, or varies by less than 15% of the nominal thickness of the layer.

The terms "epitaxial growth and/or deposition" and "epitaxial formation and/or growth" refer to the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material), wherein the grown other semiconductor material (crystalline overlayer) has substantially the same crystalline characteristics as the semiconductor material (seed material) of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gases may be controlled and system parameters may be set such that the deposition atoms reach the deposition surface of the semiconductor substrate with sufficient energy to move over the surface such that the deposition atoms orient themselves to the crystalline arrangement of deposition surface atoms. The epitaxially grown semiconductor material may have substantially the same crystalline characteristics as the deposition surface on which the epitaxially grown material is formed. For example, an epitaxially grown semiconductor material deposited on a {100} oriented crystalline surface may exhibit a {100} orientation. In some embodiments of the present invention, epitaxial growth and/or deposition processes may be selectively formed on semiconductor surfaces and may not deposit material on exposed surfaces (e.g., silicon dioxide or silicon nitride surfaces).

As previously mentioned, conventional techniques related to semiconductor device and Integrated Circuit (IC) fabrication may or may not be described in detail herein for the sake of brevity. By way of background, however, a more general description of a semiconductor device fabrication process that may be used to implement one or more embodiments of the present invention will now be provided. While certain manufacturing operations for carrying out one or more embodiments of the invention may be known individually, combinations of the described operations of the invention and/or the resulting structures are unique. Thus, the unique combination of operations described in connection with the fabrication of semiconductor devices in accordance with the present invention utilize various separately known physical and chemical processes performed on semiconductor (e.g., silicon) substrates, some of which are described in the immediately following paragraphs.

Generally, the various processes used to form microchips to be packaged into ICs fall into four broad categories, namely film deposition, removal/etching, semiconductor doping and patterning/photolithography. Deposition is any process of growing, coating, or otherwise transferring material onto a wafer. Useful techniques include Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), electrochemical deposition (ECD), Molecular Beam Epitaxy (MBE), and more recently Atomic Layer Deposition (ALD), among others. Removal/etching is any process that removes material from a wafer. Examples include etching processes (wet or dry), Chemical Mechanical Planarization (CMP), and the like. For example, Reactive Ion Etching (RIE) is a type of dry etching that uses a chemically reactive plasma to remove material, such as a mask pattern of semiconductor material, by exposing the material to a bombardment of ions that causes portions of the ions to be removed from the exposed surface. Plasma is typically generated at low pressure (vacuum) by an electromagnetic field. Semiconductor doping is the changing of electrical properties by doping (e.g., transistor source and drain), typically by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or Rapid Thermal Annealing (RTA). Annealing serves to activate the implanted dopants. Two films of conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of a semiconductor substrate allows the conductivity of the substrate to be altered by application of a voltage. By creating a structure of these various components, millions of transistors can be built and connected together to form the complex circuitry of modern microelectronic devices. Semiconductor lithography is the formation of a three-dimensional relief image or pattern on a semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, a pattern is formed from a photosensitive polymer called a photoresist. The photolithography and etch pattern transfer steps are repeated multiple times in order to build many wires that make up the complex structure of transistors and connect the millions of transistors of a circuit. Each pattern printed on the wafer is aligned with a previously formed pattern and the conductor, insulator and selectively doped regions are slowly built up to form the final device.

The flowchart and block diagrams in the figures illustrate possible implementations of methods of manufacture and/or operation according to various embodiments of the present invention. Various functions/operations of the method are represented by blocks in the flowchart. In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.

Having described embodiments of the present invention, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein were chosen in order to best explain the principles of the embodiments, the practical application, or technical improvements to the techniques in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.