阅读说明：本技术 多级多尔蒂功率放大器和发射机 (Multi-stage doherty power amplifier and transmitter ) 是由 王占仓 于 2017-07-21 设计创作，主要内容包括：提供了多级多尔蒂(Doherty)功率放大器和发射机,并且多级多尔蒂功率放大器包括：通用载波放大器(201),其是嵌套的两路反相多尔蒂子放大器；连接到通用载波放大器(201)的通用峰值放大器(202),其是嵌套的单端子放大器或嵌套的两路普通多尔蒂子放大器；通用载波放大器(201)和通用峰值放大器(202)以通用两路反相多尔蒂功率放大器的形式布置。在实施例中,应用了面向经济高效的多级多尔蒂PA设计的信号功率概率分布函数(PDF),并且将两路普通和反相多尔蒂PA单元用作基本单元来构造具有增益扩展效果的多级多尔蒂PA。(A multi-stage Doherty power amplifier and a transmitter are provided, and the multi-stage Doherty power amplifier includes: a general carrier amplifier (201) which is a nested two-way inverting doherty sub-amplifier; a general peak amplifier (202) connected to the general carrier amplifier (201), which is a nested single-terminal amplifier or a nested two-way general doherty amplifier; the general carrier amplifier (201) and the general peak amplifier (202) are arranged in the form of a general two-way inverting doherty power amplifier. In an embodiment, a signal power Probability Distribution Function (PDF) designed for a cost-efficient multi-stage doherty PA is applied, and a multi-stage doherty PA with gain expansion effect is constructed using two normal and inverted doherty PA units as basic units.)

1. A multi-stage doherty power amplifier (200) comprising:

a general carrier amplifier (201) which is a nested two-way inverting doherty sub-amplifier, an

A general peak amplifier (202) connected to a general carrier amplifier (201), which is a nested single-terminal amplifier or a nested two-way general doherty amplifier,

wherein the common carrier amplifier (201) and the common peaking amplifier (202) are arranged in the form of a two-way inverting doherty power amplifier.

2. The multi-stage doherty power amplifier of claim 1 wherein the common carrier amplifier (201) comprises a subcarrier amplifier and a first sub-peaking amplifier connected to the subcarrier amplifier.

3. The multi-stage doherty power amplifier of claim 2 wherein the subcarrier amplifier has a first semiconductor characteristic and the first sub-peak amplifier has a second semiconductor characteristic with harmonic termination.

4. The multi-stage doherty power amplifier of claim 3 wherein the amplifier efficiency of the first sub-peaking amplifier is higher than the amplifier efficiency of the subcarrier amplifier.

5. The multi-stage doherty power amplifier of claim 4 wherein the common peaking amplifier (202) comprises a second sub-peaking amplifier having the first semiconductor feature.

6. The multi-stage doherty power amplifier of claim 5 wherein the bias voltage values of the subcarrier amplifiers and sub-second peaking amplifiers are positive and the bias voltage value of the first sub-peaking amplifier is negative.

7. The multi-stage doherty power amplifier of claim 5 wherein power ratios among the subcarrier amplifiers, the first sub-peaking amplifier and the second sub-peaking amplifier are determined according to a Power Distribution Function (PDF) of an applied high peak-to-average power ratio (PAPR) signal.

8. The multi-stage doherty power amplifier of claim 5 wherein the first semiconductor feature is an LDMOS and the second semiconductor feature is a GaN HEMT.

9. The multi-stage doherty power amplifier of claim 3 wherein the power gain of the first sub-peaking amplifier is greater than the power gain of the subcarrier amplifier for power gain expansion, the power gain of the subcarrier amplifier is compressed to a predetermined compression level, and the power gain of the first peaking amplifier is uncompressed.

10. The multi-stage doherty power amplifier of claim 9, wherein the characteristic of the power gain expansion is an inverse characteristic of a driver amplifier connected to the multi-stage doherty power amplifier in a queue or cascade manner so as to perform predistortion on the driver amplifier.

11. The multi-stage doherty power amplifier of claim 4 wherein the common peaking amplifier (202) includes a plurality of sub-peaking amplifiers, a final stage sub-peaking amplifier has a first semiconductor characteristic, other stages of sub-peaking amplifiers than the final stage sub-peaking amplifier have a second semiconductor characteristic, and amplifier efficiencies of the other stages of sub-peaking amplifiers than the final stage sub-peaking amplifier are higher than the amplifier efficiency of the final stage sub-peaking amplifier.

12. The multi-stage doherty power amplifier of claim 11, wherein bias voltage values of the subcarrier amplifier and the final stage sub-peaking amplifier are positive, and bias voltage values of the first sub-peaking amplifier and other stages of sub-peaking amplifiers than the final stage sub-peaking amplifier are negative.

13. The multi-stage doherty power amplifier of claim 11 wherein power ratios among the subcarrier amplifier, the first sub-peaking amplifier and the plurality of sub-peaking amplifiers are determined according to a Power Distribution Function (PDF) of an applied high peak-to-average power ratio (PAPR) signal.

14. The multi-stage doherty power amplifier of claim 11 wherein the first semiconductor feature is an LDMOS and the second semiconductor feature is a GaN HEMT.

15. The multi-stage doherty power amplifier of claim 11, wherein power gains of sub-peak amplifiers of other stages than the final sub-peak amplifier are higher than that of the first sub-peak amplifier for power gain expansion; the power gain of each sub-peak amplifier in the other sub-peak amplifiers except the final sub-peak amplifier is higher than that of the previous sub-peak amplifier for power gain expansion; the power gain of the sub-carrier amplifier is compressed to a predetermined compression level, and the power gains of the sub-peak amplifiers of the other stages than the final sub-peak amplifier are not compressed.

16. The multi-stage doherty power amplifier of claim 15 wherein the characteristic of the power gain expansion is an inverse characteristic of a driver amplifier connected to the multi-stage doherty power amplifier in a queue or cascade manner so as to perform predistortion on the driver amplifier.

17. The multi-stage doherty power amplifier of claim 11 wherein the common peaking amplifier (202) includes 3 sub-peaking amplifiers to form a four-stage doherty power amplifier.

18. A transmitter, comprising:

a signal processor configured to perform signal processing on baseband input signals of a plurality of channels;

the multi-stage doherty power amplifier according to any of claims 1-17.

19. An apparatus, comprising:

a processor (1710);

a memory (1720), the memory (1720) containing a program (1740), the program (1740) comprising instructions executable by the processor (1710), an

The transmitter of claim 18.

20. The device of claim 19, wherein the device is a terminal device or a network device.

Technical Field

Embodiments of the present disclosure relate generally to the field of communications, and more particularly, to a multi-stage doherty power amplifier and transmitter.

Background

In cellular base stations of fourth generation (4G) and higher versions of mobile communication systems, advanced digital modulation schemes are used for high spectral efficiency. A Radio Frequency (RF) signal, which is amplified at a Power Amplifier (PA), exhibits a large peak-to-average power ratio (PAPR). Therefore, the magnitude of the instantaneous transmit power will vary greatly. As such, conventional RF PAs can be quite inefficient on average under high PAPR stimulation.

One way to increase the efficiency of an RF PA is to use a doherty power amplifier (doherty PA). The classic doherty PA or the normal doherty PA in this disclosure is used to enhance the efficiency of high PAPR signals, which results in a second efficiency peak point 6dB away from the peak output power during backoff. However, as PAPR increases, the main challenge of doherty PA is to maintain high efficiency with limited doherty area with PAPR greater than 6 dB.

This section introduces aspects that may help to better understand the present disclosure. Accordingly, the statements of this section are to be read in this light and are not to be construed as admissions of prior art material or non-prior art material.

Disclosure of Invention

The inventors have found that the doherty concept has been extended to multi-stage (i.e., more than two-stage) variants. This allows for maintaining high efficiency over a wide range of output power levels for varying amplitude distributions. At the same time, the average efficiency for a particular amplitude profile and a particular power level may be increased.

However, two problems have been identified in connection with multi-stage doherty PAs: the problem of low efficiency (if gain limited amplifiers (transistors) are used) and the problem of poor linearity. The inefficiency is caused by excessive drive power consumption, which is necessary if a conventional multi-stage doherty PA implementation is used, to ensure high linearity of the driver stage. This problem is particularly pronounced if the power amplifier gain in the doherty PA is low. Poor linearity is due to the fact that: in a conventional multi-stage doherty PA, some amplifiers (all but the two top-stage power amplifiers) are required to saturate at certain transition points and remain saturated at these transition points.

To address at least some of the above issues, a multi-stage doherty PA and transmitter are provided in the present disclosure. It will be appreciated that embodiments of the present disclosure are not limited to multiple-input multiple-output (MIMO) transmitter systems, but may be applied more broadly to any application scenario where similar issues exist.

Various embodiments of the present disclosure are generally directed to providing a multi-stage doherty PA and transmitter, for example, in a MIMO transmitter system. The transmitter may be, for example, a terminal device or a network device. Other features and advantages of embodiments of the present disclosure will also be appreciated when the following description of the specific embodiments is read in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the embodiments of the disclosure.

In general, embodiments of the present disclosure provide a concept of nested multistage doherty PAs to overcome the problems noted in the above description.

In a first aspect, a multi-stage doherty power amplifier is provided. The multi-stage doherty power amplifier includes: the universal carrier amplifier is a nested two-way inverse doherty sub-amplifier; the general peak amplifier is connected to the general carrier amplifier and is a nested single-terminal amplifier or a nested two-path general Doherty sub-amplifier; the common carrier amplifier and the common peak amplifier are arranged in the form of a common two-way inverting doherty power amplifier.

In one embodiment, a general carrier amplifier includes a subcarrier amplifier and a first sub-peak amplifier connected to the subcarrier amplifier, the subcarrier amplifier having a first semiconductor characteristic and the first sub-peak amplifier having a second semiconductor characteristic with harmonic termination, and an amplifier efficiency of the first sub-peak amplifier is higher than an amplifier efficiency of the subcarrier amplifier.

In one embodiment, the general peak amplifier includes a second sub-peak amplifier having the first semiconductor feature.

In an implementation of this embodiment, the bias voltage values of the subcarrier amplifier and the sub-second peaking amplifier are positive, and the bias voltage value of the first sub-peaking amplifier is negative.

In an implementation of this embodiment, the power ratio among the subcarrier amplifier, the first sub-peak amplifier and the second sub-peak amplifier is determined according to a Power Distribution Function (PDF) of an applied high peak-to-average power ratio (PAPR) signal.

In an implementation of this embodiment, the first semiconductor feature is an LDMOS and the second semiconductor feature is a gan hemt.

In an implementation of this embodiment, the power gain of the first sub-peaking amplifier is greater than the power gain of the sub-carrier amplifier for power gain expansion, the power gain of the sub-carrier amplifier is compressed to a predetermined compression level, and the power gain of the first peaking amplifier is uncompressed.

In an implementation of this embodiment, the characteristic of the power gain expansion is the inverse characteristic of a driver amplifier connected to the multi-stage doherty power amplifier in a queue or cascade manner in order to perform predistortion on the driver amplifier.

In another embodiment, the general peak amplifier includes a plurality of sub-peak amplifiers, the final stage sub-peak amplifier has a first semiconductor characteristic, the other stages of sub-peak amplifiers except the final stage sub-peak amplifier have a second semiconductor characteristic, and the amplifier efficiency of the other stages of sub-peak amplifiers except the final stage sub-peak amplifier is higher than the amplifier efficiency of the final stage sub-peak amplifier.

In an embodiment of this embodiment, the bias voltage values of the subcarrier amplifier and the final-stage sub-peak amplifier are positive, and the bias voltage values of the first sub-peak amplifier and the sub-peak amplifiers of the other stages than the final-stage sub-peak amplifier are negative.

In an implementation of this embodiment, the power ratios among the subcarrier amplifier, the first sub-peak amplifier and the plurality of sub-peak amplifiers are determined according to a Power Distribution Function (PDF) of an applied high peak-to-average power ratio (PAPR) signal.

In an implementation of this embodiment, the first semiconductor feature is an LDMOS and the second semiconductor feature is a gan hemt.

In an embodiment of this embodiment, the power gain of the sub-peak amplifiers of the other stages except the final-stage sub-peak amplifier is higher than that of the first sub-peak amplifier for power gain expansion; the power gain of each sub-peak amplifier in the other sub-peak amplifiers except the final sub-peak amplifier is higher than that of the sub-peak amplifier in the previous sub-peak amplifier for power gain expansion; the power gain of the sub-carrier amplifier is compressed to a predetermined compression level, and the power gains of the sub-peak amplifiers of the other stages except the final stage sub-peak amplifier are not compressed.

In an implementation of this embodiment, the power gain expansion is characterized as opposed to a driver amplifier connected in a serial or cascaded fashion to a multi-stage doherty power amplifier in order to perform predistortion on the driver amplifier.

In an implementation of this embodiment, the general peak amplifier includes 3 sub-peak amplifiers to form a four-stage doherty power amplifier.

In a second aspect, a transmitter is provided. The transmitter includes a signal processor configured to perform signal processing on baseband input signals of a plurality of channels; and a multi-stage doherty power amplifier as described in the first aspect.

In a third aspect, an apparatus is provided. The apparatus comprising a processor, a memory containing a program comprising instructions executable by the processor, and a transmitter as described in the second aspect.

In one embodiment, the device is a terminal device.

In another embodiment, the device is a network device.

According to various embodiments of the present disclosure, a signal power Probability Distribution Function (PDF) oriented for a cost-effective multi-stage doherty PA design is applied, and two-way normal and inverted doherty PA units are used as basic units to construct a multi-stage doherty PA with gain expansion effect.

According to various embodiments of the present disclosure, the doherty output power back-off range is segmented for different designs. Transistors based on different semiconductor processes are simultaneously used for different segment output power back-off ranges. They are designed separately to meet different requirements for power, efficiency and cost.

According to various embodiments of the present disclosure, the gain expansion effect is used to compensate for non-linearities of the driver amplifier. Thus, overall queue efficiency will be improved.

Drawings

The foregoing and other aspects, features and advantages of various embodiments of the present disclosure will become more fully apparent from the following detailed description, taken in conjunction with the accompanying drawings, wherein like reference numerals or letters are used to designate like or equivalent elements. The accompanying drawings are shown to facilitate a better understanding of the disclosed embodiments and are not necessarily drawn to scale, wherein:

fig. 1 is a schematic diagram of a cell of a wireless communication network;

FIG. 2 illustrates a block diagram of a multi-stage Doherty PA of the present disclosure;

FIG. 3 illustrates a block diagram of a three-stage Doherty PA of the present disclosure;

FIG. 4 illustrates a block diagram of a four-stage Doherty PA of the present disclosure;

FIG. 5 illustrates a generic three-level doherty PA used in this disclosure to "step-by-step" process segmented doherty operating regions;

FIG. 6 illustrates a generalized four-level Doherty PA used in this disclosure to "step-by-step" process segmented Doherty operating regions;

FIG. 7 is a flow chart showing how PDF analysis is used to obtain the doherty design parameters in this disclosure;

FIG. 8 is an illustration of the "step-by-step" division of the Doherty operation region in this disclosure;

FIG. 9 is a graphical illustration of the input biasing scheme in the present disclosure compared to LDMOS and GaN alone solutions;

fig. 10 is a diagram of an analog predistortion scheme in the present disclosure;

fig. 11 is a block diagram of a queue configuration of a predistortion queue in the present disclosure with a higher driver level and queue efficiency and an existing solution;

FIG. 12 is a schematic diagram of a technical embodiment of the present disclosure as a four-stage Doherty PA;

FIG. 13 is a graphical representation of supply current versus output power in the present disclosure;

FIG. 14 is a graphical representation of PAE and gain versus output power and gain spread effect observations in the present disclosure;

FIG. 15 is a graphical illustration of gain expansion effect observation in RF output power versus RF input power in the present disclosure;

fig. 16 is a diagram of a transmitter of the present disclosure;

fig. 17 is a simplified block diagram of an apparatus according to an embodiment of the present disclosure.

Detailed Description

The present disclosure will now be described with reference to a number of example embodiments. It should be understood that these examples are discussed only for the purpose of enabling those skilled in the art to better understand the present disclosure and to thereby carry out the present disclosure, and do not imply any limitation on the scope of the present disclosure.

As used herein, the term "wireless communication network" refers to a network that conforms to any suitable communication standard, such as LTE-advanced (LTE-a), LTE, Wideband Code Division Multiple Access (WCDMA), High Speed Packet Access (HSPA), and the like. Further, communication between the terminal device and the network device in the wireless communication network may be performed according to any appropriate generation of communication protocol, including, but not limited to, first generation (1G), second generation (2G), 2.5G, 2.75G, third generation (3G), fourth generation (4G), 4.5G, future fifth generation (5G) communication protocols, and/or any other protocol now known or to be developed in the future.

The term "network device" refers to a device in a wireless communication network via which a terminal device accesses the network and receives services therefrom. A network device refers to a Base Station (BS), an Access Point (AP), a server, a controller, or any other suitable device in a wireless communication network. The BS may be, for example, a node B (NodeB or NB), an evolved NodeB (eNodeB or eNB)), a enode B (gNB), a relay, a low power node (e.g., femto, pico), etc.

Other examples of network devices include multi-standard radio (MSR) radios (e.g., MSR BSs), Base Transceiver Stations (BTSs), transmission points, transmission nodes. More generally, however, a network device may represent any suitable device (or group of devices) capable of, configured to, arranged and/or operable to enable and/or provide terminal device access to a wireless communication network or to provide some service to terminal devices that have access to a wireless communication network.

The term "terminal device" refers to any end device that can access a wireless communication network and receive services from the wireless communication network. By way of example, and not limitation, terminal device refers to a mobile terminal, User Equipment (UE), or other suitable device. The UE may be, for example, a Subscriber Station (SS), a portable subscriber station, a Mobile Station (MS), or an Access Terminal (AT). The terminal devices may include, but are not limited to, portable computers, image capture terminal devices such as digital cameras, gaming terminal devices, music storage and playback devices, mobile phones, cellular phones, smart phones, tablets, wearable devices, Personal Digital Assistants (PDAs), vehicles, and the like.

The terminal device may support device-to-device (D2D) communication, for example by implementing the 3GPP standard for sidelink communication, and may be referred to in this case as a D2D communication device.

As yet another particular example, in an internet of things (IoT) scenario, a terminal device may represent a machine or other device that performs monitoring and/or measurements and transmits results of such monitoring and/or measurements to another terminal device and/or network device. In this case, the terminal device may be a machine-to-machine (M2M) device, which may be referred to as a Machine Type Communication (MTC) device in the 3GPP context.

As a specific example, the terminal device may be a UE implementing the 3GPP narrowband internet of things (NB-IOT) standard. Specific examples of such machines or devices are sensors, metering devices (e.g., power meters), industrial machines, or household or personal appliances (e.g., refrigerators, televisions, personal wearable computing devices (e.g., watches), etc.). In other scenarios, a terminal device may represent a vehicle or other device capable of monitoring and/or reporting its operational status or other functionality associated with its operation.

As used herein, the terms "first" and "second" refer to different elements. The singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," "containing" and/or "incorporating" mean the presence of stated features, elements, and/or components, etc., but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. The term "based on" should be read as "based at least in part on. The terms "one embodiment" and "an embodiment" should be read as "at least one embodiment". The term "another embodiment" should be read as "at least one other embodiment". Other explicit and implicit definitions may be included below.

Some exemplary embodiments of the present disclosure will be described below with reference to the accompanying drawings. Referring first to fig. 1, a schematic diagram of a wireless communication network 100 is shown. Here, a network device 101 and a terminal device 102 in a wireless communication network 100 are shown. In the example of fig. 1, a network device 101 serves a terminal device 102.

It should be understood that the configuration of fig. 1 is described for illustrative purposes only, and does not imply any limitation on the scope of the present disclosure. Those skilled in the art will appreciate that wireless communication network 100 may include any suitable number of terminal devices and/or network devices, and may have other suitable configurations.

For convenience, in the following embodiments, a MIMO system is described as an example, but the embodiments are not limited thereto, and any system related to a multi-channel power amplifier (e.g., a satellite system, etc.) is possible in the present invention.

The present disclosure is proposed to solve at least one of the problems described in the summary of the invention (i.e., the problem of low efficiency and the problem of poor linearity). Embodiments of the present disclosure will be described below with reference to the accompanying drawings and specific embodiments.