阅读说明：本技术 固态储存装置及其电源失效时的数据处理方法 (Solid-state storage device and data processing method thereof during power failure ) 是由 李宜忠 谢尚均 曾士豪 毛超远 于 2018-07-06 设计创作，主要内容包括：一种固态储存装置及其电源失效时的数据处理方法,固态储存装置包括：一缓冲器,暂时储存一写入数据；一非挥发性记忆体,包括多个芯片,每一该芯片中包括一第一部分空间作为一数据储存区；以及一控制器,连接至一主机、该缓冲器、该非挥发性记忆体。当一电源失效发生时,若该写入数据未到达一预定数据量时,该控制器对该写入数据进行一同位检查,并产生一同位数据；以及,该控制器将该缓冲器中的该写入数据分配为至少一笔子写入数据,并将该至少一笔子写入数据同时储存至部分该些芯片的该数据储存区,且该控制器将该同位数据以及一位置信息储存至该非挥发性记忆体的一系统储存区。(A solid-state storage device and a data processing method thereof when a power supply fails, the solid-state storage device comprises: a buffer for temporarily storing a write data; a non-volatile memory, which comprises a plurality of chips, wherein each chip comprises a first partial space as a data storage area; and a controller connected to a host, the buffer and the non-volatile memory. When a power failure occurs, if the written data does not reach a preset data volume, the controller carries out a parity check on the written data and generates parity data; and the controller distributes the write data in the buffer into at least one sub-write data and simultaneously stores the at least one sub-write data to the data storage areas of part of the chips, and the controller stores the same-bit data and position information to a system storage area of the non-volatile memory.)

1. A solid state storage device, comprising:

a buffer for temporarily storing a write data;

a non-volatile memory, which comprises a plurality of chips, wherein each chip comprises a first partial space as a data storage area; and

a controller connected to a host, the buffer and the non-volatile memory;

when a power failure occurs, if the written data does not reach a preset data volume, the controller carries out a parity check on the written data and generates parity data; and the controller distributes the write data in the buffer into at least one sub-write data and simultaneously stores the at least one sub-write data to the data storage areas of part of the chips, and the controller stores the same-bit data and position information to a system storage area of the non-volatile memory.

2. The solid state storage device of claim 1, further comprising a voltage detector for receiving a power voltage of the solid state storage device, wherein the voltage detector determines that the power failure occurs when the power voltage drops to a specific voltage value.

3. The solid state storage device of claim 1, wherein the write data is not equal to the predetermined amount of data if the amount of data of the write data plus the amount of data of the parity check does not reach a striped size.

4. The solid-state storage device according to claim 1, wherein the at least one sub-write data is stored in a stripe of the data storage area of the chips, and when the solid-state storage device is restarted and a new write data is to be stored, the new write data is stored in the stripe first.

5. The solid state storage device of claim 1, wherein the controller further generates a system data to be stored in the system storage area when the power failure occurs.

6. The solid state storage device of claim 1, wherein each of the chips comprises a second portion of space, and the second portions of space of the chips are combined into the system storage area.

7. A data processing method of a solid-state storage device, a non-volatile memory in the solid-state storage device comprises a plurality of chips, and each chip comprises a first partial space as a data storage area, the data processing method comprises the following steps:

when the solid-state storage device normally operates, storing write-in data in a buffer, and continuously judging whether a power failure occurs or not;

when the power failure occurs, if the written data does not reach a preset data volume, carrying out a parity check on the written data and generating parity data;

distributing the write data into at least one sub-write data, and simultaneously storing the at least one sub-write data into the data storage areas of part of the chips; and

storing the parity data and a location information into a system storage area of the non-volatile memory.

8. The data processing method of claim 7, wherein the power failure is determined when a power voltage of the solid-state storage device drops to a specific voltage value.

9. The data processing method of claim 7, wherein the write data is not equal to the predetermined data amount if the data amount of the write data plus the data amount of the parity check does not reach a striped size.

10. The data processing method of claim 7, wherein the at least one sub-write data is stored in a stripe of the data storage area of the chips, and when the solid-state storage device is restarted and a new write data is to be stored, the new write data is stored in the stripe first.

11. The data processing method of claim 7, further generating a system data to be stored in the system storage area when the power failure occurs.

12. The data processing method of claim 7, wherein each of the chips comprises a second portion of space, and the second portions of space of the chips are combined into the system storage area.

13. The data processing method of claim 7, further comprising the steps of:

after the power failure occurs, judging whether a false power failure occurs; and

when the false power failure occurs, the solid state storage device is enabled to return to normal operation.

14. The data processing method of claim 13, wherein the power failure is detected to be a power voltage recovery of the solid-state storage device after the power failure occurs, and the power failure is determined to be a false power failure.

Technical Field

The present invention relates to a solid state storage device and a data processing method thereof, and more particularly, to a solid state storage device and a data processing method thereof when a power failure (power failure) occurs.

Background

It is known that data in early computer systems was mostly stored in Hard disks (Hard Disk Drive). A fault-tolerant array of independent disks (RAID) combines multiple hard disks, so that the performance of the RAID exceeds that of one expensive hard disk with a large capacity.

For example, the RAID hard disk includes a plurality of independent hard disks, and during the writing operation, the controller may allocate the write data to a plurality of sub-write data, and write the plurality of sub-write data to all the independent hard disks in the RAID hard disk at the same time.

During reading, the controller obtains multiple sub-read data from all independent hard disks in the RAID hard disk and combines the sub-read data into read data. Therefore, the RAID hard disk has advantages of improving the performance (performance) of data, enhancing the reliability (reliability) of data, increasing the capacity (capacity), and the like.

Since the current solid state storage device has gradually replaced the conventional hard disk, the RAID concept is also applied to a single solid state storage device.

Referring to fig. 1, a schematic diagram of a conventional solid-state storage device is shown. The solid-state storage device 160 includes a controller 162, a buffer 164, and a non-volatile memory 166. The non-volatile memory 166 is composed of a plurality of chips (die) 111-126, and the chips 111-126 can be NAND flash memory chips (NAND flash die). In addition, the buffer 164 may be a Dynamic Random Access Memory (DRAM).

The solid-state storage device 160 is connected to the host (host)150 via an external bus 152, wherein the external bus 152 may be a USB bus, a SATA bus, a PCIe bus, an m.2 bus, or an U.2 bus, etc.

Further, the controller 162 is connected to the non-volatile memory 166 and the buffer 164. Basically, the controller 162 temporarily stores the write data of the host 150 in the buffer 164 according to the write command issued by the host 150, and stores the write data in the buffer 164 in the non-volatile memory 166 at an appropriate time. Furthermore, the controller 162 further operates the nonvolatile memory 166 according to a read command issued by the host 150 to obtain read data, and the read data is transmitted to the host 150 through the controller 162.

In order to achieve the performance of the RAID hard disk, the controller 162 may treat each of the chips 111-126 in the non-volatile memory 166 as a separate hard disk.

First, the controller 162 temporarily stores write data of the host 150 in the buffer 164 in response to a write command. Then, the controller 162 allocates the write data in the buffer 164 to a plurality of sub-write data at an appropriate timing, and writes the plurality of sub-write data into the chips 111-126 simultaneously. For example, when the data amount in the buffer 164 reaches a predetermined data amount, the controller 162 allocates the write data in the buffer 164 to a plurality of sub-write data, and writes the plurality of sub-write data into the chips 111-126 simultaneously.

When the controller 162 executes a read command of the host 150, the controller 162 acquires a plurality of sub-write data from the chips 111-126, combines the sub-write data into read data, and transmits the read data to the host 150.

Referring to fig. 2A and 2B, schematic diagrams of storing write data in a non-volatile memory are shown. Basically, the controller 162 stores the write data in the buffer 164 into the non-volatile memory 166 only after the write data temporarily stored in the buffer 164 reaches a specific data amount.

Furthermore, most of the space in each of the chips 111-126 is allocated as data storage areas (data storage areas) 111 d-126 d. The controller 162 can store the write data of the host 150 in the data storage areas (data storage areas) 111d to 126d of the chips 111 to 126. That is, the data storage areas (datastore areas) 111d 126d of the chips 111-126 are areas where the host 150 can store and read data.

Furthermore, the data storage areas (data storage areas) 111d to 126d of the chips 111 to 126 are divided into a plurality of stripes (stripes). For example, assume that there are 16 chips 111-126 in the non-volatile memory 166, and the striping size (stripe size) set in the solid-state storage device 160 is 160 Kbytes. Therefore, the controller 162 can simultaneously write sub-write data of 10Kbytes to each of the chips 111-126. In addition, the reliability of data in the non-volatile memory 166 is to be maintained. The last chip 126 is used to store parity data.

That is, each specific storage space (e.g., 10Kbytes) in the data storage areas (data storage areas) 111 d-126 d of each of the chips 111-126 is a storage space logically combined into one stripe (stripe). The storage space of each stripe is the striping size (stripe size).

Furthermore, after 150Kbytes of write data is temporarily stored in the buffer 164, the controller 164 performs a parity check on the 150Kbytes of write data and generates 10Kbytes of parity data. Therefore, the write data plus the same-bit data corresponds to 160Kbytes of the striping size (stripe size).

After the controller 162 divides the 150Kbytes write data area into 15 sub-write data Da1 Da15, the controller 162 stores the sub-write data Da1 Da15 and the identical data Dap into the first stripe (stripe) SP1 of the data storage areas 111d 126d of the chips 111-126.

As shown in FIG. 2A, the data storage area 111d of the chip 111 stores 10Kbytes of sub-write data Da1, the data storage area 112d of the chip 112 stores 10Kbytes of sub-write data Da2, and the data storage area 113d of the chip 113 stores 10Kbytes of sub-write data Da 3. By analogy, the data storage area 125d of the chip 125 stores sub-write data Da15 of 10 Kbytes. In addition, the data storage area 126d of the chip 126 stores the same-bit data Dap of 10 Kbytes.

Furthermore, when the controller 162 executes the read command, the controller 162 obtains 15 sub-write data Da1 Da15 and the same-bit data Dap from the chips 111-126 at the same time, and performs the parity check to combine the sub-write data and the same-bit data into 150Kbytes of read data, and then transmits the 150Kbytes of read data to the host 150.

As shown in FIG. 2B, when the 150Kbytes of write data are temporarily stored in the buffer 164 again, the controller 164 performs the same operation and stores the 15 sub-write data Db 1-Db 15 and the same bit data Dbp into the second stripe SP2 of the data storage areas 111 d-126 d of the chips 111-126.

Furthermore, the striping size (stripe size) of the solid-state storage device 160 is not limited to 160Kbytes, and the number of chips in the non-volatile memory 166 is not limited to 16 chips. For example, there are n chips in the nonvolatile memory 166, and the striping size of the solid-state storage device 160 is set to mKbytes. Thus, the size of each sub-write data is (m/n) Kbytes.

Disclosure of Invention

The invention aims to provide a solid-state storage device and a data processing method thereof when a power supply fails.

The invention provides a solid-state storage device, comprising: a buffer for temporarily storing a write data; a non-volatile memory, which comprises a plurality of chips, wherein each chip comprises a first partial space as a data storage area; and a controller connected to a host, the buffer and the non-volatile memory. When a power failure occurs, if the written data does not reach a preset data volume, the controller carries out a parity check on the written data and generates parity data; and the controller distributes the write data in the buffer into at least one sub-write data and simultaneously stores the at least one sub-write data to the data storage areas of part of the chips, and the controller stores the same-bit data and position information to a system storage area of the non-volatile memory.

The invention relates to a data processing method of a solid-state storage device, wherein a non-volatile memory in the solid-state storage device comprises a plurality of chips, and each chip comprises a first partial space as a data storage area. The data processing method comprises the following steps: when the solid-state storage device normally operates, storing write-in data in a buffer, and continuously judging whether a power failure occurs or not; when the power failure occurs, if the written data does not reach a preset data volume, carrying out a parity check on the written data and generating parity data; distributing the write data into at least one sub-write data, and simultaneously storing the at least one sub-write data into the data storage areas of part of the chips; and storing the parity data and a location information into a system storage area of the non-volatile memory.

The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.

Drawings

FIG. 1 is a diagram of a conventional solid state memory device;

FIGS. 2A and 2B are schematic diagrams illustrating the storage of write data in a non-volatile memory;

FIG. 3 is a diagram of a solid state memory device according to the present invention;

FIG. 4A is a diagram illustrating a data processing method for a solid-state storage device in a power failure mode according to a first embodiment of the present invention;

FIGS. 4B to 4C are schematic diagrams illustrating a data processing method according to a first embodiment of the invention;

FIG. 5A is a diagram illustrating a data processing method for a solid-state storage device in a power failure mode according to a second embodiment of the present invention;

FIGS. 5B to 5C are schematic diagrams illustrating a data processing method according to a second embodiment of the present invention;

FIG. 6A is a diagram illustrating a data processing method for a solid-state storage device in a power failure mode according to a third embodiment of the present invention;

FIGS. 6B to 6C are schematic diagrams illustrating a data processing method according to a third embodiment of the invention;

FIG. 7A is a diagram illustrating a fourth embodiment of a data processing method when a power failure occurs in a solid-state storage device according to the present invention;

fig. 7B to 7C are schematic diagrams illustrating a data processing method according to a fourth embodiment of the invention.

Detailed Description

The invention will be described in detail with reference to the following drawings, which are provided for illustration purposes and the like:

basically, solid-state storage devices used at the data center (data center) level must be able to ensure data reliability, and therefore, more data protection measures are available for solid-state storage devices. For example, power failure (powerfailure) data protection measures.

Referring to fig. 3, a schematic diagram of a solid-state storage device according to the present invention is shown. Compared to the solid-state storage device of fig. 1. The controller 362 of the solid-state storage device 360 of the present invention includes a voltage detector 364 connected to a power detection pin pdp for detecting whether the power voltage Vcc of the solid-state storage device 360 is stable.

As shown in fig. 3, the solid-state storage device 360 includes a capacitor C, a first terminal of the capacitor C receives the power voltage Vcc, and a second terminal of the capacitor C is connected to the ground voltage. Furthermore, the power detection pin pdp of the controller 362 is connected to the first terminal of the capacitor C.

According to the embodiment of the invention, the voltage detector 364 of the controller 362 continuously detects the voltage on the capacitor C when the solid-state storage device 360 is operating normally. When the voltage on the capacitor C drops to a specific voltage value (e.g., 0.95 × Vcc), the voltage detector 364 determines that the power supply is disabled. At this time, the controller 362 must perform a data protection operation using the amount of electricity remaining in the capacitor C.

During the data protection operation, the controller 362 needs to store the write data in the buffer 164 into the non-volatile memory 166 to prevent the write data in the buffer 164 from disappearing when the solid-state storage device 160 is powered off. The following describes the data processing method of the solid-state storage device in the case of power failure.

Referring to fig. 4A, a first embodiment of a data processing method of a solid-state storage device in the case of power failure is shown.

First, the solid state storage device 360 operates normally (step S402). That is, when the power failure does not occur, the solid state storage device 360 operates normally. At this time, the controller 362 may receive the host 150 and execute commands of the host 150, for example, the controller 362 executes write commands and temporarily stores the write data in the buffer 164.

When a power failure occurs (step S404), the controller 362 performs a data protection operation. At this time, the controller 362 generates invalid data (invalid data) and performs parity check so that the data amount in the buffer 164 is expanded to the striping size (step S406).

Next, the controller 362 divides the data in the buffer 164 into a plurality of sub-write data and a same-bit data (step S408). Then, all the sub-write data and the same-bit data are simultaneously stored in the data storage areas 111d 126d of all the chips 111-126 (step S410).

Next, the controller 362 updates the system data in the system storage area (step S412).

Fig. 4B to 4C are schematic diagrams illustrating a data processing method according to a first embodiment of the invention. For example, the nonvolatile memory 166 has 16 chips 111-126, and the striping size (stripe size) set in the solid state storage device 360 is 160 Kbytes.

According to the embodiment of the present invention, most of the space in each of the chips 111-126 is allocated as a data storage area (data storage area)111 d-126 d, and another part of the space 111 s-126 in each of the chips 111-126 constitutes a system storage area (system storage area). Moreover, data storage areas (data storage areas) 111d 126d of the chips 111-126 are areas where the host 150 can store and read data, and the host 150 cannot access data in the system storage area.

Basically, the system storage area stores system data (system data) which records relevant information in the solid state storage device 360. For example, the system data includes the available space range in the data storage area 111 d-126 d of the chip 111-126, the location of a bad block (bad block), or the event (event) occurred.

When the solid-state storage device 360 is turned off, the controller 362 updates the system data in the system storage area. Therefore, when the solid state storage device 360 is turned on again, the controller 362 initializes the solid state storage device 360 according to the latest system data in the system storage area, and then the solid state storage device can operate normally.

As shown in FIG. 4B, 15 sub-write data Da1 Da15 and the same-bit data Dap are already stored in the first stripe SP1 of the data storage areas 111d 126d of the chips 111-126.

Assuming that a power failure occurs, only 20Kbytes of write data is stored in the buffer 164. At this time, the controller 362 generates invalid data of 130Kbytes and performs parity check to generate parity data of 10 Kbytes. Thus, the amount of data in the buffer 164 is expanded to a striping size of 160 Kbytes.

As shown in FIG. 4C, the controller 362 divides the write data in the buffer 164 into 15 sub-write data Db1, Db2, Div 1-Div 13 and the same-bit data Dbp. Thereafter, the controller 362 stores all the sub-write data Db1, Db2, Div 1-Div 13 and the parity data Dbp into the second stripe SP2 of the data storage areas 111 d-126 d of the chips 111-126. The sub-write data Div1 to Div13 are invalid data.

Then, the controller 362 updates the system data Ds1 in the system storage area 111 s.

After the above operations are completed, the solid state storage device 360 is powered off (power off) until the remaining power in the capacitor C is exhausted.

As can be seen from the above description, when a power failure occurs, the controller 362 must perform a data protection operation to prevent the loss of the write data and ensure the correctness of the write data by using the remaining power in the capacitor C.

However, according to the first embodiment of the present invention, during the data protection operation, the controller 362 must generate invalid data, perform parity check, store the sub-write data and the parity data in the data storage areas 111 d-126 d of all the chips 111-126 simultaneously, and update the system data in the system storage area. Obviously, the amount of charge remaining in capacitor C does not guarantee that controller 362 can perform all of the above-described actions.

Referring to fig. 5A, a second embodiment of a data processing method of a solid-state storage device in the case of power failure is shown.

First, the solid state storage device 360 operates normally (step S502). That is, when the power failure does not occur, the solid state storage device 360 operates normally. At this time, the controller 362 may receive the host 150 and execute a command of the host 150, such as a write command or a read command.

When a power failure occurs (step S504), the controller 362 performs a data protection operation. At this time, the controller 362 performs a parity check according to the write data in the buffer 164 to generate parity data (step S506).

Next, the controller 362 divides the data in the buffer 164 into a plurality of sub-write data and a same-bit data (step S508). Then, all the sub-write data and the same-bit data are stored in the data storage area of a part of the chip (step S510).

Next, the controller 362 updates the system data in the system storage area (step S512).

Referring to fig. 5B to 5C, schematic diagrams of a data processing method according to a second embodiment of the invention are shown. The non-volatile memory 166 has 16 chips 111-126, and the striping size (stripe size) set in the solid-state storage device 360 is 160 Kbytes.

As shown in FIG. 5B, 15 sub-write data Da1 Da15 and the same-bit data Dap are already stored in the first stripe SP1 of the data storage areas 111d 126d of the chips 111-126.

Assuming that a power failure occurs, only 20Kbytes of write data is stored in the buffer 164. At this time, the controller 362 directly performs the parity check according to the write data in the buffer 164, and generates the 10Kbytes parity data. At this time, the amount of data in the buffer 164 is expanded to only 30Kbytes, not to the striping size.

As shown in FIG. 5C, the controller 362 divides the write data in the buffer 164 into 2 sub-write data Db1, Db2 and the same-bit data Dbp. Thereafter, the controller 362 simultaneously stores the sub-write data Db1, Db2 and the same-bit data Dbp into the second stripe SP2 of the data storage areas 111 d-113 d of the three chips 111-113, while the second stripe SP2 (dotted line portion) of the data storage areas 114 d-126 d of the other chips 114-126 does not store any data. Thus, it is ensured that the written data will not be lost.

Then, the controller 362 updates the system data Ds1 in the system storage area 111 s.

After the above operations are completed, the solid state storage device 360 is powered off (power off) until the remaining power in the capacitor C is exhausted.

Compared to the first embodiment, the controller 362 of the second embodiment does not need to generate invalid data when a power failure occurs, so that the controller 362 can be ensured to complete all the above actions in real time. However, after the parity data Dbp is written into the data storage area 113d of the chip 113, the other space (the dotted area in the second stripe SP2 of the data storage areas 114d to 126 d) in the corresponding stripe (stripe) can not be used for storing other sub-write data temporarily. In other words, when the solid-state storage device 360 is restarted and new write data is to be stored, the new write data is stored in another stripe (stripe). For example, in the above embodiment, when the solid state storage device 360 is restarted and new write data is to be written, the new write data cannot be stored in the virtual line portion area of the second stripe SP2, which is to be stored in the next stripe, such as the third stripe SP 3.

Referring to fig. 6A, a third embodiment of a data processing method of a solid-state storage device in the case of power failure is shown.

First, the solid state storage device 360 operates normally (step S602). That is, when the power failure does not occur, the solid state storage device 360 operates normally. At this time, the controller 362 may receive the host 150 and execute a command of the host 150, such as a write command or a read command.

When a power failure occurs (step S604), the controller 362 performs a data protection operation. At this time, the controller 362 performs a parity check according to the write data in the buffer 164 to generate parity data (step S606).

Next, the controller 362 divides the data in the buffer 164 into a plurality of sub-write data and a same-bit data (step S608). Then, all the sub-write data are stored in the data storage area of part of the chip at the same time (step S610).

Next, the controller 362 updates the system data, the position information and the parity data in the system storage area (step S612).

Fig. 6B to 6C are schematic diagrams illustrating a data processing method according to a third embodiment of the invention. The non-volatile memory 166 has 16 chips 111-126, and the striping size (stripe size) set in the solid-state storage device 360 is 160 Kbytes.

As shown in FIG. 6B, 15 sub-write data Da1 Da15 and the same-bit data Dap are already stored in the first stripe SP1 of the data storage areas 111d 126d of the chips 111-126.

Assuming that a power failure occurs, only 20Kbytes of write data is stored in the buffer 164. At this time, the controller 362 directly performs the parity check according to the write data in the buffer 164, and generates the 10Kbytes parity data. At this time, the amount of data in the buffer 164 is expanded to only 30Kbytes, not to the striping size.

As shown in FIG. 6C, the controller 362 divides the write data in the buffer 164 into 2 sub-write data Db1, Db2 and the same-bit data Dbp 1. Thereafter, the controller 362 simultaneously stores the sub-write data Db1 and Db2 in the second stripe SP2 of the data storage areas 111d 112d of the two chips 111-112, while the second stripe SP2 of the data storage areas 113d 126d of the other chips 113-126 does not store any data.

Then, the controller 362 updates the system data Ds1, the position information Inf _ b and the parity data Dbp1 in the system storage areas 111 s-113 s. The location information Inf _ b is used to indicate the storage locations of the sub-write data Db1, Db2 in the non-volatile memory 166. That is, the parity data Dbp1 is obtained by performing the parity check according to the sub-write data Db1 and Db2 indicated by the position information Inf _ b. In other words, the controller 362 can know that the parity data Dbp1 is generated after performing the parity check on the sub-write data in which storage locations according to the location information Inf _ b.

After the above operations are completed, the solid state storage device 360 is powered off (power off) until the remaining power in the capacitor C is exhausted.

According to the third embodiment of the present invention, the controller 362 does not need to generate invalid data when a power failure occurs, so that it is ensured that the controller 362 can immediately complete all the above actions. Furthermore, since the parity data Dbp1 is updated in the system storage areas 111 s-113 s, other spaces in the corresponding stripe (stripe) will be available for storing the sub-write data. In other words, when the solid-state storage device 360 is restarted and new write data is to be stored, the new write data may be stored in the corresponding stripe that was last stored before the power failure. For example, in the above embodiment, when the solid state storage device 360 is restarted and new write data is to be stored, the new write data can be stored in the second stripe SP2 of the data storage areas 113 d-126 d of the other chips 113-126.

Referring to fig. 7A, a fourth embodiment of a data processing method of a solid-state storage device in the case of power failure is shown. Compared with the third embodiment of the present invention, the fourth embodiment adds a step of determining whether the power supply voltage Vcc is a false power failure (step S614).

Basically, when the power fails, the controller 362 performs a data protection operation, and the capacitor C is exhausted to power down the solid-state storage device 360 (step S616). However, when the power supply voltage Vcc returns to normal before the capacitor C is exhausted, it is considered as a false power failure (electrical breakdown). In other words, if the power supply voltage Vcc returns to normal before the capacitor C is exhausted, the controller 362 returns to step S602, so that the solid state storage device 360 operates normally again.

Referring to fig. 7B to 7C, schematic diagrams of a data processing method according to a fourth embodiment of the invention are shown. Fig. 7B is a sequence of operations shown in fig. 6C.

As shown in fig. 6C, after the controller 362 updates the system data Ds1, the location information Inf _ b and the parity data Dbp1 in the system storage area 111S, the controller 362 determines whether the power supply voltage Vcc is a false power failure (electrical power failure) (step S614). If the power supply voltage Vcc is not a false power failure, for example, the controller 362 does not detect that the power supply voltage Vcc returns to normal, the solid state storage device 360 is powered off (power off) after the power remaining in the capacitor C is exhausted (step S616). On the other hand, if the power supply voltage Vcc is determined to be a false power failure, for example, the controller 362 detects that the power supply voltage Vcc returns to normal, and the controller 362 resumes normal operation.

Since 20Kbytes of write data have been temporarily stored in the buffer 164. Therefore, when the controller 362 receives 130Kbytes of write data again, the controller 362 performs the parity check on the write data in the buffer 164 to generate 10Kbytes of parity data Dbp 2. That is, the amount of data in the buffer 164 is expanded to the striping size.

As shown in FIG. 7B, in normal operation, the controller 362 divides the written data that has not been written into the nonvolatile memory 166 into 13 sub-written data Db 3-Db 15. Then, the controller 362 stores the 13 sub-write data Db 3-Db 15 and the same-bit data Dp2 in the second stripe SP2 of the data storage areas 113 d-126 d of the chips 113-126.

As shown in fig. 7C, assuming that 10Kbytes of write data is received again in the buffer 164, a power failure occurs. At this time, the controller 362 directly performs the parity check according to the write data in the buffer 164, and generates the 10Kbytes parity data. At this time, the amount of data in the buffer 164 is expanded to only 20Kbytes, not to the striping size.

Next, the controller 362 divides the write data in the buffer 164 into 1 sub-write data Dc1 and the same-bit data Dcp 1. Thereafter, the controller 362 simultaneously stores the sub-write data Dc1 in the third stripe SP3 of the data storage area 111d of the chip 111, while no data is stored in the other data storage areas 112d 126d of the third stripe SP 3.

Then, the controller 362 updates the system data Ds2, the position information Inf _ c, and the parity data Dcp1 in the system storage region 111 s. The system data Ds2, the position information Inf _ c and the parity data Dcp1 replace the previously written system data Ds1, the position information Inf _ b and the parity data Dbp 1.

After the above operations are completed, the controller 362 will continuously determine whether the power failure is false, i.e. whether the power supply voltage Vcc returns to normal is detected, until the power is turned off after the residual power in the capacitor C is exhausted.

As can be seen from the above description, the present invention provides a solid-state storage device and a data processing method thereof when a power supply fails. A voltage detector 364 is included in the controller 362 of the solid-state storage device 360 for determining whether a power failure has occurred. When a power failure occurs, the controller 362 stores the write data in the buffer 164 into the nonvolatile memory 166 to prevent the write data from being lost. Furthermore, parity data generated after parity checking can be stored in the data storage area or system storage area of the non-volatile memory 166, thereby ensuring the correctness of the write data.

Furthermore, the voltage detector 364 in the embodiment of the present invention may also be designed outside the controller 362. When the voltage detector determines that the power supply fails, it notifies the controller 362 to perform data protection.

In addition, in the present invention, a small portion of the area 111 s-126 s in each chip 111-126 is used to form a system storage area. It is understood that the present invention is not limited thereto, and those skilled in the art can add a chip to the non-volatile memory and utilize the space in the added chip as the system storage area.

The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.