阅读说明：本技术 存储器系统及其操作方法 (Memory system and operating method thereof ) 是由 崔海起 于 2019-04-02 设计创作，主要内容包括：本发明公开了一种存储器系统。存储器系统可以包括：非易失性存储器装置；写入缓冲器；以及控制器,适于：在写入缓冲器上执行清除操作的时间点检查是否已提交第一写入数据,根据检查结果将清除操作分为彼此不重叠但彼此连续的第一清除操作和第二清除操作,当分组为事务的第一写入数据和未分组为事务的第二写入数据混合并存储在写入缓冲器中时,执行第一清除操作和第二清除操作；在存储在写入缓冲器中的写入数据之中,控制器在第一清除操作期间可选择提交的第一写入数据并将提交的第一写入数据存储在非易失性存储器装置的第一存储区域中。(The invention discloses a memory system. The memory system may include: a non-volatile memory device; a write buffer; and a controller adapted to: checking whether the first write data has been committed at a point in time when the flush operation is performed on the write buffer, dividing the flush operation into a first flush operation and a second flush operation that do not overlap each other but are continuous with each other according to a result of the checking, and performing the first flush operation and the second flush operation when the first write data grouped as a transaction and the second write data not grouped as a transaction are mixed and stored in the write buffer; among the write data stored in the write buffer, the controller may select committed first write data and store the committed first write data in a first storage area of the nonvolatile memory device during a first clear operation.)

1. A memory system, comprising:

a non-volatile memory device;

a write buffer temporarily storing a plurality of write data received from a host; and

a controller:

checking whether first write data has been committed at a point in time when a flush operation is performed on the write buffer,

dividing the clear operation into a first clear operation and a second clear operation which do not overlap each other but are continuous with each other, according to the check result, an

Performing the first clear operation and the second clear operation when the first write data grouped as a transaction and second write data not grouped as a transaction are mixed and stored in the write buffer according to an order of the write data received from the host, wherein the controller selects the first write data committed among the write data stored in the write buffer and stores the first write data committed in a first storage area of the nonvolatile memory device during the first clear operation, and the controller selects the first write data not completely committed and the second write data among the write data stored in the write buffer and stores the first write data not completely committed and the second write data in a second storage area of the nonvolatile memory device during the second clear operation In the domain.

2. The memory system according to claim 1, wherein the controller receives a plurality of write commands corresponding to respective write data from the host,

wherein each of the write commands includes transaction information of corresponding write data, an

Wherein the transaction information of each of the write data includes transaction identification information, i.e., transaction ID information, commit information, and abort information.

3. The memory system according to claim 2, wherein the controller checks the transaction ID information of the transaction information of the respective write data, classifies the write data having no transaction ID information set therein as the second write data, and classifies the write data having the transaction ID information set to a specific value therein as the first write data.

4. The memory system according to claim 3, wherein the controller performs the clear operation when a predetermined storage space of the write buffer is full,

wherein when it is checked that commit information set at a point of time when the clear operation is performed is included in the transaction information of the respective first write data, the controller selects the first write data committed among the write data stored in the write buffer and stores the first write data committed in the first storage area during the first clear operation, and the controller selects the first write data incompletely committed and the second write data incompletely committed and stores the first write data incompletely committed and the second write data incompletely committed in the second storage area during the second clear operation.

5. The memory system according to claim 4, wherein when it is checked that the set commit information is not included in the transaction information of the respective first write data at a time point of performing the clear operation, the controller selects the first write data and the second write data that are not completely committed among the write data stored in the write buffer during the clear operation, and programs the first write data and the second write data that are not completely committed to the nonvolatile memory device.

6. The memory system according to claim 5, wherein when it is checked that abort information set at a time point of performing the clear operation is included in the transaction information of the respective first write data, the controller does not program the aborted first write data of the write data stored in the write buffer to the nonvolatile memory device even during the clear operation.

7. The memory system of claim 1, wherein the non-volatile memory device includes a plurality of memory blocks, and each of the memory blocks includes a plurality of pages,

wherein when each of the write data is set to a size corresponding to one or more pages, the controller sets one or more specific memory blocks as the first memory region and sets one or more memory blocks of other memory blocks than the specific memory block among the memory blocks as the second memory region, wherein the one or more specific memory blocks among the memory blocks are simultaneously or sequentially accessed for one read operation.

8. The memory system of claim 1, wherein the non-volatile memory device comprises a plurality of memory blocks, each of the memory blocks comprising a plurality of pages, and each of the pages comprising a plurality of sectors,

wherein when each of the write data is set to a size corresponding to one or more sectors, the controller sets one or more specific pages included in one or more specific memory blocks among the memory blocks to be simultaneously or sequentially accessed for one read operation as the first memory region and sets one or more pages of other pages than the specific pages in the specific memory blocks as the second memory region.

9. The memory system according to claim 3, wherein when a merge operation for moving the first write data and the second write data valid in the first storage area and the second storage area to another storage area of the nonvolatile memory device is performed after the first write data and the second write data are stored in the first storage area and the second storage area by the first clear operation and the second clear operation, the controller checks whether all of the first write data stored in the first storage area are valid, and changes a method for performing the merge operation according to a result of the check.

10. The memory system according to claim 9, wherein when the merge operation is performed after the first write data having the transaction ID information set to a first value and the first write data having the transaction ID information set to a second value are stored in the first storage area, the controller moves the first write data having the transaction ID information set to the first value to a third storage area of the nonvolatile memory device, and when the first write data having the transaction ID information set to the first value are all valid and only a part of the first write data having the transaction ID information set to the second value is valid, moves valid data of the first write data having the transaction ID information set to the second value and valid data of the second write data to a fourth storage area of the nonvolatile memory device A domain.

11. An operating method for a memory system including a non-volatile memory device and a write buffer for temporarily storing a plurality of write data received from a host, the operating method comprising:

a first checking step of checking whether first write data grouped as a transaction and second write data not grouped as a transaction are mixed and stored in the write buffer according to an order of the write data received from the host;

a second checking step of checking whether the first write data has been committed at a point in time when a flush operation is performed on the write buffer, when a result of the first checking step indicates that the first write data and the second write data are mixed and stored in the write buffer; and

a dividing and storing step, when the result of the second checking step indicates that the first write data has been committed, dividing the clear operation to the write buffer into a first clear operation and a second clear operation that do not overlap each other but are consecutive to each other, selecting the first write data committed among the write data stored in the write buffer and storing the first write data committed in a first storage area of the non-volatile memory device during the first clear operation, and during the second clear operation, selecting the first write data and the second write data that are not completely committed among the write data stored in the write buffer and storing the first write data and the second write data that are not completely committed in a second storage area of the non-volatile memory device.

12. The method of operation of claim 11, further comprising: receiving a plurality of write commands corresponding to respective write data from the host,

wherein each of the write commands includes transaction information of corresponding write data, an

Wherein the transaction information of each write data includes transaction identification information, i.e., transaction ID information, commit information, and abort information.

13. The method of operation of claim 12, wherein the first checking step comprises:

a first classification step of checking the transaction ID information of the transaction information of the respective write data and classifying the write data for which the transaction ID information is not set into the second write data;

a second classification step of checking the transaction ID information of the transaction information of the respective write data and classifying the write data having the transaction ID information set to a specific value into the first write data; and

a third checking step of checking whether the first write data and the second write data are mixed and stored in the write buffer after the write data stored in the write buffer are classified into the first write data and the second write data by the first classifying step and the second classifying step.

14. The method of operation of claim 13, further comprising: a clear operation step of performing the clear operation when a predetermined storage space of the write buffer is full,

wherein when the result of the third checking step indicates that the first write data and the second write data are mixed and stored in the write buffer, the second checking step includes checking whether commit information set at a point in time when the clearing operation step is performed is included in the transaction information of the respective first write data.

15. The method of operation of claim 14, further comprising:

performing the dividing and storing step when it is checked at the second checking step that the set commit information is included in the transaction information of the respective first write data at a time point at which the clearing operation step is started; and

when it is checked at the second checking step that the set commit information is not included in the transaction information of the respective first write data at a time point at which the clearing operation step is started, the first write data and the second write data that are not completely committed are selected among the write data stored in the write buffer and the selected data are programmed to the nonvolatile memory device during the clearing operation.

16. The method of operation of claim 15, further comprising: checking whether the set abort information is included in the transaction information of the respective first write data at a point of time when the clear operation step is performed, and when the check result indicates that the abort information is included, programming the aborted first write data of the write data stored in the write buffer to the nonvolatile memory device is not performed even during the clear operation.

17. The operating method of claim 11, wherein the non-volatile memory device includes a plurality of memory blocks, and each of the memory blocks includes a plurality of pages,

wherein the method of operation further comprises: when each of the write data is set to a size corresponding to one or more pages, one or more specific memory blocks among the memory blocks, which are simultaneously or consecutively accessed for one read operation, are set as the first memory area, and one or more memory blocks among other memory blocks except the specific memory block among the memory blocks are set as the second memory area.

18. The operating method of claim 11, wherein the non-volatile memory device includes a plurality of memory blocks, each of the memory blocks includes a plurality of pages, and each of the pages includes a plurality of sectors,

wherein the method of operation further comprises: when each of the write data is set to a size corresponding to one or more sectors, one or more specific pages included in one or more specific memory blocks among the memory blocks to be simultaneously or sequentially accessed for one read operation are set as the first memory region, and one or more pages among other pages except the specific pages in a specific memory block are set as the second memory region.

19. The method of operation of claim 13, further comprising: when a merge operation for moving the first write data and the second write data that are valid in the first storage area and the second storage area to another storage area of the nonvolatile memory device is performed after the first write data and the second write data are stored in the first storage area and the second storage area by the first clear operation and the second clear operation in the dividing and storing step,

a fourth checking step of checking whether all the first write data stored in the first storage area are valid; and

a merging operation step of changing a method for performing the merging operation according to a result of the fourth checking step.

20. The operating method according to claim 19, wherein when the merge operation is performed after the first write data having the transaction ID information set to a first value and the first write data having the transaction ID information set to a second value are stored in the first storage area in the second sorting step,

the merging operation step includes moving the first write data having the transaction ID information set to the first value to a third storage area of the nonvolatile memory device, and then moving valid data of the first write data having the transaction ID information set to the second value and valid data of the second write data to a fourth storage area of the nonvolatile memory device when it is checked in the fourth checking step that the first write data having the transaction ID information set to the first value are all valid and that only a part of the first write data having the transaction ID information set to the second value is valid.

Technical Field

The exemplary embodiments relate to a memory system, and more particularly, to a memory system that stores a plurality of write data grouped into transactions (transactions).

Background

Computing environment paradigms have become ubiquitous computing systems that can be used at any time and at any place. Due to this, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers has been rapidly increasing. These portable electronic devices typically use a memory system having one or more memory devices to store data. The memory system may be used as a primary storage device or a secondary storage device for the portable electronic device.

Because the memory system has no moving parts, it can provide excellent stability, endurance, fast information access speed, and low power consumption. Examples of the memory system having such advantages include a Universal Serial Bus (USB) memory device, a memory card having various interfaces, and a Solid State Drive (SSD).

Disclosure of Invention

Various embodiments relate to a memory system that can efficiently store a plurality of write data grouped into transactions and an operating method thereof.

In an embodiment, a memory system may include: a non-volatile memory device; a write buffer adapted to temporarily store a plurality of write data received from a host; and a controller adapted to: checking whether the first write data has been committed (commit) at a point of time when the flush operation is performed on the write buffer, dividing the flush operation into a first flush operation and a second flush operation that do not overlap each other but are consecutive to each other according to a result of the checking, and performing the first flush operation and the second flush operation when the first write data grouped as a transaction and the second write data not grouped as a transaction are mixed and stored in the write buffer according to an order of the write data received from the host. The controller may select the committed first write data among the write data stored in the write buffer and may store the committed first write data in a first storage area of the nonvolatile memory device during a first clear operation, and may select the incompletely committed first write data and second write data among the write data stored in the write buffer and may store the incompletely committed first write data and second write data in a second storage area of the nonvolatile memory device during a second clear operation.

The controller may receive a plurality of write commands corresponding to respective write data of the host, each of the write commands may include transaction information of the corresponding write data, and the transaction information of each of the write data may include transaction Identification (ID) information, commit information, and abort information.

The controller may check the transaction ID information of the transaction information of each write data, may classify the write data in which the transaction ID information is not set as the second write data, and may classify the write data having the transaction ID information set to a specific value as the first write data.

The controller may perform a flush operation when the predetermined storage space of the write buffer is full; when it is checked that the set commit information is included in the transaction information of the respective first write data at the time point of performing the clear operation, the controller may select the committed first write data among the write data stored in the write buffer and may store the committed first write data in the first storage area during the first clear operation, and may select the incompletely committed first write data and the second write data and may store the incompletely committed first write data and the second write data in the second storage area during the second clear operation.

When it is checked that the set commit information is not included in the transaction information of the respective first write data at the time point of performing the clear operation, the controller may select the first write data and the second write data that are not completely committed among the write data stored in the write buffer during the clear operation, and may program the first write data and the second write data that are not completely committed to the nonvolatile memory device.

When it is checked that the set abort information is included in the transaction information of the respective first write data at the time point of performing the clear operation, the controller may not program the aborted first write data of the write data stored in the write buffer to the nonvolatile memory device even during the clear operation.

The nonvolatile memory device may include a plurality of memory blocks, and each of the memory blocks includes a plurality of pages, and when each of the write data is set to a size corresponding to one or more pages, the controller may set one or more specific memory blocks, which are simultaneously or sequentially accessed for one read operation, among the memory blocks, as the first memory region, and may set one or more memory blocks of other memory blocks than the specific memory block among the memory blocks, as the second memory region.

The nonvolatile memory device may include a plurality of memory blocks, each of the memory blocks including a plurality of pages, and each of the pages including a plurality of sectors, and when each of the write data is set to a size corresponding to one or more sectors, the controller may set one or more specific pages included in one or more specific memory blocks to be simultaneously or consecutively accessed among the memory blocks for one read operation as the first memory region, and may set one or more pages of other pages than the specific pages in the specific memory blocks as the second memory region.

When a merge operation for moving valid first and second write data in the first and second storage areas to another storage area of the nonvolatile memory device is performed after the first and second write data are stored in the first and second storage areas through the first and second clear operations, the controller may check whether all of the first write data stored in the first storage area are valid, and may change a method of performing the merge operation according to a result of the check.

When a merge operation is performed after first write data having transaction ID information set to a first value and first write data having transaction ID information set to a second value are stored in a first storage region, the controller may move the first write data having the transaction ID information set to the first value to a third storage region of the nonvolatile memory device, and may move valid data of the first write data having the transaction ID information set to the second value and valid data of the second write data to a fourth storage region of the nonvolatile memory device when all of the first write data having the transaction ID information set to the first value are valid and only a portion of the first write data having the transaction ID information set to the second value is valid.

In an embodiment, an operating method for a memory system including a nonvolatile memory device and a write buffer for temporarily storing a plurality of write data received from a host may include: a first checking step of checking whether first write data grouped as a transaction and second write data not grouped as a transaction are mixed and stored in a write buffer according to an order of write data received from a host; a second checking step of checking whether the first write data has been committed at a point in time when a clear operation is performed on the write buffer, when a result of the first checking step indicates that the first write data and the second write data are mixed and stored in the write buffer; and a dividing and storing step of dividing, when a result of the second checking step indicates that the first write data has been committed, a clearing operation on the write buffer into a first clearing operation and a second clearing operation which do not overlap with each other but are consecutive to each other, selecting, during the first clearing operation, the committed first write data among the write data stored in the write buffer and storing the committed first data in a first storage area of the nonvolatile memory device, and selecting, during the second clearing operation, the incompletely committed first write data and second write data among the write data stored in the write buffer and storing the incompletely committed first write data and second write data in a second storage area of the nonvolatile memory device.

The method of operation may further include receiving a plurality of write commands corresponding to respective write data from the host, each of the write commands may include transaction information of the corresponding write data, and the transaction information of the respective write data may include transaction Identification (ID) information, commit information, and abort information.

The first checking step may include: a first classification step of checking transaction ID information of transaction information of each write data and classifying the write data in which the transaction ID information is not set into second write data; a second classification step of checking transaction ID information of the transaction information of each write data and classifying the write data having the transaction ID information set to a specific value into first write data; and a third checking step of checking whether the first write data and the second write data are mixed and stored in the write buffer after the write data stored in the write buffer are classified into the first write data and the second write data by the first classifying step and the second classifying step.

The operation method may further include a clear operation step of performing a clear operation when a predetermined storage space of the write buffer is full, and when a result of the third checking step indicates that the first write data and the second write data are mixed and stored in the write buffer, the second checking step may include checking whether the set commit information is included in the transaction information of the respective first write data at a point of time when the clear operation step is performed.

The method of operation may further comprise: performing the dividing and storing step when it is checked at the second checking step that the set commit information is included in the transaction information of the respective first write data at the time point when the clearing operation step is started; and selecting the first write data and the second write data that are not completely committed among the write data stored in the write buffer and programming the selected data to the nonvolatile memory device during the clear operation, when it is checked at the second checking step that the set commit information is not included in the transaction information of the respective first write data at the time point at which the clear operation step is started.

The method of operation may further comprise: checking whether the set abort information is included in the transaction information of the respective first write data at a point of time when the clear operation step is performed, and when the check result indicates that the abort information is included, not programming the aborted first write data of the write data stored in the write buffer to the nonvolatile memory device even during the clear operation.

The non-volatile memory device may include a plurality of memory blocks, and each of the memory blocks includes a plurality of pages, and the operation method may further include: when each of the write data is set to a size corresponding to one or more pages, one or more specific memory blocks among the memory blocks are simultaneously or sequentially accessed for one read operation are set as a first memory area, and one or more memory blocks among other memory blocks except for a specific memory block among the memory blocks are set as a second memory area.

The non-volatile memory device may include a plurality of memory blocks, each of the memory blocks including a plurality of pages, and each of the pages including a plurality of sectors, the method of operation may further include: when each write data is set to a size corresponding to one or more sectors, one or more specific pages included in one or more specific memory blocks among the memory blocks to be accessed simultaneously or consecutively for one read operation are set as a first memory region, and one or more pages among other pages except for a specific page in the specific memory blocks are set as a second memory region.

The operation method may further include, when a merge operation for moving the valid first write data and second write data in the first storage area and the second storage area to another storage area of the nonvolatile memory device is performed after the first write data and the second write data are stored in the first storage area and the second storage area through the first clear operation and the second clear operation in the dividing and storing step, checking whether all of the first write data stored in the first storage area are valid; and a merging operation step of changing a method for performing the merging operation according to a result of the fourth checking step.

When the merge operation is performed after the first write data having the transaction ID information set to the first value and the first write data having the transaction ID information set to the second value are stored in the first storage area in the second sorting step, the merge operation step may include moving the first write data having the transaction ID information set to the first value to a third storage area of the nonvolatile memory device, and then moving the valid data of the first write data having the transaction ID information set to the second value and the valid data of the second write data to a fourth storage area of the nonvolatile memory device when it is checked in the fourth checking step that the first write data having the transaction ID information set to the first value are all valid and that only a part of the first write data having the transaction ID information set to the second value is valid.

In an embodiment, a memory system may include: a memory device including a first storage area and a second storage area; a controller comprising a write buffer, the controller adapted to: receiving and storing a plurality of write data including a plurality of transaction data and at least one normal data in a write buffer; when the write buffer is full, determining whether each of the plurality of transaction data is transaction commit data or transaction abort data; clearing transaction commit data in a first storage area of a memory device; and clearing the transaction abort data and the normal data in the second storage area of the memory device.

Drawings

These and other features and advantages of the present invention will become apparent to those skilled in the art to which the present invention pertains in the following detailed description, taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram illustrating a data processing system including a memory system according to an embodiment of the present invention;

FIG. 2 is a diagram showing a memory device employed in the memory system shown in FIG. 1;

FIG. 3 is a circuit diagram illustrating a memory cell array of a memory block in the memory device shown in FIG. 2;

FIG. 4 is a diagram illustrating a three-dimensional structure of the memory device shown in FIG. 2;

fig. 5 and 6A to 6D are diagrams illustrating an operation of storing a plurality of write data grouped into transactions in a nonvolatile memory device in a memory system according to an embodiment;

FIG. 7 is a diagram showing a method of performing a merge operation after multiple write data grouped into transactions are stored in a non-volatile memory;

FIG. 8 is a flowchart illustrating an operation of storing a plurality of write data grouped into transactions in a nonvolatile memory device of a memory system according to the present embodiment;

fig. 9 to 17 are diagrams showing application examples of the data processing system according to the respective embodiments of the present invention.

Detailed Description

Various embodiments of the present invention are described in more detail below with reference to the accompanying drawings. It is to be noted, however, that the present invention may be embodied in various other embodiments, forms and modifications thereof, and should not be construed as limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the invention to those skilled in the art to which the invention pertains. Throughout this disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, a first element described below may also be referred to as a second element or a third element without departing from the spirit and scope of the present invention.

The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of embodiments.

It will be further understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or one or more intervening elements may be present. In addition, it will also be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and "including," when used in this specification, specify the presence of stated elements, but do not preclude the presence or addition of one or more other elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Unless defined otherwise, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs based on the present disclosure. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the present disclosure and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be practiced without some or all of these specific details. In other instances, well known process structures and/or processes have not been described in detail in order to not unnecessarily obscure the present invention.

It is also noted that, in some instances, features or elements described in connection with one embodiment may be used alone or in combination with other features or elements of another embodiment unless expressly stated otherwise, as would be apparent to one skilled in the relevant art.

FIG. 1 is a block diagram illustrating a data processing system 100 including a memory system 110 according to an embodiment of the invention.

Referring to FIG. 1, a data processing system 100 may include a host 102 and a memory system 110.

The host 102 may include, for example, portable electronic devices such as mobile phones, MP3 players, and laptop computers, or non-portable electronic devices such as desktop computers, game consoles, Televisions (TVs), and projectors.

The memory system 110 is operable to store data for the host 102 in response to requests by the host 102. Non-limiting examples of the memory system 110 may include a Solid State Drive (SSD), a multimedia card (MMC), a Secure Digital (SD) card, a universal memory bus (USB) device, a universal flash memory (UFS) device, a Compact Flash (CF) card, a Smart Media Card (SMC), a Personal Computer Memory Card International Association (PCMCIA) card, and a memory stick. The MMC may include an embedded MMC (emmc), a reduced-size MMC (RS-MMC), and a micro MMC. The SD card may include a mini SD card and a micro SD card.

The memory system 110 may be implemented by various types of storage devices. Non-limiting examples of storage devices included in memory system 110 may include volatile memory devices such as Dynamic Random Access Memory (DRAM) and static ram (sram), and non-volatile memory devices such as the following: read-only memory (ROM), mask ROM (mrom), programmable ROM (prom), erasable programmable ROM (eprom), electrically erasable programmable ROM (eeprom), ferroelectric RAM (fram), phase change RAM (pram), magnetic RAM (mram), resistive RAM (RRAM or ReRAM), and flash memory. The flash memory may have a three-dimensional (3D) stack structure.

Memory system 110 may include a controller 130 and a memory device 150. The memory device 150 may store data for the host 102, and the controller 130 may control the storage of data into the memory device 150.

The controller 130 and the memory device 150 may be integrated into one semiconductor device, and one semiconductor device may be included in various types of memory systems as shown above.

Non-limiting application examples of the memory system 110 may include a computer, an ultra mobile pc (umpc), a workstation, a netbook, a Personal Digital Assistant (PDA), a portable computer, a web tablet, a tablet computer, a wireless phone, a mobile phone, a smart phone, an electronic book, a Portable Multimedia Player (PMP), a portable game machine, a navigation system, a black box, a digital camera, a Digital Multimedia Broadcasting (DMB) player, a 3-dimensional television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device constituting a data center, a device capable of transmitting/receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, A Radio Frequency Identification (RFID) device or one of the various components that make up the computing system.

The memory device 150 may be a non-volatile memory device, and may retain data stored therein even if power is not supplied. The memory device 150 may store data provided from the host 102 through a write operation and provide data stored therein to the host 102 through a read operation. Memory device 150 may include a plurality of memory dies (not shown), each memory die including a plurality of planes (not shown), each plane including a plurality of memory blocks 152-156, each of memory blocks 152-156 may include a plurality of pages, and each of the pages may include a plurality of memory cells coupled to a wordline.

The controller 130 may control the memory device 150 in response to a request from the host 102. For example, the controller 130 may provide data read from the memory device 150 to the host 102 and store data provided by the host 102 into the memory device 150. For this operation, the controller 130 may control a read operation, a write operation, a program operation, and an erase operation of the memory device 150.

Controller 130 may include a host interface (I/F) unit 132, a processor 134, an Error Correction Code (ECC) unit 138, a Power Management Unit (PMU)140, a memory interface (I/F) (or NAND Flash Controller (NFC))142, and a memory 144, all operatively coupled by an internal bus.

The host interface unit 132 may be configured to process commands and data for the host 102 and may communicate with the host 102 through one or more of a variety of interface protocols, such as: universal Serial Bus (USB), multi-media card (MMC), peripheral component interconnect express (PCI-e or PCIe), Small Computer System Interface (SCSI), serial SCSI (sas), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

The ECC unit 138 may detect and correct errors included in data read from the memory device 150. In other words, the ECC unit 138 may perform an error correction encoding process on data read from the memory device 150 through an ECC code used during the ECC encoding process. Based on the results of the error correction encoding process, the ECC unit 138 may output a signal, such as an error correction success/failure signal. When the number of error bits is greater than the threshold number of correctable error bits, ECC unit 138 may not be able to correct the error bits and may output an error correction fail signal.

The ECC unit 138 may perform error correction by coded modulation such as: low Density Parity Check (LDPC) codes, Bose-Chaudhri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, Recursive Systematic Codes (RSC), Trellis Coded Modulation (TCM), and Block Coded Modulation (BCM). However, the ECC unit 138 is not limited thereto. ECC unit 138 may include all circuits, modules, systems, or devices used for error correction.

PMU 140 may provide and manage power for controller 130.

NFC 142 may serve as a memory or storage interface for interfacing controller 130 and memory device 150 such that controller 130 may control memory device 150 in response to requests from host 102. When memory device 150 is a flash memory or specifically a NAND flash memory, NFC 142 may generate control signals for memory device 150 and process data to be provided to memory device 150 under the control of processor 134. NFC 142 may serve as an interface (e.g., a NAND flash interface) to process commands and data between controller 130 and memory device 150. Specifically, NFC 142 may support data transfer between controller 130 and memory device 150.

The memory 144 may serve as a working memory for the memory system 110 and the controller 130, and store data for driving the memory system 110 and the controller 130. The controller 130 may control the memory device 150 to perform read operations, write operations, program operations, and erase operations in response to requests from the host 102. The controller 130 may provide data read from the memory device 150 to the host 102, and may store data provided from the host 102 in the memory device 150. Memory 144 may store data needed by controller 130 and memory device 150 to perform these operations.

The memory 144 may be implemented by a volatile memory. For example, the memory 144 may be implemented by Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The memory 144 may be provided within or external to the controller 130. Fig. 1 illustrates the memory 144 disposed within the controller 130. In an embodiment, the memory 144 may be implemented by an external volatile memory having a memory interface that transfers data between the memory 144 and the controller 130.

Processor 134 may control the overall operation of memory system 110. Processor 134 may drive firmware to control the overall operation of memory system 110. The firmware may be referred to as a Flash Translation Layer (FTL).

Processor 134 of controller 130 may include a management unit (not shown) for performing bad block management operations for memory device 150. The management unit may perform a bad block management operation of checking a bad block, in which a program failure occurs due to characteristics of the NAND flash memory during a program operation, among the plurality of memory blocks 152 to 156 included in the memory device 150. The management unit may write the data of the bad block, which failed to be programmed, to the new memory block. In the memory device 150 having the 3D stack structure, the bad block management operation may reduce the utilization efficiency of the memory device 150 and the reliability of the memory system 110. Therefore, bad block management operations need to be performed more reliably.

Fig. 2 is a diagram illustrating a memory device 150 of the memory system 110 of fig. 1.

Referring to FIG. 2, the memory device 150 may include a plurality of memory blocks 0 to N-1, and among the blocks 0 to N-1May include, for example, 2^MA plurality of pages of a plurality of pages, the number of pages being variable depending on the circuit design. The memory cells included in the respective memory blocks 0 to N-1 may be one or more of single-layer cells (SLC) storing 1-bit data or multi-layer cells (MLC) storing 2-bit or more data. In an embodiment, memory device 150 may include multiple Triple Layer Cells (TLCs) that each stores 3-bit data. In another embodiment, memory device 150 may include a plurality of four-layer cells (QLCs) that each stores 4-bit data.

Fig. 3 is a circuit diagram showing a memory cell array of the memory block 330 in the memory device 150.

Referring to fig. 3, a memory block 330, which may correspond to any one of a plurality of memory blocks 152 through 156 included in a memory device 150 of a memory system 110, may include a plurality of cell strings 340 coupled to a plurality of respective bit lines BL0 through BLm-1. In the cell string 340, each column may include one or more drain select transistors DST and one or more source select transistors SST. Between the drain select transistor DST and the source select transistor SST, a plurality of memory cells MC0 through MCn-1 may be coupled in series. In an embodiment, each of the memory cell transistors MC0 through MCn-1 may be implemented by an MLC capable of storing multiple bits of data information. Each of the cell strings 340 may be electrically coupled to a respective bit line among a plurality of bit lines BL0 through BLm-1. For example, as shown in FIG. 3, the first cell string is coupled to first bit line BL0, and the last cell string is coupled to last bit line BLm-1.

Although FIG. 3 shows a NAND flash memory cell, the invention is not limited in this manner. Note that the memory cells may be NOR flash memory cells, or include hybrid flash memory cells in which two or more kinds of memory cells are combined. Further, it is noted that the memory device 150 may be a flash memory device including a conductive floating gate as a charge storage layer or a charge extraction flash (CTF) memory device including an insulating layer as a charge storage layer.

The memory device 150 may further include a voltage supply unit 310 that supplies a word line voltage including a program voltage, a read voltage, and a pass voltage supplied to the word line according to an operation mode. The voltage generating operation of the voltage supply unit 310 may be controlled by a control circuit (not shown). Under the control of the control circuit, the voltage supply unit 310 may select one of the memory blocks (or sectors) of the memory cell array, select one of the word lines of the selected memory block, and supply a word line voltage to the selected word line and unselected word lines as necessary.

The memory device 150 may include read and write (read/write) circuitry 320 controlled by control circuitry. During verify/normal read operations, read/write circuits 320 may be used as sense amplifiers for reading data from the memory cell array. During a programming operation, the read/write circuits 320 may function as write drivers that drive the bit lines according to data to be stored in the memory cell array. During a program operation, the read/write circuits 320 may receive data to be stored into the memory cell array from a buffer (not shown) and drive the bit lines according to the received data. The read/write circuits 320 may include a plurality of Page Buffers (PBs) 322-326 corresponding to columns (or bit lines) or column pairs (or bit line pairs), respectively. Each of the page buffers 322-326 may include a plurality of latches (not shown).

Fig. 4 is a diagram illustrating a three-dimensional (3D) structure of the memory device 150 in fig. 2.

The memory device 150 may be implemented by a two-dimensional (2D) or 3D memory device. Specifically, as shown in fig. 4, the memory device 150 may be implemented by a nonvolatile memory device having a 3D stack structure. When the memory device 150 has a 3D structure, the memory device 150 may include a plurality of memory blocks BLK0 through BLKN-1, each of which has a 3D structure (or a vertical structure).

Fig. 5 and 6A to 6D are diagrams illustrating an operation of storing a plurality of write data grouped into transactions in a nonvolatile memory device in a memory system according to an embodiment.

FIG. 5 shows data processing system 100 including host 102 and memory system 110, with reference to the configuration of data processing system 100 shown in FIG. 1.

Referring to fig. 5, as described with reference to fig. 1, the memory system 110 may include a controller 130 and a memory device 150.

Further, as described with reference to FIG. 1, memory device 150 may include a plurality of memory blocks 152, 154, and 156. Memory blocks 152, 154, and 156 may include a plurality of pages P <10,11,12,13,14,15>, P <20,21,22,23,24,25>, and P <30,31,32,33,34,35>, respectively.

For reference, FIG. 5 shows that memory system 110 includes only one non-volatile memory device 150. However, for convenience of description, this configuration is merely an example, and a large number of nonvolatile memory devices may be included in the memory system 110. Fig. 5 shows a configuration in which the nonvolatile memory device 150 includes three memory blocks 152, 154, and 156. However, this is merely an example for convenience, and a greater or lesser number of memory blocks may be included in non-volatile memory device 150. Further, FIG. 5 shows that memory blocks 152, 154, and 156 include six pages P <10,11,12,13,14,15>, P <20,21,22,23,24,25>, and P <30,31,32,33,34,35>, respectively. However, this is merely an example for convenience, and a greater or lesser number of pages may be included in each of the memory blocks 152, 154, and 156.

Fig. 1 shows the host interface 132, the processor 134, the ECC unit 138, the power management unit 140, and the NAND flash controller 142 included in the controller 130, and fig. 5 shows that the respective units are not included in the controller 130. However, these units are omitted for convenience only, and may be included in the controller 130.

The memory system 110 described below may perform an operation of processing write data WDATA grouped into transactions.

In various embodiments, grouping write data WDATA into a transaction may indicate that multiple write data WDATA packets used for the same purpose among write data WDATA are one transaction.

For example, data for correcting, adding, and updating data stored in a database may be grouped into transactions according to respective uses. At this time, data for correcting the database may be set as one transaction group, and data for adding to the database may be set as another transaction group.

Thus, when write data WDATA grouped into one transaction is transferred from host 102 to memory system 110, write data WDATA may only have a commit state or an abort state. When write data WDATA has a commit status, it may indicate that all write data WDATA are valid because all write data WDATA have been normally transferred and stored. On the other hand, when write data WDATA has a suspension state, it may indicate that any one of write data WDATA is not normally transferred and stored or that all write data WDATA is invalid according to a suspension request of host 102. That is, write data WDATA grouped into one transaction may be of importance only if write data WDATA has a commit status as follows: in this commit state, all write data WDATA are valid since all write data WDATA have been normally transferred and stored.

For example, only when all of the plurality of first write data TRAN _ WDATA are normally transferred from the host 102 and stored in the memory system 110, and no abort request is provided from the host 102, the first write data TRAN _ WDATA grouped as a transaction among the write data WDATA transferred from the host 102 to the memory system 110 may be determined to have a commit state in the memory system 110. If any one of the first write data TRAN _ WDATA is not normally transferred and stored, or an abort request is provided from the host 102, all of the first write data TRAN _ WDATA in the memory system 110 may be determined to have an abort state.

The above-described operation of managing the first write data TRAN _ WDATA grouped into one transaction by distinguishing the first write data TRAN _ WDATA into the commit state or the abort state may be generally referred to as an operation for guaranteeing atomicity (atomic) transactions.

Referring again to fig. 5, the controller 130 may include a non-volatile memory device 150, a volatile memory device 144, and a transaction manager 1300.

Non-volatile memory device 150 may include a plurality of memory blocks 152, 154, and 156. Memory blocks 152, 154, and 156 may include a plurality of pages P <10,11,12,13,14,15>, P <20,21,22,23,24,25>, and P <30,31,32,33,34,35>, respectively. Each of the pages may include a plurality of sections N < 1: 4 >.

Volatile memory device 144 may include a write buffer 1442. At operation 1443, the write buffer 1442 may temporarily store a plurality of write data WDATA input from the host 102.

At operation 1443, the controller 130 may perform a flush operation on the write buffer 1442 in response to the predetermined storage space of the write buffer 1442 being full. For example, controller 130 may clear write buffer 1442 in response to all storage space in volatile memory device 144 designated as write buffer 1442 being full.

In operation 1301, transaction manager 1300 may classify write data WDATA into first write data TRAN _ WDATA grouped into a transaction and second write data NMAL _ WDATA not grouped into a transaction. Write data WDATA may be input from host 102 and stored in write buffer 1442. That is, after write data WDATA is input from host 102 and stored in write buffer 1442, transaction manager 1300 may classify write data WDATA into first write data TRAN _ WDATA grouped into a transaction and second write data NMAL _ WDATA not grouped into a transaction before write data WDATA is stored in non-volatile memory device 150.

The write data WDATA stored in the write buffer 1442 may be sequentially stored according to the order of write data WDATA input from the host 102. Thus, write data WDATA grouped as transactions, i.e., first write data TRAN _ WDATA, and write data WDATA not grouped as transactions, i.e., second write data NMAL _ WDATA, may be mixed and stored in write buffer 1442 only according to the order of write data WDATA input from host 102.

Accordingly, transaction manager 1300 may classify write data WDATA mixed and stored in write buffer 1442 according to the order of write data WDATA input from host 102 into first write data TRAN _ WDATA grouped into a transaction and second write data NMAL _ WDATA not grouped into a transaction, depending on whether write data WDATA is grouped into a transaction.

More specifically, operation 1301 will be described as follows.

When write data WDATA is input from the host 102, write commands WCMD corresponding to the respective write data WDATA may be input together.

Write command WCMD may include transaction information TRINFO of write data WDATA corresponding to each write command WCMD.

Transaction information TRINFO of write data WDATA may include transaction Identification (ID) information TRID, transaction commit information CMIF, and transaction abort information ABIF.

At operation 1021, host 102 may generate write command WCMD including transaction information TRINFO, which includes transaction ID information TRID, transaction commit information CMIF, and transaction abort information ABIF. The write command WCMD may be input to the controller 130 of the memory system 110 together with write data WDATA.

Accordingly, the controller 130 of the memory system 110 may store write data WDATA in the write buffer 1442 in response to the write command WCMD. Then, the controller 130 may store the write data WDATA stored in the write buffer 1442 into the nonvolatile memory device 150 by performing a clear operation on the write buffer 1442 in response to the predetermined storage space of the write buffer 1442 being full.

In operation 1304, the transaction manager 1300 included in the controller 130 may check the transaction ID information TRID of the transaction information TRINFO included in the write command WCMD. Further, transaction manager 1300 may classify write data WDATA stored in write buffer 1442 into first write data TRAN _ WDATA grouped into transactions and second write data NMAL _ WDATA not grouped into transactions.

That is, the transaction manager 1300 may check the transaction ID information TRID of the transaction information TRINFO of the write data WDATA stored in the write buffer 1442. When write data WDATA has transaction ID information TRID set to a specific value, transaction manager 1300 may classify write data WDATA into first write data TRAN _ WDATA.

When the transaction ID information TRID is not set in the write data WDATA, the transaction manager 1300 may check the transaction ID information TRID of the transaction information TRINFO of the write data WDATA stored in the write buffer 1442 and classify the write data WDATA into the second write data NMAL _ WDATA.

For example, write data WDATA having the first value of transaction ID information TRID among write data WDATA stored in write buffer 1442 is first write data TRAN _ WDATA grouped into a first transaction.

Similarly, write data WDATA of which transaction ID information TRID has the second value among write data WDATA stored in write buffer 1442 is first write data TRAN _ WDATA grouped into the second transaction.

On the other hand, write data WDATA of which transaction ID information TRID is not set to any value among write data WDATA stored in write buffer 1442 is second write data NMAL _ WDATA that is not grouped as a transaction.

When the transaction ID information TRID is not set to any value, it may indicate that the transaction ID information TRID is set to a predefined initial value or an insignificant value as the transaction ID information.

In operation 1302, the transaction manager 1300 may check whether the first write data TRAN _ WDATA stored in the write buffer 1442 has been committed at the point in time when the write buffer 1442 is cleared.

At this time, first write data TRAN _ WDATA classified into data grouped into a transaction among write data WDATA stored in write buffer 1442 by operation 1301 needs to be written into storage blocks 152, 154, and 156 in different manners depending on whether or not first write data TRAN _ WDATA has been committed due to the characteristics of the data grouped into a transaction.

For this reason, the transaction manager 1300 may first check whether the first write data TRAN _ WDATA stored in the write buffer 1442 has been committed at the point in time when the write buffer 1442 is cleared.

For example, when the set commit information CMIF is included in the transaction information TRINFO of the first write data TRAN _ WDATA grouped as the first transaction and stored in the write buffer 1442, it may be determined that the first write data TRAN _ WDATA grouped as the first transaction has been completely committed in operation 1306.

When the set commit information CMIF is not included in the transaction information TRINFO of the first write data TRAN _ WDATA grouped as the second transaction and stored in the write buffer 1442, it may be determined that the first write data TRAN _ WDATA grouped as the second transaction is not completely committed in operation 1308.

When the set abort information ABIF is included in the transaction information TRINFO of the first write data TRAN _ WDATA grouped into the third transaction and stored in the write buffer 1442, it may be determined that the first write data TRAN _ WDATA grouped into the third transaction is aborted at operation 1307.

In various embodiments, each of the first write data TRAN _ WDATA grouped into the first transaction may be in a state in which the transaction ID information TRID of the transaction information TRINFO has a first value. Further, each of the first write data TRAN _ WDATA grouped into the second transaction may be in a state in which the transaction ID information TRID of the transaction information TRINFO has the second value. Further, each of the first write data TRAN _ WDATA grouped into the third transaction may be in a state in which the transaction ID information TRID of the transaction information TRINFO has a third value.

In this way, the first write data TRAN _ WDATA stored in the write buffer 1442 can be distinguished into different transaction groups depending on which value the transaction ID information TRID of the transaction information TRINFO is specified as.

That is, the first write data TRAN _ WDATA stored in the write buffer 1442 may include a plurality of transaction groups mixed therein. Among multiple transaction groups, a transaction may have been completely committed, another transaction may not have been completely committed, and another transaction may be aborted.

Through operation 1302, the transaction manager 1300 may check whether the first write data TRAN _ WDATA stored in the write buffer 1442 has been committed. Then, the transaction manager 1300 may perform the flushing operation only on the write buffer 1442 according to the check result, or perform the first flushing operation FLUSH1 and the second flushing operation FLUSH2, which do not overlap each other but are consecutive to each other, respectively.

Specifically, when the result of operation 1302 indicates that the committed first write data TRAN _ WDATA is included in the first write data TRAN _ WDATA (operation 1306), the transaction manager 1300 may perform the first FLUSH operation FLUSH1 and the second FLUSH operation FLUSH2, which do not overlap with each other but are consecutive to each other, respectively, as FLUSH operations to the write buffer 1442. In other words, when it is checked that the set commit information CMIF is included in the transaction information TRINFO of the respective first write data TRAN _ WDATA, the transaction manager 1300 may perform the first FLUSH operation FLUSH1 and the second FLUSH operation FLUSH2, respectively.

First clear operation FLUSH1 may indicate operation 1309, which includes selecting committed first write data TRAN _ WDATA among first write data TRAN _ WDATA stored in write buffer 1442, and storing the selected data in a "first storage area" of non-volatile memory device 150.

Second clear operation FLUSH2 may indicate operation 1310, which includes selecting incompletely committed first write data TRAN _ WDATA among first write data TRAN _ WDATA and second write data NMAL _ WDATA stored in write buffer 1442, and then storing the selected data in a "second storage area" of non-volatile memory device 150.

That is, in operation 1309, when the result of operation 1302 indicates that the committed first write data TRAN _ WDATA is included in the first write data TRAN _ WDATA stored in the write buffer 1442, the transaction manager 1300 may select only the committed first write data TRAN _ WDATA through the first clear operation FLUSH1 and store the selected data in the "first storage area" of the nonvolatile memory device 150. After the first FLUSH operation FLUSH1, the transaction manager 1300 may select the first write data TRAN _ WDATA and the second write data NMAL _ WDATA, which are not completely committed, and store the selected data in the "second storage region" of the nonvolatile memory device 150 through the second FLUSH operation FLUSH2 in operation 1310.

Accordingly, when the committed first write data TRAN _ WDATA is included in the first write data TRAN _ WDATA stored in the write buffer 1442 (operation 1306), the transaction manager 1300 may select only the committed first write data TRAN _ WDATA and store the selected data in the "first storage area" of the nonvolatile memory device 150. Further, the transaction manager 1300 may select the incomplete first write data TRAN _ WDATA and the second write data and then store the selected data in the "second storage region" of the nonvolatile memory device 150.

For example, first write data TRAN _ WDATA grouped into a first transaction, first write data TRAN _ WDATA grouped into a second transaction, and second write data NMAL _ WDATA are stored in write buffer 1442. Further, the set commit information CMIF is included in the transaction information TRINFO of the respective first write data TRAN _ WDATA grouped into the first transaction. Further, the set commit information CMIF and the set abort information ABIF are not included in the transaction information TRINFO of the respective first write data TRAN _ WDATA grouped into the second transaction.

In this case, through operation 1302, the transaction manager 1300 may check that the first write data TRAN _ WDATA grouped into the first transaction and stored in the write buffer 1442 has been completely committed and the first write data TRAN _ WDATA grouped into the second transaction has not been completely committed.

Accordingly, through operation 1309, the transaction manager 1300 may store the first write data TRAN _ WDATA grouped into the first transaction in the "first storage area" of the nonvolatile memory device 150 by performing the first clear operation FLUSH 1. Then, the transaction manager 1300 may store the first write data TRAN _ WDATA and the second write data NMAL _ WDATA grouped into the second transaction in the "second storage region" of the nonvolatile memory device 150 through operation 1310.

When the result of operation 1302 indicates that the committed first write data TRAN _ WDATA is not included in the first write data TRAN _ WDATA (operation 1308), transaction manager 1300 may perform a flush operation only on write buffer 1442. In other words, when the set commit information CMIF is not included in the transaction information TRINFO of the respective first write data TRAN _ WDATA, the transaction manager 1300 may perform the flushing operation only on the write buffer 1442 even if the transaction information TRINFO is all checked. Specifically, at operation 1312, transaction manager 1300 may select incompletely committed first write data TRAN _ WDATA and second write data NMAL _ WDATA among write data WDATA stored in write buffer 1442, and then store the selected data in non-volatile memory device 150.

For example, first write data TRAN _ WDATA grouped into a first transaction, first write data TRAN _ WDATA grouped into a second transaction, and second write data NMAL _ WDATA are stored in write buffer 1442. Further, the set commit information CMIF and the set abort information ABIF are not included in the transaction information TRINFO of the respective first write data TRAN _ WDATA grouped as the first transaction, nor are they included in the transaction information TRINFO of the respective first write data TRAN _ WDATA grouped as the second transaction.

In this case, through operation 1302, the transaction manager 1300 may check that the first write data TRAN _ WDATA grouped as the first transaction and stored in the write buffer 1442 is not completely committed and that the first write data TRAN _ WDATA grouped as the second transaction is not completely committed.

Accordingly, transaction manager 1300 may store first write data TRAN _ WDATA grouped into a first transaction, first write data TRAN _ WDATA grouped into a second transaction, and second write data NMAL _ WDATA in non-volatile memory device 150 by performing a clear operation with operation 1312.

When the result of operation 1302 indicates that the set abort information ABIF is included in the transaction information TRINFO of the respective first write data TRAN _ WDATA (operation 1307), at operation 1311, the transaction manager 1300 may perform a clear operation only on the write buffer 1442, but not program the aborted first write data TRAN _ WDATA of the write data WDATA stored in the write buffer 1442 to the nonvolatile memory device 150 even during the clear operation.

For example, first write data TRAN _ WDATA grouped into a first transaction, first write data TRAN _ WDATA grouped into a second transaction, and second write data NMAL _ WDATA are stored in write buffer 1442. Further, the set commit information CMIF and the set abort information ABIF are not included in the transaction information TRINFO of the respective first write data TRAN _ WDATA grouped as the first transaction, and the set abort information ABIF is included in the transaction information TRINFO of the respective first write data TRAN _ WDATA grouped as the second transaction.

In this case, through operation 1302, the transaction manager 1300 may check that the first write data TRAN _ WDATA grouped as the first transaction and stored in the write buffer 1442 is not completely committed, and the first write data TRAN _ WDATA grouped as the second transaction is aborted.

Accordingly, the transaction manager 1300 may perform the clear operation through operation 1311, but does not store the first write data TRAN _ WDATA grouped into the second transaction in the nonvolatile memory device 150 even during the clear operation. That is, during a clear operation, the transaction manager 1300 may select only the first write data TRAN _ WDATA and the second write data NMAL _ WDATA grouped into the first transaction and store the selected data in the nonvolatile memory device 150.

Fig. 6A to 6D show that the committed first write data TRAN _ WDATA "0, 1,2, and 3" and second write data NMAL _ WDATA "a, B, C, and D" are mixed and stored in the write buffer 1442.

Further, fig. 6A and 6B illustrate that the transaction manager 1300 stores the first write data TRAN _ WDATA "0, 1,2, and 3" in the "first storage area" of the nonvolatile memory device 150 during the first clear operation FLUSH1, and stores the second write data NMAL _ WDATA "a, B, C, and D" in the "second storage area" of the nonvolatile memory device 150 during the second clear operation FLUSH2, through operation 1303 of fig. 5. That is, the set commit information CMIF may be included in the transaction information TRINFO corresponding to the first write data TRAN _ WDATA "0, 1,2, and 3". Accordingly, the transaction manager 1300 may perform operation 1303.

Fig. 6A shows how "first and second storage areas" of the nonvolatile memory device 150 used in operation 1303 are set when each write data WDATA stored in the write buffer 1442 is set to a size corresponding to one or more "sectors".

Fig. 6B shows how "first and second storage areas" of the nonvolatile memory device 150 used in operation 1303 are set when each write data WDATA stored in the write buffer 1442 is set to a size corresponding to one or more "pages".

As described above with reference to fig. 5, non-volatile memory device 150 may include a plurality of memory blocks 152, 154, and 156. Memory blocks 152, 154, and 156 may include a plurality of pages P <10,11,12,13,14,15>, P <20,21,22,23,24,25>, and P <30,31,32,33,34,35>, respectively. Each of pages P <10,11,12,13,14,15>, P <20,21,22,23,24,25> and P <30,31,32,33,34,35> may include a plurality of sections N < 1: 4 >.

Fig. 6A shows that each write data WDATA stored in the write buffer 1442 is set to a size corresponding to one or more "sectors". As such, each write data WDATA stored in the write buffer 1442 may be set to a size corresponding to one or more sectors smaller than a unit page.

Accordingly, the controller 130 may set one or more "specific pages" as "first storage regions". One or more specific pages may be included in one or more "specific memory blocks" among memory blocks 152, 154, and 156, which are accessed simultaneously or sequentially for one read operation. In addition, the controller 130 may set one or more pages as the "second storage area". In addition to the "specific page" set as the "first storage region" in the "specific memory block", one or more pages may be included in other pages.

At this time, one or more "specific memory blocks" may indicate one or more memory blocks that can be simultaneously or sequentially accessed for one read operation. That is, one or more "specific memory blocks" may indicate one memory block selected for one read operation, indicate that two or more memory blocks simultaneously or consecutively selected for one read operation are grouped into a super block, or indicate two or more memory blocks that can be consecutively accessed for one read operation by the interleaving method.

For example, each of "0, 1,2, a, B, C, D, and 3", which are a total of eight write data WDATA stored in the write buffer 1442, has a size corresponding to one sector. Thus, the write buffer 1442 has a size corresponding to eight sections in total. In this case, since one page includes four sectors, the write buffer 1442 may have a size corresponding to a total of two pages.

Accordingly, the controller 130 may set the first memory block 152 of the memory blocks 152, 154, and 156 as a "specific memory block". Further, the controller 130 may set the first page P10 of the first memory block 152 set as the "specific memory block" as the "first memory area". Further, the controller 130 may set any one page P11 of the other pages P <11,12,13,14,15> as the "second storage region", and the other pages P <11,12,13,14,15> are pages excluding the first page P10 set as the "first storage region" in the first storage block 152 set as the "specific storage block".

In this state, the transaction manager 1300 included in the controller 130 may perform operation 1303. Operation 1303 may include selecting "0, 1,2, and 3" corresponding to first write data TRAN _ WDATA grouped as a transaction among eight write data WDATA of "0, 1,2, a, B, C, D, and 3" stored in write buffer 1442. Further, operation 1303 may include storing the selected data in four sectors included in first page P10 of first storage block 152 through first clear operation FLUSH 1. Further, operation 1303 may include selecting second write data NMAL _ WDATA "a, B, C, and D" and storing the selected data in four sectors included in second page P11 of first memory block 152 through a second clear operation FLUSH 2.

In short, first write data TRAN _ WDATA grouped into transactions and second write data NMAL _ WDATA not grouped into transactions may be mixed and stored in write buffer 1442 according to the order of write data input from host 102. However, the transaction manager 1300 may perform the first and second FLUSH operations FLUSH1 and FLUSH2, respectively, as a FLUSH operation of the write buffer 1442 through operation 1303. Accordingly, a first storage space in which first write data TRAN _ WDATA grouped as a transaction is stored, i.e., first page P10 of first storage block 152, and a second storage space in which second write data NMAL _ WDATA not grouped as a transaction is stored, i.e., second page P11 of first storage block 152, may be physically separated from each other in nonvolatile memory device 150.

Fig. 6B shows that each write data WDATA stored in the write buffer 1442 is set to a size corresponding to one or more "pages". In this way, each write data WDATA stored in the write buffer 1442 can be set to a size corresponding to one or more pages smaller than a unit memory block.

Accordingly, the controller 130 may set one or more "specific memory blocks" as "first memory regions". One or more "particular memory blocks" among memory blocks 152, 154, and 156 may be accessed simultaneously or sequentially for a read operation. In addition, the controller 130 may set one or more memory blocks as "second memory regions". One or more memory blocks may be included in memory blocks other than the "specific memory block" set as the "first memory region" among the memory blocks 152, 154, and 156.

At this time, one or more "specific memory blocks" may indicate one or more memory blocks that can be simultaneously or sequentially accessed for one read operation. That is, the one or more "specific memory blocks" may indicate one memory block selected for one read operation, indicate that two or more memory blocks simultaneously or consecutively selected for one read operation are grouped into a super block, or indicate that two or more memory blocks consecutively accessible for one read operation may be accessed by an interleaving method.

For example, each of "0, 1,2, a, B, C, D, and 3", which are a total of eight write data WDATA stored in the write buffer 1442, has a size corresponding to one page. Thus, the write buffer 1442 has a size corresponding to a total of eight pages.

Accordingly, the controller 130 may select the first memory block 152 of the memory blocks 152, 154, and 156 as a "specific memory block" and set the selected memory block as a "first memory region". Further, the controller 130 may set any one of the memory blocks 154 as a "second memory region". Among the memory blocks 152, 154, and 156, the memory block 154 may be included in other memory blocks 154 and 156 except for the first memory block 152 selected as a "specific memory block" and set as a "first memory region".

In this state, the transaction manager 1300 included in the controller 130 may perform operation 1303. Operation 1303 may include selecting "0, 1,2, and 3" corresponding to first write data TRAN _ WDATA grouped as a transaction among eight write data WDATA "0, 1,2, a, B, C, D, and 3" stored in write buffer 1442, and storing the selected data in four pages P <10,11,12,13> included in first storage block 152 through first FLUSH operation FLUSH 1. Further, operation 1303 may include selecting second write data NMAL _ WDATA "a, B, C, and D" and storing the selected data in four pages P <20,21,22,23> included in second storage block 154 through a second clear operation FLUSH 2.

In short, first write data TRAN _ WDATA grouped into transactions and second write data NMAL _ WDATA not grouped into transactions may be mixed and stored in write buffer 1442 according to the order of write data input from host 102. However, the transaction manager 1300 may perform the first and second FLUSH operations FLUSH1 and FLUSH2, respectively, as a FLUSH operation of the write buffer 1442 through operation 1303. Thus, a first storage space, i.e., first storage block 152, in which first write data TRAN _ WDATA grouped as a transaction is stored, and a second storage space, i.e., second storage block 154, in which second write data NMAL _ WDATA not grouped as a transaction is stored, may be physically separated from each other in non-volatile memory device 150.

Fig. 6C shows that transaction manager 1300 does not store first write data TRAN _ WDATA "0, 1,2, 3" in nonvolatile memory device 150 by operation 1311 of fig. 5, but selects only second write data NMAL _ WDATA "a, B, C, and D", and then stores the selected data in nonvolatile memory device 150 during a clear operation. That is, the set abort information ABIF may be included in the transaction information TRINFO corresponding to the first write data TRAN _ WDATA "0, 1,2, and 3". Accordingly, the transaction manager 1300 may perform operation 1311.

Specifically, fig. 6C shows that each write data WDATA stored in the write buffer 1442 is set to a size corresponding to one or more "sectors", similarly to fig. 6A. That is, each write data WDATA stored in the write buffer 1442 may be set to a size corresponding to one or more sectors smaller than a unit page.

Accordingly, in operation 1311 of fig. 5, the controller 130 may set one or more "specific memory blocks" among the memory blocks 152, 154, and 156, which are simultaneously or sequentially accessed for one read operation, and then use the set one or more memory blocks as a space for storing the selected second write data NMAL _ WDATA.

For example, each of "0, 1,2, a, B, C, D, and 3", which are a total of eight write data WDATA stored in the write buffer 1442, has a size corresponding to one sector. Thus, the write buffer 1442 has a size corresponding to eight sections in total. In this case, since one page includes four sectors, the write buffer 1442 may have a size corresponding to a total of two pages.

Accordingly, the controller 130 may set the first memory block 152 of the memory blocks 152, 154, and 156 as a "specific memory block". In this state, the transaction manager 1300 included in the controller 130 may select the second write data NMAL _ WDATA "a, B, C, and D" that is not grouped into a transaction among the eight write data WDATA "0, 1,2, a, B, C, D, and 3" stored in the write buffer 1442, and then store the selected data in four sectors included in the first page P10 of the first storage block 152 set as the "specific storage block" through a clear operation. At this time, the first write data TRAN _ WDATA "0, 1,2, and 3" grouped as a transaction among the eight write data WDATA "0, 1,2, a, B, C, D, and 3" stored in the write buffer 1442 may not be stored in the first storage block 152 set as the "specific storage block" because the set abort information ABIF is included in the transaction information TRINFO corresponding to the first write data TRAN _ WDATA "0, 1,2, and 3".

FIG. 6D illustrates transaction manager 1300 storing write data WDATA stored in write buffer 1442 into non-volatile memory device 150 during a clear operation via operation 1312 of FIG. 5. That is, set commit information CMIF and set abort information ABIF may not be included in transaction information TRINFO corresponding to first write data TRAN _ WDATA "0, 1,2, and 3". Accordingly, the transaction manager 1300 may perform operation 1312.

Specifically, fig. 6D shows that each write data WDATA stored in the write buffer 1442 is set to a size corresponding to one or more "sectors", similarly to fig. 6A. That is, each write data WDATA stored in the write buffer 1442 may be set to a size corresponding to one or more sectors smaller than a unit page.

Thus, controller 130 may set one or more "particular memory blocks" among memory blocks 152, 154, and 156 that are accessed simultaneously or sequentially for a read operation. Then, the controller 130 may use the set one or more storage blocks as a space for storing the incompletely committed first write data TRAN _ WDATA and second write data NMAL _ WDATA selected in operation 1312.

For example, each of "0, 1,2, a, B, C, D, and 3", which are a total of eight write data WDATA stored in the write buffer 1442, has a size corresponding to one sector. Thus, the write buffer 1442 has a size corresponding to eight sections in total. In this case, since one page includes four sectors, the write buffer 1442 may have a size corresponding to a total of two pages.

Accordingly, the controller 130 may set the first memory block 152 of the memory blocks 152, 154, and 156 as a "specific memory block". In this state, the transaction manager 1300 included in the controller 130 may store eight write data WDATA "0, 1,2, a, B, C, D, and 3" stored in the write buffer 1442 into eight sectors included in the first and second pages P10 and P11 of the first storage block 152 set as the "specific storage block". At this time, only the first write data TRAN _ WDATA "0, 1,2, and 3" grouped as a transaction among the eight write data WDATA "0, 1,2, a, B, C, D, and 3" stored in the write buffer 1442 may not be selected and stored in a separate storage space because the set commit information CMIF and the set abort information ABIF are not included in the transaction information TRINFO corresponding to the first write data TRAN _ WDATA "0, 1,2, and 3".

Fig. 7 is a diagram illustrating a method of performing a merge operation after a plurality of write data grouped into transactions are stored in a nonvolatile memory device by the operations described with reference to fig. 5 and 6A to 6D.

Fig. 7 illustrates that the controller 130 of fig. 5 checks whether each first write data TRAN _ WDATA stored in the "first storage region" is valid, and changes a method for performing a merge operation according to the check result. By the operations described with reference to fig. 5 and 6A to 6D, the operations of fig. 7 may be performed when a merge operation for moving valid first write data TRAN _ WDTA and valid second write data NMAL _ WDATA in "first and second storage areas" to another storage area of the nonvolatile memory device 150 is performed after storing write data TRAN _ WDATA grouped into transactions in the "first storage area" and storing second write data NMAL _ WDATA not grouped into transactions in the "second storage area".

Specifically, as shown in fig. 7, a first memory block 152 of memory blocks 152, 154, and 156 of non-volatile memory device 150 may be selected as a "particular memory block". Each of the first page P10 and the fourth page P13 of the first memory block 152 may be set as a "first memory region", and each of the second, third, fifth, and sixth pages P11, P12, P14, and P15 may be set as a "second memory region".

At this time, the first write data TRAN _ WDATA "0, 1,2, and 3" grouped as the first transaction is stored in the first page P10 of the first storage block 152 set as the "first storage area". Further, the first write data TRAN _ WDATA "4, 5,6, and 7" grouped into the second transaction are stored in the fourth page P13 of the first storage block 152 set as the "first storage area". Similarly, the second write data NMAL _ WDATA "a, B, C, D, E, F, G, H, I, J, K, L, M, N, O, and P" are stored in the second, third, fifth, and sixth pages P11, P12, P14, and P15 of the first storage block 152 set as the "second storage area".

Then, the state of some of the data stored in the first memory block 152 may transition to the INVALID state INVALID when the memory system 110 is operating.

For example, as shown in fig. 7, the state of the data "D" stored in the fourth section N4 of the second page P11 of the first memory block 152, the data "F, G and H" stored in the second to fourth sections N2 to N4 of the third page P12, the data "5 and 6" stored in the second and third sections N2 and N3 of the fourth page P13, the data "J and L" stored in the second and fourth sections N2 and N4 of the fifth page P14, and the data "N and O" stored in the second and third sections N2 and N3 of the sixth page P15 may be transited to the INVALID state INVALID.

In this state, controller 130 may select first memory BLOCK 152 as the VICTIM BLOCK VICTIM BLOCK for the merge operation. Accordingly, the controller 130 may check whether each of the first write data TRAN _ WDATA grouped into transactions and stored in the first storage block 152 is valid, and then change a method for performing the merge operation according to the check result.

Accordingly, the controller 130 may check whether all of the first write data TRAN _ WDTA "0, 1,2, and 3" grouped as the first transaction and stored in the first storage block 152 are valid before performing the merge operation. Then, the controller 130 may check whether all of the first write data TRAN _ WDATA "4, 5,6, and 7" grouped as the second transaction are valid.

By checking the result, the controller 130 may recognize that all of the first write data TRAN _ WDATA "0, 1,2, and 3" grouped as the first transaction remain in the valid state. Further, among the first write data TRAN _ WDATA "4, 5,6, and 7" grouped as the second transaction, the controller 130 may recognize that "5 and 6" are transitioned to the INVALID state INVALID and only "4 and 7" remain the valid state. That is, controller 130 may recognize that all of first write data TRAN _ WDATA "0, 1,2, and 3" grouped as the first transaction are valid, and that only a part of first write data TRAN _ WDATA "4, 5,6, and 7" grouped as the second transaction is valid.

Accordingly, in performing the merge operation, the controller 130 may move the first write data TRAN _ WDATA "0, 1,2, and 3" grouped into the first transaction and determined to be valid to a "third storage region" of the nonvolatile memory device 150, for example, the first page P10 of the second storage block 154 among the storage blocks 152, 154, and 156 included in the nonvolatile memory device 150. Then, the controller 130 may move the valid data "4 and 7" among the first write data TRAN _ WDATA "4, 5,6 and 7" grouped as the second transaction and the valid data "a, B, C, E, I, K, M and P" among the second write data NMAL _ WDATA not grouped as the transaction to a "fourth storage area" of the nonvolatile memory device 150, for example, the second, third and fourth pages P21, P22 and P23 of the second storage block 154 included among the storage blocks 152, 154 and 156 in the nonvolatile memory device 150.

In short, first write data TRAN _ WDATA grouped into transactions and all held in a valid state and first write data TRAN _ WDATA grouped into transactions and partially held in a valid state may be mixed and stored in "first storage region" of nonvolatile memory device 150. Further, the second write data NMAL _ WDATA that is not grouped into transactions and remains in a valid or invalid state may be mixed and stored in the "second storage area" of the nonvolatile memory device 150.

In this state, when the "first storage region" and the "second storage region" of the nonvolatile memory device 150 need to be selected as the victim region to perform the merge operation, the controller 130 may first select the first write data TRAN _ WDATA grouped into transactions and all remaining in the valid state, and then move the selected data to the "third storage region" set as the separate storage space. Then, controller 130 may mix valid data of first write data TRAN _ WDATA grouped into a transaction and partially maintaining a valid state and valid data of second write data NMAL _ WDATA not grouped into a transaction, and then move the mixed data to "fourth storage area". Therefore, even after the merge operation is performed, the first write data TRAN _ WDATA grouped into transactions and all held in the valid state can be collected and stored in a storage space physically separated from other data.

For reference, first write data TRAN _ WDATA grouped as a transaction but not completely committed and second write data NMAL _ WDATA not grouped as a transaction and remaining in a valid or invalid state may be further stored in a "second storage area" of the nonvolatile memory device 150 while remaining in a valid or invalid state. However, first write data TRAN _ WDATA grouped as a transaction but not completely committed may not be distinguishable from second write data NMAL _ WDATA not grouped as a transaction, but has been mixed with second write data NMAL _ WDATA at the point in time when first write data TRAN _ WDATA is stored in the "second storage area" as in operation 1312. That is, from the point in time when first write data TRAN _ WDATA grouped as a transaction but not completely committed is stored in the "second storage area" of nonvolatile memory device 150, this first write data TRAN _ WDATA may be managed in the same manner as second write data NMAL _ WDATA not grouped as a transaction.

In the above embodiments, the "merge operation" may indicate a garbage collection operation. However, the "merge operation" is not limited to only the garbage collection operation, but an operation for merging two or more blocks, for example, a read reclamation operation or a wear leveling operation may also be included in the "merge operation".

Fig. 8 is a flowchart showing an operation of storing a plurality of write data grouped into transactions in a nonvolatile memory device in a memory system according to the present embodiment.

Fig. 8 illustrates a sequence of operations of storing a plurality of write data grouped into transactions in a nonvolatile memory device in a memory system, which have been described with reference to fig. 5 and 6A to 6D, according to an embodiment.

At step S10, write data WDATA may be received from host 102 and stored in write buffer 1442.

In step S20, the controller 130 may check whether the predetermined storage space of the write buffer 1442 is full. At this time, an example of step S20 may include checking whether the storage space allocated to write buffer 1442 in volatile memory device 144 is full.

When it is checked that the predetermined storage space of the write buffer 1442 is not full (S20, no), step S10 may be performed again.

When the check result of step S20 indicates that the predetermined storage space of the write buffer 1442 is full (S20, yes), the controller 130 needs to perform a clear operation on the write buffer 1442. At this time, before performing the purge operation on the write buffer 1442, the controller 130 may check whether the first write data TRAN _ WDATA grouped into a transaction exists among the write data WDATA stored in the write buffer 1442 at step S30.

When the check result of step S30 indicates that the first write data TRAN _ WDATA grouped as a transaction is not present in the write buffer 1442 (S30, no), the controller 130 may perform a clear operation on the write buffer 1442 at step S40. That is, all write data WDATA stored in the write buffer 1442 may be stored in the nonvolatile memory device 150.

When the result of step S30 indicates that the first write data TRAN _ WDATA packetized as a transaction exists in the write buffer 1442 (S30, yes), the controller 130 may check the state of the first write data TRAN _ WDATA packetized as a transaction and stored in the write buffer 1442 at step S50. Through step S50, the controller 130 may check whether the first write data TRAN _ WDATA grouped into a transaction and stored in the write buffer 1442 has been completely committed (Commit) or aborted (Abort) or incompletely committed (Continues).

When the result of step S50 indicates that committed first write data TRAN _ WDATA is included in first write data TRAN _ WDATA grouped as a transaction and stored in the write buffer 1442 (S50, Commit), the controller 130 may select only the committed first write data TRAN _ WDATA grouped as a transaction (i.e., committed data) and store the selected data in the "first storage area" of the nonvolatile memory device 150 through the first clear operation FLUSH1 at step S70. When performing the operation of step S70, at step S60 following step S70, the controller 130 may select other data stored in the write buffer 1442, i.e., the second write data NMAL _ WDATA (i.e., normal data) that is not grouped into a transaction and the first write data TRAN _ WDATA (i.e., resume data) that is grouped into a transaction but is not completely committed, and then store the selected data in the "second storage area" of the nonvolatile memory device 150.

When the result of step S50 indicates that the aborted first write data TRAN _ WDATA is included in the first write data TRAN _ WDATA grouped as a transaction and stored in the write buffer 1442 (S50, Abort), the controller 130 may select other data than the first write data TRAN _ WDATA grouped as a transaction but aborted among the write data WDATA stored in the write buffer 1442 at step S60. That is, the controller 130 may select the second write data NMAL _ WDATA (normal data) that is not grouped into a transaction and the first write data TRAN _ WDATA (continuation data) that is grouped into a transaction but is not completely committed. The controller 130 may then store the selected data in the non-volatile memory device 150 through a clear operation.

When the result of step S50 indicates that the committed first write data TRAN _ WDATA and the aborted first write data TRAN _ WDATA are not included in the first write data TRAN _ WDATA grouped as a transaction and stored in the write buffer 1442, but include only the incompletely committed first write data TRAN _ WDATA (S50, Continues), the controller 130 may perform a clear operation on the write buffer 1442 at step S40. That is, all write data WDATA stored in the write buffer 1442 may be stored in the nonvolatile memory device 150.

Hereinafter, with reference to fig. 9 to 17, a data processing system and an electronic device to which the memory system 110 according to the present embodiment is applied will be described in more detail, wherein the memory system 110 includes the memory device 150 and the controller 130 described with reference to fig. 1 to 8.

Fig. 9 to 17 are diagrams showing application examples of the data processing system of fig. 1.

Fig. 9 is a diagram showing another example of a data processing system including a memory system according to the present embodiment. For example, fig. 9 shows a memory card system 6100 to which the memory system according to the present embodiment is applied.

Referring to fig. 9, a memory card system 6100 may include a memory controller 6120, a memory device 6130, and a connector 6110.

More specifically, the memory controller 6120 may be connected to a memory device 6130 implemented by a non-volatile memory (NVM) and may be configured to access the memory device 6130. For example, the memory controller 6120 may be configured to control read operations, write operations, erase operations, and background operations of the memory device 6130. The memory controller 6120 may be configured to provide an interface between the memory device 6130 and a host and drive firmware to control the memory device 6130. That is, the memory controller 6120 may correspond to the controller 130 of the memory system 110 described with reference to fig. 1 and 5, and the memory device 6130 may correspond to the memory device 150 of the memory system 110 described with reference to fig. 1 and 5.

Thus, the memory controller 6120 may include a Random Access Memory (RAM), a processing unit, a host interface, a memory interface, and an error correction unit. The memory controller 6120 may further include the elements shown in FIG. 5.

The memory controller 6120 may communicate with an external device, such as the host 102 of FIG. 1, through the connector 6110. For example, as described with reference to fig. 1, the memory controller 6120 may be configured to communicate with external devices through one or more of a variety of communication protocols, such as: universal Serial Bus (USB), multimedia card (MMC), embedded MMC (emmc), Peripheral Component Interconnect (PCI), PCI express (pcie), Advanced Technology Attachment (ATA), serial ATA, parallel ATA, Small Computer System Interface (SCSI), enhanced compact disc interface (EDSI), Integrated Drive Electronics (IDE), firewire, Universal Flash (UFS), wireless fidelity (Wi-Fi or WiFi), and bluetooth. Therefore, the memory system and the data processing system according to the present embodiment can be applied to wired/wireless electronic devices, or particularly mobile electronic devices.

The memory device 6130 can be implemented with non-volatile memory. For example, the memory device 6130 may be implemented with various non-volatile memory devices such as: erasable Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), Ferroelectric RAM (FRAM), and spin transfer Torque magnetic RAM (STT-MRAM). Memory device 6130 may include multiple dies as in memory device 150 of fig. 5.

The memory controller 6120 and the memory device 6130 may be integrated into a single semiconductor device. For example, the memory controller 6120 and the memory device 6130 may constitute a Solid State Drive (SSD) by being integrated into a single semiconductor device. Also, the memory controller 6120 and the memory device 6130 may constitute a memory card such as a PC card (personal computer memory card international association (PCMCIA)), a Compact Flash (CF) card, a smart media card (e.g., SM and SMC), a memory stick, a multimedia card (e.g., MMC, RS-MMC, micro MMC, and eMMC), a Secure Digital (SD) card (e.g., SD, mini SD, micro SD, and SDHC), and a Universal Flash (UFS).

Fig. 10 is a diagram showing another example of a data processing system 6200 including the memory system according to the present embodiment.

Referring to fig. 10, data processing system 6200 may include a memory device 6230 having one or more non-volatile memories (NVMs) and a memory controller 6220 for controlling memory device 6230. The data processing system 6200 shown in fig. 10 may serve as a storage medium such as a memory card (e.g., CF, SD, micro SD, or the like) or a USB device as shown with reference to fig. 1. The memory device 6230 may correspond to the memory device 150 in the memory system 110 shown in fig. 1 to 5, and the memory controller 6220 may correspond to the controller 130 in the memory system 110 shown in fig. 1 to 5.

The memory controller 6220 may control read, write, or erase operations to the memory device 6230 in response to requests by the host 6210, and the memory controller 6220 may include one or more Central Processing Units (CPUs) 6221, a buffer memory such as a Random Access Memory (RAM)6222, an Error Correction Code (ECC) circuit 6223, a host interface 6224, and a memory interface such as a non-volatile memory device (NVM) interface 6225.

The CPU 6221 may control all operations on the memory device 6230, such as read operations, write operations, file system management operations, and bad page management operations. The RAM 6222 is operable according to control of the CPU 6221, and functions as a work memory, a buffer memory, or a cache memory. When the RAM 6222 is used as a working memory, data processed by the CPU 6221 can be temporarily stored in the RAM 6222. When RAM 6222 is used as a buffer memory, RAM 6222 can be used to buffer data transferred from the host 6210 to the memory device 6230 or data transferred from the memory device 6230 to the host 6210. When RAM 6222 is used as cache memory, the RAM 6222 may assist the low-speed memory device 6230 in operating at high speed.

The ECC circuit 6223 may correspond to the ECC unit 138 of the controller 130 shown in fig. 1. As described with reference to fig. 1, the ECC circuit 6223 may generate an Error Correction Code (ECC) for correcting a failed bit or an error bit of data provided from the memory device 6230. ECC circuitry 6223 may perform error correction coding on data provided to memory device 6230, forming data with parity bits. The parity bits may be stored in the memory device 6230. The ECC circuit 6223 may perform error correction decoding on data output from the memory device 6230. At this time, the ECC circuit 6223 may correct the error using the parity bit. For example, as described with reference to fig. 1, the ECC circuit 6223 may correct errors using a Low Density Parity Check (LDPC) code, a Bose-Chaudhri-Hocquenghem (BCH) code, a turbo code, a Reed-Solomon (Reed-Solomon) code, a convolutional code, a Recursive Systematic Code (RSC), or a coded modulation such as Trellis Coded Modulation (TCM) or Block Coded Modulation (BCM).

The memory controller 6220 may transmit data or signals to and/or receive data or signals from the host 6210 through the host interface 6224 and transmit data or signals to and/or receive data or signals from the memory device 6230 through the NVM interface 6225. The host interface 6224 may be connected to the host 6210 by a Parallel Advanced Technology Attachment (PATA) bus, a Serial Advanced Technology Attachment (SATA) bus, a Small Computer System Interface (SCSI), a Universal Serial Bus (USB), a peripheral component interconnect express (PCIe), or a NAND interface. The memory controller 6220 may have a wireless communication function having a mobile communication protocol such as wireless fidelity (WiFi) or Long Term Evolution (LTE). The memory controller 6220 may connect to an external device, such as the host 6210 or another external device, and then transmit and/or receive data to/from the external device. In particular, since the memory controller 6220 is configured to communicate with an external device through one or more of various communication protocols, the memory system and the data processing system according to the present embodiment may be applied to wired/wireless electronic devices or particularly mobile electronic devices.

Fig. 11 is a diagram showing another example of a data processing system including the memory system according to the present embodiment. Fig. 11 shows a Solid State Drive (SSD) to which the memory system according to the present embodiment is applied.

Referring to fig. 11, the SSD 6300 may include a controller 6320 and a memory device 6340 including a plurality of nonvolatile memories (NVMs). The controller 6320 may correspond to the controller 130 in the memory system 110 of fig. 1 and 5, and the memory device 6340 may correspond to the memory device 150 in the memory system of fig. 1 and 5.

More specifically, the controller 6320 may be connected to the memory device 6340 through a plurality of channels CH1 through CHi. The controller 6320 may include one or more processors 6321, Error Correction Code (ECC) circuitry 6322, a host interface 6324, a buffer memory 6325, and a memory interface such as a non-volatile memory interface 6326.

The buffer memory 6325 may temporarily store data supplied from the host 6310 or data supplied from the plurality of flash memories NVM included in the memory device 6340, or temporarily store metadata of the plurality of flash memories NVM, for example, mapping data including a mapping table. The buffer memory 6325 may be implemented by volatile memory such as Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate (DDR) SDRAM, low power DDR (lpddr) SDRAM, and graphics RAM (gram), or non-volatile memory such as ferroelectric RAM (fram), resistive RAM (RRAM or ReRAM), spin transfer torque magnetic RAM (STT-MRAM), and phase change RAM (pram). For convenience, fig. 11 shows that the buffer memory 6325 exists in the controller 6320. However, the buffer memory 6325 may exist outside the controller 6320.

The ECC circuit 6322 may calculate an Error Correction Code (ECC) value of data to be programmed to the memory device 6340 during a program operation, perform an error correction operation on data read from the memory device 6340 based on the ECC value during a read operation, and perform an error correction operation on data recovered from the memory device 6340 during a failed data recovery operation.

The host interface 6324 may provide an interface function with an external device such as the host 6310, and the nonvolatile memory interface 6326 may provide an interface function with the memory device 6340 connected through a plurality of channels.

Further, a plurality of SSDs 6300 to which the memory system 110 of fig. 1 and 5 is applied may be provided to implement a data processing system, for example, a Redundant Array of Independent Disks (RAID) system. At this time, the RAID system may include a plurality of SSDs 6300 and a RAID controller for controlling the plurality of SSDs 6300. When the RAID controller performs a program operation in response to a write command provided from the host 6310, the RAID controller may select one or more memory systems or SSDs 6300 in the SSD 6300 according to a plurality of RAID levels, i.e., RAID level information of the write command provided from the host 6310, and output data corresponding to the write command to the selected SSD 6300. Further, when the RAID controller performs a read operation in response to a read command provided from the host 6310, the RAID controller may select one or more memory systems or SSDs 6300 in the SSD 6300 according to a plurality of RAID levels, that is, RAID level information of the read command provided from the host 6310, and provide data read from the selected SSDs 6300 to the host 6310.

Fig. 12 is a diagram showing another example of a data processing system including the memory system according to the present embodiment. For example, fig. 12 shows an embedded multimedia card (eMMC)6400 to which the memory system according to the present embodiment is applied.

Referring to fig. 12, the eMMC 6400 may include a controller 6430 and a memory device 6440 implemented by one or more NAND flash memories. The controller 6430 may correspond to the controller 130 in the memory system 110 of fig. 1 and 5, and the memory device 6440 may correspond to the memory device 150 in the memory system 110 of fig. 1 and 5.

More specifically, the controller 6430 may be connected to the memory device 6440 through a plurality of channels. The controller 6430 may include one or more cores 6432, a host interface 6431, and a memory interface such as a NAND interface 6433.

The kernel 6432 may control the overall operation of the eMMC 6400, the host interface 6431 may provide an interface function between the controller 6430 and the host 6410, and the NAND interface 6433 may provide an interface function between the memory device 6440 and the controller 6430. For example, the host interface 6431 may be used as a parallel interface, such as the MMC interface described with reference to fig. 1. In addition, the host interface 6431 may be used as a serial interface, such as a Ultra High Speed (UHS) -I/UHS-II interface.

Fig. 13 to 16 are diagrams showing other examples of a data processing system including the memory system according to the present embodiment. For example, fig. 13 to 16 show a Universal Flash Storage (UFS) system to which the memory system according to the present embodiment is applied.

Referring to fig. 13 through 16, UFS systems 6500, 6600, 6700, and 6800 may include hosts 6510, 6610, 6710, and 6810, UFS devices 6520, 6620, 6720, and 6820, and UFS cards 6530, 6630, 6730, and 6830, respectively. Hosts 6510, 6610, 6710, and 6810 may function as application processors for wired/wireless electronic devices or, in particular, mobile electronic devices, UFS devices 6520, 6620, 6720, and 6820 may function as embedded UFS devices, and UFS cards 6530, 6630, 6730, and 6830 may function as external embedded UFS devices or removable UFS cards.

Hosts 6510, 6610, 6710, and 6810 in respective UFS systems 6500, 6600, 6700, and 6800, UFS devices 6520, 6620, 6720, and 6820, and UFS cards 6530, 6630, 6730, and 6830 may communicate with external devices such as wired/wireless electronic devices or, in particular, mobile electronic devices through the UFS protocol, and UFS devices 6520, 6620, 6720, and 6820, and UFS cards 6530, 6630, 6730, and 6830 may be implemented by memory system 110 shown in fig. 1 and 5. For example, in UFS systems 6500, 6600, 6700, and 6800, UFS devices 6520, 6620, 6720, and 6820 may be implemented in the form of a data processing system 6200, SSD 6300, or eMMC 6400 described with reference to fig. 10 to 12, and UFS cards 6530, 6630, 6730, and 6830 may be implemented in the form of a memory card system 6100 described with reference to fig. 9.

Furthermore, in UFS systems 6500, 6600, 6700, and 6800, hosts 6510, 6610, 6710, and 6810, UFS devices 6520, 6620, 6720, and 6820, and UFS cards 6530, 6630, 6730, and 6830 may communicate with each other through UFS interfaces, e.g., MIPI M-PHY and MIPI unified protocol (UniPro) in Mobile Industry Processor Interface (MIPI). In addition, UFS devices 6520, 6620, 6720, and 6820 and UFS cards 6530, 6630, 6730, and 6830 may communicate with each other through various protocols other than the UFS protocol, for example, universal memory bus (USB) flash drive (UFD), multimedia card (MMC), Secure Digital (SD), mini SD, and micro SD.

In UFS system 6500 shown in fig. 13, each of host 6510, UFS device 6520, and UFS card 6530 may include UniPro. Host 6510 may perform interworking operations to communicate with UFS device 6520 and UFS card 6530. In particular, host 6510 may communicate with UFS device 6520 or UFS card 6530 via link layer exchanges, such as the L3 exchange at UniPro. At this time, the UFS device 6520 and the UFS card 6530 may communicate with each other through link layer exchange at UniPro of the host 6510. In the present embodiment, for convenience of description, a configuration in which one UFS device 6520 and one UFS card 6530 are connected to a host 6510 has been illustrated. However, multiple UFS devices and UFS cards may be connected to host 6410 in parallel or in a star, and multiple UFS cards may be connected to UFS device 6520 in parallel or in a star, or connected to UFS device 6520 in series or in a chain.

In UFS system 6600 shown in fig. 14, each of host 6610, UFS device 6620, and UFS card 6630 may include UniPro, and host 6610 may communicate with UFS device 6620 or UFS card 6630 through a switching module 6640 that performs switching operations, e.g., switching module 6640 that performs link-layer switching, e.g., L3 switching, at UniPro. UFS device 6620 and UFS card 6630 may communicate with each other through a link layer exchange of exchange module 6640 at UniPro. In the present embodiment, for convenience of description, a configuration has been illustrated in which one UFS device 6620 and one UFS card 6630 are connected to a switching module 6640. However, multiple UFS devices and UFS cards may be connected to switching module 6640 in parallel or in a star format, and multiple UFS cards may be connected to UFS device 6620 in series or in a chain format.

In UFS system 6700 shown in fig. 15, each of host 6710, UFS device 6720, and UFS card 6730 may include UniPro, and host 6710 may communicate with UFS device 6720 or UFS card 6730 through switching module 6740 that performs switching operations, e.g., through switching module 6740 that performs link-layer switching at UniPro, e.g., L3 switching. At this time, UFS device 6720 and UFS card 6730 may communicate with each other through link layer switching of switching module 6740 at UniPro, and switching module 6740 may be integrated with UFS device 6720 into one module inside or outside UFS device 6720. In the present embodiment, a configuration in which one UFS device 6720 and one UFS card 6730 are connected to a switching module 6740 has been illustrated for convenience of description. However, a plurality of modules each including the switching module 6740 and the UFS device 6720 may be connected to the main machine 6710 in parallel or in a star form, or connected to each other in series or in a chain form. Further, multiple UFS cards may be connected to UFS device 6720 in parallel or in a star formation.

In UFS system 6800 shown in fig. 16, each of host 6810, UFS device 6820, and UFS card 6830 may include a M-PHY and UniPro. UFS device 6820 may perform a swap operation to communicate with host 6810 and UFS card 6830. In particular, UFS device 6820 may communicate with host 6810 or UFS card 6830 through a swap operation between the M-PHY and UniPro modules used to communicate with host 6810 and the M-PHY and UniPro modules used to communicate with UFS card 6830, e.g., through a target Identifier (ID) swap operation. At this time, the host 6810 and the UFS card 6830 can communicate with each other through target ID exchange between the M-PHY of the UFS device 6820 and the UniPro module. In the present embodiment, for convenience of description, a configuration in which one UFS device 6820 is connected to the host 6810 and one UFS card 6830 is connected to the UFS device 6820 has been exemplified. However, a plurality of UFS devices may be connected to the host 6810 in parallel or in a star form, or connected to the host 6810 in series or in a chain, and a plurality of UFS cards may be connected to the UFS device 6820 in parallel or in a star form, or connected to the UFS device 6820 in series or in a chain form.

Fig. 17 is a diagram showing another example of a data processing system including a memory system according to the embodiment. For example, fig. 17 is a diagram showing a user system 6900 to which the memory system according to the present embodiment is applied.

Referring to fig. 17, the user system 6900 may include a user interface 6910, a memory module 6920, an application processor 6930, a network module 6940, and a storage module 6950.

More specifically, the application processor 6930 may drive components included in a user system 6900, such as an Operating System (OS), and include controllers, interfaces, and a graphics engine that control the components included in the user system 6900. The application processor 6930 may be provided as a system on chip (SoC).

The memory module 6920 may serve as a main memory, working memory, buffer memory, or cache memory for the user system 6900. Memory module 6920 may include volatile Random Access Memory (RAM) such as Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate (DDR) SDRAM, DDR2 SDRAM, DDR3SDRAM, low power DDR (LPDDR) SDARM, LPDDR2 SDRAM, or LPDDR3SDRAM, or non-volatile RAM such as phase change RAM (PRAM), resistive RAM (ReRAM), Magnetoresistive RAM (MRAM), or Ferroelectric RAM (FRAM). For example, the application processor 6930 and memory module 6920 may be packaged and installed based on a Package On Package (POP).

The network module 6940 may communicate with external devices. For example, the network module 6940 can support not only wired communication, but also various wireless communication protocols, such as Code Division Multiple Access (CDMA), global system for mobile communications (GSM), wideband CDMA (wcdma), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), Worldwide Interoperability for Microwave Access (WIMAX), Wireless Local Area Network (WLAN), Ultra Wideband (UWB), bluetooth, wireless display (WI-DI), to communicate with wired/wireless electronic devices, or in particular mobile electronic devices. Accordingly, the memory system and the data processing system according to the embodiment of the present invention may be applied to wired/wireless electronic devices. The network module 6940 can be included in the application processor 6930.

The memory module 6950 can store data, such as data received from the application processor 6930, and can transmit the stored data to the application processor 6930. The memory module 6950 may be implemented by a nonvolatile semiconductor memory device such as a phase change ram (pram), a magnetic ram (mram), a resistive ram (reram), a NAND flash memory, a NOR flash memory, and a 3D NAND flash memory, and may be provided as a removable storage medium such as a memory card or an external drive of the user system 6900. The memory module 6950 may correspond to the memory system 110 described with reference to fig. 1 and 5. Further, the memory module 6950 may be implemented as an SSD, eMMC, and UFS as described above with reference to fig. 11-16.

The user interface 6910 may include an interface for inputting data or commands to the application processor 6930 or for outputting data to external devices. For example, the user interface 6910 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touch screen, touch pad, touch ball, camera, microphone, gyro sensor, vibration sensor, and piezoelectric element, and user output interfaces such as a Liquid Crystal Display (LCD), Organic Light Emitting Diode (OLED) display device, active matrix OLED (amoled) display device, LED, speaker, and monitor.

In addition, when the memory system 110 of fig. 1 and 5 is applied to a mobile electronic device of the user system 6900, the application processor 6930 may control the overall operation of the mobile electronic device, and the network module 6940 may be used as a communication module for controlling wired/wireless communication with an external device. The user interface 6910 may display data processed by the processor 6930 on a display/touch module of the mobile electronic device or support a function of receiving data from a touch panel.

According to the present embodiment, when temporarily storing a plurality of write data grouped into transactions into a write buffer within the memory system and then storing the write data in a memory block through a clear operation on the write buffer, the memory system may adjust a method of storing the plurality of write data grouped into transactions in the memory block according to whether the transactions have committed.

Therefore, the memory system can efficiently read a plurality of write data grouped into transactions and stored in the memory block.

Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.