阅读说明：本技术 一种基于并行循环压缩的余数运算电路及方法 (Remainder operation circuit and method based on parallel cyclic compression ) 是由 刘骁 赵冠一 张昆 唐勇 谢军 朱巍 王之辰 于 2019-09-12 设计创作，主要内容包括：本发明属于计算机整数乘法校验设计技术领域,特别涉及一种基于并行压缩循环的余数运算电路及方法。包括多个输入端,分别用于输入多个同位宽的二进制数；模加法器,用于输出求余结果；一层或多层进位保留加法器组件,设置在多个输入端和模加法器之间；每一层进位保留加法器组件包括一个或者多个进位保留加法器；最上层的进位保留加法器的两个输出连接至模加法器的输入,其余每层进位保留加法器的和输出作为下层进位保留加法器的输入,其余每层进位保留加法器的进位输出向最左移动1位以后作为下层进位保留加法器的输入；同位宽的二进制数由整数拆分而成。仅在最后输出一级采用了模加法器,而中间级均采用进位保留加法器提高了电路的时序性能。(The invention belongs to the technical field of computer integer multiplication check design, and particularly relates to a remainder operation circuit and method based on parallel compression cycle. The input end is used for inputting a plurality of binary numbers with the same bit width; the modulus adder is used for outputting a remainder result; one or more layers of carry-save adder components disposed between the plurality of inputs and the modulo adder; each layer of carry-save adder components comprises one or more carry-save adders; the two outputs of the carry-save adder at the uppermost layer are connected to the inputs of the modulo adders, the sum output of the carry-save adders at each other layer is used as the input of the carry-save adder at the lower layer, and the carry output of the carry-save adders at each other layer is used as the input of the carry-save adder at the lower layer after moving 1 bit to the leftmost; binary numbers with the same bit width are formed by integer splitting. The modulo adder is adopted only in the last output stage, and the carry-retaining adders are adopted in the middle stages, so that the time sequence performance of the circuit is improved.)

1. A residue operation circuit based on parallel cyclic compression, comprising:

the input ends are respectively used for inputting a plurality of binary numbers with the same bit width;

the modulus adder is used for outputting a remainder result;

one or more layers of carry-save adder components disposed between the plurality of inputs and the modulo adder;

each layer of the carry-save adder components comprises one or more carry-save adders;

the two outputs of the carry-save adder at the uppermost layer are connected to the inputs of the modulo adders, the sum output of each of the rest layers of the carry-save adders is used as the input of the carry-save adder at the lower layer, and the carry output of each of the rest layers of the carry-save adders moves 1 bit to the leftmost circle and is used as the input of the carry-save adder at the lower layer;

the binary number with the same bit width is formed by integer splitting.

2. The parallel cycle compression-based remainder operation circuit of claim 1, wherein:

the input ends are respectively connected with the input of the carry-save adder at the bottommost layer.

3. The parallel cyclic compression-based remainder operation circuit of claim 1, wherein:

the input ends are respectively connected with the input of the carry-save adder at the bottommost layer and the input of the carry-save adder at the second last layer.

4. The integer multiply remainder circuit based on parallel loop compression of claim 1, wherein:

the carry-save adder is 3: a carry-2 save adder.

5. The parallel cyclic compression-based remainder operation circuit of claim 1, wherein:

the carry-save adder is a 4:2 carry-save adder.

6. The parallel cyclic compression-based remainder operation circuit of claim 1, wherein:

the digit of the binary number with the same bit width is k;

the modulo adder is 2^k-a modulo 1 adder.

7. A remainder operation method based on parallel cyclic compression is characterized by comprising the following steps:

step S1, dividing the integer into a plurality of binary numbers with equal bit width and carrying out carry reservation operation in parallel;

step S2, circularly shifting the carry output of one or more carry-save operations performed in parallel to the highest bit by 1 bit, and performing carry-save operations on the sum output of one or more carry-save operations;

step S3, repeating step S2 until only one carry output and one sum output remain;

a step S4 of cyclically shifting the carry output obtained in the step S3 to the highest bit by 1 bit and performing modulo addition on the sum output obtained in the step S3;

in step S5, the result of the modulo addition operation of step S4 is output as a remainder result.

8. The method of claim 7, wherein the method comprises:

in step S2, carry-save operation is performed by combining three binary arrays.

9. The method of claim 8, wherein the method comprises:

in step S2, carry-save operation is performed by combining every four binary arrays.

10. The integer multiplication remainder operation method based on parallel loop compression as claimed in claim 7, wherein:

in step S1, the integer is split into a plurality of k-bit binary numbers and carry-save operation is performed in parallel;

in the step S3, the carry output obtained in the step S3 is cyclically shifted to the highest bit by 1 bit, and the sum output obtained in the step S3 is modulo-2^k-1 addition operation.

Technical Field

The invention belongs to the technical field of computer integer multiplication check design, and particularly relates to a remainder operation circuit and a remainder operation method based on parallel cyclic compression.

Background

The integer multiplication unit is time-series tight and its reliable operation capability has a great impact on the whole chip. Further fault-tolerant operation can be achieved by performing real-time error detection on the integer multiplication component. The remainder code check is a commonly used error detection technology in an integer arithmetic part, and the purpose of error detection in the arithmetic process can be achieved by coding and checking input data and an arithmetic result. However, in the checking process, real-time remainder coding and comparison are required to be performed on the operation result, and a higher requirement is provided for the time sequence of the integral multiplication checking component.

Disclosure of Invention

In order to solve the technical problems, the invention provides a remainder operation circuit and a method based on parallel cyclic compression, wherein the remainder operation circuit is organized and optimized.

A residue operation circuit based on parallel cyclic compression, comprising:

the input ends are respectively used for inputting a plurality of binary numbers with the same bit width;

the modulus adder is used for outputting a remainder result;

one or more layers of carry-save adder components disposed between the plurality of inputs and the modulo adder;

each layer of the carry-save adder components comprises one or more carry-save adders;

the two outputs of the carry-save adder at the uppermost layer are connected to the inputs of the modulo adders, the sum output of each of the rest layers of the carry-save adders is used as the input of the carry-save adder at the lower layer, and the carry output of each of the rest layers of the carry-save adders moves 1 bit to the leftmost circle and is used as the input of the carry-save adder at the lower layer;

the binary number with the same bit width is formed by integer splitting.

In the technical scheme, the modular adder is adopted only in the last output stage, and the carry-retaining adders are adopted in the intermediate stages, so that the time sequence performance of the circuit is improved.

Further, the plurality of input ends are respectively connected with the input of the carry-save adder at the bottommost layer.

Further, the input ends are respectively connected with the input of the carry-save adder at the bottommost layer and the input of the carry-save adder at the second last layer.

Preferably, the carry-save adder is 3: a carry-2 save adder.

Preferably, the carry-save adder is a 4:2 carry-save adder.

Preferably, the number of bits of the binary number with the same bit width is k; the modulo adder is 2^k-a modulo 1 adder.

The invention also provides a remainder operation method based on parallel cycle compression, which is characterized by comprising the following steps:

step S1, dividing the integer into a plurality of binary numbers with equal bit width and carrying out carry reservation operation in parallel;

step S2, circularly shifting the carry output of one or more carry-save operations performed in parallel to the highest bit by 1 bit, and performing carry-save operations on the sum output of one or more carry-save operations;

step S3, repeating step S2 until only one carry output and one sum output remain;

a step S4 of cyclically shifting the carry output obtained in the step S3 to the highest bit by 1 bit and performing modulo addition on the sum output obtained in the step S3;

in step S5, the result of the modulo addition operation of step S4 is output as a remainder result.

In the technical scheme, the modular addition operation is only carried out in the last output step, and the time sequence performance of the circuit is improved by adopting carry-retaining addition operation in the middle steps.

Preferably, in step S2, each three binary arrays are combined together to perform a carry-save operation.

Preferably, in step S2, each four binary arrays are combined together to perform a carry-save operation.

Preferably, in step S1, the integer is split into a plurality of k-bit binary numbers and carry-save operation is performed in parallel; in the step S3, the carry output obtained in the step S3 is cyclically shifted to the highest bit by 1 bit, and the sum output obtained in the step S3 is modulo-2^k-1 addition operation.

The invention has the following beneficial effects:

the residue number circuit reduces the use of the modulus adder, and can optimize the logic sequence of residue number generation under the condition that the area overhead is not increased basically.

Drawings

Fig. 1 is a schematic diagram of a residue circuit of the prior art.

Fig. 2 is a schematic diagram of a residue circuit according to an embodiment of the present application.

Detailed Description

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that the conventional terms should be interpreted as having a meaning that is consistent with their meaning in the relevant art and this disclosure. The present disclosure is to be considered as an example of the invention and is not intended to limit the invention to the particular embodiments.