阅读说明：本技术 一种台面型肖特基集电区NPN SiGe HBT器件及其制备方法 (Mesa Schottky collector region NPN SiGe HBT device and preparation method thereof ) 是由 李迈克 于 2019-11-11 设计创作，主要内容包括：本发明提供一种台面型肖特基集电区NPN SiGe HBT器件,包括N型轻掺杂单晶硅衬底,N型轻掺杂单晶硅衬底表面顺序层叠有N型重掺杂单晶硅层、金属硅化物薄层、P型重掺杂Si<Sub>1-x</Sub>Ge<Sub>x</Sub>基区层、N型掺杂单晶硅发射区帽层和N型重掺杂多晶硅发射区层,N型重掺杂多晶硅发射区层至N型掺杂单晶硅发射区帽层刻蚀形成有发射区电极接触台面和基区电极接触台面,N型重掺杂多晶硅发射区层至金属硅化物薄层刻蚀形成有集电区电极接触台面,台面结构表面覆盖有氧化层,电极窗口形成有对应金属电极,基区电极接触区域里沉积有P型重掺杂β-Si<Sub>1-y</Sub>C<Sub>y</Sub>。本发明还提供一种前述器件制备方法。本申请能提高器件截止频率和增益并减小基区渡越时间且能与常规硅基工艺相兼容。(The invention provides a mesa Schottky collector region NPN SiGe HBT device, which comprises an N-type lightly doped monocrystalline silicon substrate, wherein an N-type heavily doped monocrystalline silicon layer, a metal silicide thin layer and a P-type heavily doped Si layer are sequentially stacked on the surface of the N-type lightly doped monocrystalline silicon substrate 1‑x Ge x The emitter region electrode contact mesa and the base region electrode contact mesa are formed by etching from the N-type heavily doped polycrystalline silicon emitter region layer to the N-type doped monocrystalline silicon emitter region cap layer, the collector region electrode contact mesa is formed by etching from the N-type heavily doped polycrystalline silicon emitter region layer to the metal silicide thin layer, an oxide layer covers the surface of the mesa structure, and an electrode window is covered by an electrode windowForming corresponding metal electrode, depositing P-type heavily doped beta-Si in the contact region of the base electrode 1‑y C y . The invention also provides a preparation method of the device. The method can improve the cut-off frequency and the gain of the device, reduce the base region transit time and be compatible with the conventional silicon-based process.)

1. The mesa Schottky collector region NPN SiGe HBT device is characterized by comprising an N-type lightly doped monocrystalline silicon substrate, wherein an N-type heavily doped monocrystalline silicon layer is formed on the surface of the N-type lightly doped monocrystalline silicon substrate, and the N-type heavily doped monocrystalline silicon layer is formed on the surface of the N-type heavily doped monocrystalline silicon layerA metal silicide thin layer is formed on the surface, and P-type heavily doped Si is formed on the surface of the metal silicide thin layer_1-xGe_xBase region layer and 0.1<x<0.3, the P type heavily doped Si_1-xGe_xAn N-type doped monocrystalline silicon emitter region cap layer is formed on the surface of the base region layer, an N-type heavily doped polycrystalline silicon emitter region layer is formed on the surface of the N-type doped monocrystalline silicon emitter region cap layer, an emitter region electrode contact table top and left and right lateral side region electrode contact table tops are formed by etching the N-type heavily doped polycrystalline silicon emitter region layer to the N-type doped monocrystalline silicon emitter region cap layer, left and right lateral collector region electrode contact table tops are formed by etching the N-type heavily doped polycrystalline silicon emitter region layer to the metal silicide thin layer, an oxide layer covers the whole surface of the table top structure, corresponding electrode contact windows are formed by etching the oxide layers corresponding to the base region, the collector region and the middle emitter region, and corresponding electrode contact windows are formed by etching the oxide layer_1-xGe_xA base electrode contact area is formed by etching the base layer, a corresponding metal electrode is formed on the electrode contact window, and P-type heavily doped beta-Si is deposited in the base electrode contact area_1-yC_yAnd 0.02<y<0.05。

2. The mesa schottky collector NPN SiGe HBT device of claim 1 wherein the heavily N-doped monocrystalline silicon layer has a thickness of 200 nm.

3. The mesa-type schottky current collector NPN SiGe HBT device of claim 1 wherein the thin layer of metal silicide is a 5nm thick CoSi₂。

4. The mesa-type schottky collector NPN SiGe HBT device of claim 1 wherein the heavily P-doped Si is doped with Si_1-xGe_xThe thickness of the base region layer is 20-30 nm.

5. The mesa schottky collector NPN SiGe HBT device of claim 1 wherein the N-doped monocrystalline silicon emitter cap layer has a thickness of 10nm and the N-heavily doped polycrystalline silicon emitter layer has a thickness of 0.5 μm.

6. The mesa schottky current collector NPN SiGe HBT device of claim 1 wherein the oxide layer is 100nm thick SiO₂And oxidizing the layer.

7. A method for fabricating a mesa schottky collector NPN SiGe HBT device according to any one of claims 1-6, comprising the steps of:

s1, preparing a doping concentration of 10¹⁵cm^-3After that, a layer of doping concentration of 1 multiplied by 10 is grown on the surface of the N type lightly doped monocrystalline silicon substrate by CVD¹⁹cm^-3Cleaning and chemically-mechanically polishing the surface of the N-type heavily-doped monocrystalline silicon layer;

s2, growing a layer of metal with the thickness of 5nm on the surface of the N-type heavily-doped monocrystalline silicon layer by utilizing physical vapor deposition, and then carrying out rapid thermal annealing treatment to oxidize the metal and the monocrystalline silicon surface below to form a metal silicide thin layer as a collector region;

s3, depositing a layer of thin P-type heavily doped Si on the surface of the metal silicide thin layer by using molecular beam epitaxy technology_1-xGe_xBase region layer with Ge group x of 0.1<x<0.3, doping concentration of 1X 10¹⁹cm^-3(ii) a Then heavily doping Si in P type_1-xGe_xA cap layer of an N-type doped monocrystalline silicon emitter region is continuously grown on the surface of the base region layer, and the doping concentration is 5 multiplied by 10¹⁷cm^-3(ii) a Finally, depositing a layer of N-type heavily doped polysilicon emitter region layer with typical thickness of 0.5 μm on the surface of the cap layer of the N-type doped monocrystalline silicon emitter region, with doping concentration of 2 × 10¹⁹cm^-3；

S4, etching an emitter and a base region from the N-type heavily doped polycrystalline silicon emitter region layer to the N-type doped monocrystalline silicon emitter region cap layer according to the emitter width preset by the device, and then etching a collector region from the N-type heavily doped polycrystalline silicon emitter region layer to the metal silicide thin layer to form a mesa structure;

s5, forming an oxide layer covering the whole mesa by dry oxygen oxidation on the etched mesa structure, determining electrode contact windows of the emitter, the base and the collector, and etching off the oxide layer of the emitter region, the base region and the collector region window and the P-type heavily doped Si below the base region window_1-xGe_xBase region, then Si etched away_1-xGe_xThe doping concentration of the region is 2 multiplied by 10¹⁹cm^-3P-type heavily doped beta-Si_1-yC_yThe value of the component C y is 0.02<y<And 0.05, finally depositing metal on electrode contact windows of the emitter region, the base region and the collector region to be used as an emitter electrode, a base electrode and a collector electrode, and finishing the manufacture of the device.

8. The method for manufacturing a mesa schottky collector NPN SiGe HBT device according to claim 7, wherein in the step S1, the N-type lightly doped single crystal silicon substrate is a semi-insulating single crystal silicon substrate having a (100) crystal plane.

9. The method of manufacturing a mesa-type schottky collector NPN SiGe HBT device as claimed in claim 7, wherein in step S2, the metal grown on the surface of the heavily doped monocrystalline silicon layer is Co, and Co is oxidized with the surface of the underlying monocrystalline silicon to form CoSi₂。

10. The method for fabricating a mesa-type schottky current collector NPN SiGe HBT device according to claim 7, wherein in step S5, the oxide layer is SiO 10nm thick₂。

Technical Field

The invention relates to the technical field of semiconductors, in particular to a mesa Schottky collector region NPN SiGe HBT device and a preparation method thereof.

Background

The market at present has increasingly strong demands for high-performance devices such as high-speed devices, high-frequency devices, low-cost devices and the like. But because of the limitation of the physical properties of the Si material, the performances of high speed, high frequency and the like of the conventional Si device are difficult to improve; although III-V compound semiconductor devices (e.g., GaAs, InP, etc.) are much better than Si devices in high-speed high-frequency performance, they have disadvantages of incompatibility with Si device processes, high cost, etc. A silicon-germanium heterojunction bipolar transistor (SiGe HBT) is a silicon-based bipolar junction transistor (SiBJT) with a small amount of Ge added to the base region. The base region is made of SiGe material, so that the device performance is remarkably improved, and the SiGeHBT becomes a standard bipolar transistor in high-speed application. The key index of the ultrahigh frequency semiconductor device is cut-off frequency (fT), and SiGe HBT developed on the basis of mature silicon process utilizes the advantages of 'energy band engineering', thereby fundamentally solving the contradiction between the improvement of amplification factor and the improvement of frequency characteristic. Due to the complete compatibility with the mature silicon process and the development and maturation of the process technologies such as Molecular Beam Epitaxy (MBE) and Chemical Vapor Deposition (CVD), the SiGe HBT has its unique advantages and is widely used in high-performance microwave rf devices and circuits.

Because the mobility of electrons is obviously higher than that of holes, the current SiGe HBTs mostly adopt NPN type. However, if the collector junction of a conventional SiGe HBT is replaced by a schottky junction, the operating speed of the device can be further improved, since the schottky contact has two significant main advantages: (1) the collector resistance is 0; (2) because there is no collector junction space charge region, the collector junction transit time can be 0, as can the charge storage time, which can further increase the cutoff frequency.

The inventor of the invention researches and discovers that in order to achieve the purpose of reducing the base transition time of the NPN type SiGe HBT, the advantages of strain engineering can be combined with the conventional means of reducing the thickness of the SiGe base region. At present, "strain engineering" is mainly applied to the process of high-speed MOSFET, especially in the semiconductor process of 90 nm and below, uniaxial strain is a commonly used technical means. Therefore, if the uniaxial strain technology can be introduced into the NPN-type SiGe HBT, stress is applied to the base region of the NPN-type SiGe HBT through simple process steps, the longitudinal mobility of base region minority carriers (electrons) is reduced, the base region transit time is reduced, and the cut-off frequency of the device is improved; meanwhile, the compatibility with the conventional silicon-based CMOS process is also considered, and the method is convenient for large-scale commercial manufacturing.

Disclosure of Invention

Aiming at the technical problem of how to reduce the transition time of an NPN-type SiGe HBT base region and the longitudinal mobility of electrons, the invention provides a mesa-type Schottky collector region NPN SiGe HBT device.

In order to solve the technical problems, the invention adopts the following technical scheme:

a mesa Schottky collector region NPN SiGe HBT device comprises an N-type lightly doped monocrystalline silicon substrate, wherein an N-type heavily doped monocrystalline silicon layer is formed on the surface of the N-type lightly doped monocrystalline silicon substrate, a metal silicide thin layer is formed on the surface of the N-type heavily doped monocrystalline silicon layer, and a P-type heavily doped Si layer is formed on the surface of the metal silicide thin layer_1-xGe_xBase region layer and 0.1<x<0.3, the P type heavily doped Si_1-xGe_xAn N-type doped monocrystalline silicon emitter region cap layer is formed on the surface of the base region layer, an N-type heavily doped polycrystalline silicon emitter region layer is formed on the surface of the N-type doped monocrystalline silicon emitter region cap layer, an emitter region electrode contact table top and left and right lateral side region electrode contact table tops are formed by etching the N-type heavily doped polycrystalline silicon emitter region layer to the N-type doped monocrystalline silicon emitter region cap layer, left and right lateral collector region electrode contact table tops are formed by etching the N-type heavily doped polycrystalline silicon emitter region layer to the metal silicide thin layer, an oxide layer covers the whole surface of the table top structure, corresponding electrode contact windows are formed by etching the oxide layers corresponding to the base region, the collector region and the middle emitter region, and corresponding electrode contact windows are formed by etching the oxide layer_1-xGe_xA base electrode contact area is formed by etching the base layer, a corresponding metal electrode is formed on the electrode contact window, and P-type heavily doped beta-Si is deposited in the base electrode contact area_1-yC_yAnd 0.02<y<0.05。

Further, the thickness of the N-type heavily doped monocrystalline silicon layer is 200 nm.

Further, the thin metal silicide layer is CoSi with the thickness of 5nm₂。

Go toStep (b), the P type heavily doped Si_1-xGe_xThe thickness of the base region layer is 20-30 nm.

Further, the thickness of the cap layer of the N-type doped monocrystalline silicon emitting region is 10nm, and the thickness of the N-type heavily doped polycrystalline silicon emitting region layer is 0.5 mu m.

Further, the oxide layer is SiO with the thickness of 10nm₂。

The invention also provides a preparation method of the mesa Schottky region NPN SiGe HBT device, which comprises the following steps:

s1, preparing a doping concentration of 10¹⁵cm^-3After that, a layer of doping concentration of 1 multiplied by 10 is grown on the surface of the N type lightly doped monocrystalline silicon substrate by CVD¹⁹cm^-3Cleaning and chemically-mechanically polishing the surface of the N-type heavily-doped monocrystalline silicon layer;

s2, growing a layer of metal with the thickness of 5nm on the surface of the N-type heavily-doped monocrystalline silicon layer by utilizing physical vapor deposition, and then carrying out rapid thermal annealing treatment to oxidize the metal and the monocrystalline silicon surface below to form a metal silicide thin layer as a collector region;

s3, depositing a layer of thin P-type heavily doped Si on the surface of the metal silicide thin layer by using molecular beam epitaxy technology_1-xGe_xBase region layer with Ge group x of 0.1<x<0.3, doping concentration of 1X 10¹⁹cm^-3(ii) a Then heavily doping Si in P type_1-xGe_xA cap layer of an N-type doped monocrystalline silicon emitter region is continuously grown on the surface of the base region layer, and the doping concentration is 5 multiplied by 10¹⁷cm^-3(ii) a Finally, depositing a layer of N-type heavily doped polysilicon emitter region layer with typical thickness of 0.5 μm on the surface of the cap layer of the N-type doped monocrystalline silicon emitter region, with doping concentration of 2 × 10¹⁹cm^-3；

S4, etching an emitter and a base region from the N-type heavily doped polycrystalline silicon emitter region layer to the N-type doped monocrystalline silicon emitter region cap layer according to the emitter width preset by the device, and then etching a collector region from the N-type heavily doped polycrystalline silicon emitter region layer to the metal silicide thin layer to form a mesa structure;

s5, forming an oxide layer covering the whole mesa by dry oxygen oxidation on the etched mesa structure, determining electrode contact windows of the emitter, the base and the collector, and etching off the oxide layer of the emitter region, the base region and the collector region window and the P-type heavily doped Si below the base region window_1-xGe_xBase region, then Si etched away_1-xGe_xThe doping concentration of the region is 2 multiplied by 10¹⁹cm^-3P-type heavily doped beta-Si_1-yC_yThe value of the component C y is 0.02<y<And 0.05, finally depositing metal on electrode contact windows of the emitter region, the base region and the collector region to be used as an emitter electrode, a base electrode and a collector electrode, and finishing the manufacture of the device.

Further, in the step S1, the N-type lightly doped monocrystalline silicon substrate is a semi-insulating monocrystalline silicon substrate having a (100) crystal plane.

Further, in step S2, the metal grown on the surface of the heavily doped N-type monocrystalline silicon layer is Co, and Co is oxidized with the underlying monocrystalline silicon surface to form CoSi₂。

Further, in the step S5, the oxide layer is 100nm thick SiO₂And oxidizing the layer.

Compared with the prior art, the mesa Schottky collector region NPN SiGe HBT device and the preparation method thereof provided by the invention have the following technical advantages:

1. using extremely thin layers of metal silicides, e.g. CoSi₂Forming Si/CoSi with the single crystal silicon of the base region₂The Schottky contact ensures excellent contact interface characteristics, can improve the switching speed and cut-off frequency of the device, is compatible with the conventional silicon-based process, and has relatively simple process;

2. in Si_1-xGe_xThe beta-Si is formed on two sides of the base region in the form of 'embedded' growth_1-yC_yIn the base contact region (note: forming a base metal electrode in contact with a metal) of (1) satisfying the condition of Si_1-xGe_xHas a lattice constant greater than that of Si_1-yC_yThe values of x and y can be flexibly designed under the condition of the lattice constant, so that the design freedom of the device is improved; at this time, due to lattice mismatch, both sidesSi of (2)_1-yC_yFor intermediate Si_1-xGe_xThe base region generates a transverse uniaxial tensile stress effect and a longitudinal compressive stress effect, wherein the longitudinal compressive stress can not only effectively improve the mobility of a base region cavity, but also improve the mobility of base region electrons, thereby reducing the base region transit time and improving the cut-off frequency of a device;

3. the method uses a very thin N-type doped monocrystalline silicon emitter region cap layer and a very thick N-type heavily doped polycrystalline silicon emitter region layer as a combined emitter structure, and adopts P-type heavily doped Si according to the principle of elastomechanics_1-xGe_xThe transverse uniaxial tensile stress of the base region layer can be conducted into the upper N-type doped monocrystalline silicon emitter cap layer to form a strained silicon layer with compressive strain, namely the N-type doped monocrystalline silicon emitter cap layer is also subjected to tensile strain Si_1-xGe_xUniaxial compressive strain silicon is formed under the influence of the base region, and the compressive strain silicon cap layer can further improve the injection efficiency of the emitter and the cut-off frequency and the direct-current amplification factor (gain) of the device.

Drawings

Fig. 1 is a schematic structural diagram of a mesa schottky collector NPN SiGe HBT device provided in the present invention.

Fig. 2a to 2e are schematic cross-sectional structures of the mesa schottky collector NPN SiGe HBT device provided in the present invention at various stages of the process.

Detailed Description

In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further explained below by combining the specific drawings.

In the description of the present invention, it is to be understood that the terms "longitudinal", "radial", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. In the description of the present invention, "a plurality" means two or more unless otherwise specified.

Referring to fig. 1, the present invention provides a mesa schottky collector NPN SiGe HBT device, which comprises an N-type lightly doped monocrystalline silicon substrate, wherein an N-type heavily doped monocrystalline silicon layer is formed on a surface of the N-type lightly doped monocrystalline silicon substrate, a metal silicide thin layer is formed on a surface of the N-type heavily doped monocrystalline silicon layer, the N-type heavily doped monocrystalline silicon layer and the metal silicide thin layer thereon form a "combined collector" structure, and a P-type heavily doped Si is formed on a surface of the metal silicide thin layer_1-xGe_xBase layer, wherein x represents the molar content of Ge (germanium), in particular 0.1<x<0.3, the P type heavily doped Si_1-xGe_xAn N-type doped monocrystalline silicon emitter region cap layer is formed on the surface of the base region layer, an N-type heavily doped polycrystalline silicon emitter region layer is formed on the surface of the N-type doped monocrystalline silicon emitter region cap layer, the N-type heavily doped polycrystalline silicon emitter region layer and the N-type doped monocrystalline silicon emitter region cap layer form a combined emitter electrode structure, an emitter region electrode contact table top and left and right lateral group region electrode contact table tops are formed by etching from the N-type heavily doped polycrystalline silicon emitter region layer to the N-type doped monocrystalline silicon emitter region, the emitter region electrode contact table top is located in the middle, the base region electrode contact table tops are located on the left side and the right side of the emitter region electrode contact table top, the left side collector region electrode contact table top is located on the left side of the left side electrode base region contact table top by etching from the N-type heavily doped polycrystalline silicon emitter region layer to, the right collector region electrode contact mesa is positioned on the right side of the right base region electrode contact mesa, the whole surface of the mesa structure is covered with an oxide layer, corresponding electrode contact windows, namely a base region window, a collector region window and an emitter region window, are formed on the oxide layer corresponding to the base region, the collector region and the middle emitter region, and a P-type heavily doped Si window is arranged below the base region window_1-xGe_xEtching the base region layer to form a base electrode contact regionCorresponding metal electrodes, namely a base electrode, a collector electrode and an emitter electrode, are formed on the electrode contact window, and P-type heavily doped beta-Si is deposited in the base region electrode contact area_1-yC_yI.e. heavily doped with Si in the P-type_1-xGe_xThe left and right sides of the base region layer are the existing P-type heavily doped beta-Si_1-yC_y(cubic Si)_1-yC_y) Material, wherein y represents the molar content of C (carbon), in particular 0.02<y<0.05。

In a specific embodiment, the thickness of the N-type heavily doped monocrystalline silicon layer is 200nm, and the thicker polycrystalline silicon layer is beneficial to reducing the square resistance of the collector region and improving the working frequency.

As a specific embodiment, the interface morphology and the interface state at the interface of the metal silicide thin layer and the monocrystalline silicon contact in the N-type heavily doped monocrystalline silicon layer below the metal silicide thin layer have great influence on the device characteristics, and according to the conventional silicon process at present, a layer of extremely thin CoSi (usually less than 10 nanometers) with good interface morphology and interface state can be grown on the monocrystalline silicon material₂And CoSi₂The barrier height in contact with N-type single crystal silicon is about 0.7eV, so CoSi₂Is the preferred metal silicide material for forming the collector schottky barrier. As a preferred embodiment, the thin layer of metal silicide CoSi₂Is 5 nm.

As a specific embodiment, the P type heavily doped Si_1-xGe_xThe thickness of the base region layer is 20-30nm, so that the base region transition time can be favorably reduced by reducing the thickness of the base region as much as possible under the condition of ensuring that the SiGe layer of the base region is not relaxed, but the square resistance of the base region is increased if the thickness of the base region layer is too small.

As a specific embodiment, the thickness of the cap layer of the N-type doped monocrystalline silicon emitter region is 10nm, and the thickness of the N-type heavily doped polycrystalline silicon emitter region layer is 0.5 μm, so that the thicker polycrystalline silicon layer is beneficial to reducing the square resistance of the emitter region.

As a specific embodiment, the oxide layer is SiO with the thickness of 100nm₂And oxidizing the layer, thereby being beneficial to reducing the self-heating effect of the device.

The invention also provides a preparation method of the mesa Schottky region NPN SiGe HBT device, which comprises the following steps:

s1, preparing a doping concentration of 10¹⁵cm^-3Then a layer of 200nm thick doping concentration of 1 multiplied by 10 is grown on the surface of the N type lightly doped monocrystalline silicon substrate by CVD¹⁹cm^-3Cleaning and chemical mechanical polishing the surface of the heavily doped monocrystalline silicon layer to generate metal silicide on the heavily doped monocrystalline silicon layer, and the specific structure is shown in fig. 2 a;

s2, depositing and growing a layer of metal with the thickness of 5nm on the surface of the N-type heavily doped monocrystalline silicon layer by using the existing Physical Vapor Deposition (PVD) method, and then carrying out Rapid Thermal Annealing (RTA) treatment to oxidize the metal and the monocrystalline silicon surface below to form a metal silicide thin layer as a collector region; as a specific implementation mode, the metal grown on the surface of the N-type heavily doped monocrystalline silicon layer is Co, and the Co is oxidized with the surface of the lower monocrystalline silicon layer to form CoSi₂Mixing CoSi₂As a collector region, please refer to fig. 2b for a specific structure;

s3, depositing a layer of P-type heavily doped Si with thickness of 30nm on the surface of the metal silicide thin layer by using the existing Molecular Beam Epitaxy (MBE) technology_1-xGe_xThe base region layer has Ge component x with value of 0.1<x<0.3, doping concentration of 1X 10¹⁹cm^-3(ii) a Then heavily doping Si in P type_1-xGe_xA cap layer of an N-type doped monocrystalline silicon emitter region is continuously grown on the surface of the base region layer, and the doping concentration is 5 multiplied by 10¹⁷cm^-3(ii) a Finally, depositing a layer of N-type heavily doped polysilicon emitter region layer with typical thickness of 0.5 μm on the surface of the cap layer of the N-type doped monocrystalline silicon emitter region, with doping concentration of 2 × 10¹⁹cm^-3The specific structure is shown in fig. 2 c;

s4, etching an emitter and a base region from the N-type heavily doped polycrystalline silicon emitter region layer to the N-type doped monocrystalline silicon emitter region cap layer according to the emitter width preset by the device, wherein the emitter region is positioned in the middle of the base region, namely the base region is positioned on two sides of the emitter region, then etching a collector region from the N-type heavily doped polycrystalline silicon emitter region layer to the metal silicide thin layer to form a mesa structure, and the collector region is positioned on two sides of the base region, wherein the specific structure is shown in figure 2 d;

s5, forming an oxide layer covering the whole mesa by dry oxygen oxidation on the whole etched mesa structure, such as SiO with a thickness of 10nm₂Determining electrode contact windows of an emitter, a base and a collector as an oxide layer, etching the oxide layer of the emitter region, the base region and the collector region window, and etching P-type heavily doped Si below the base region window_{1- x}Ge_xBase region, then Si etched away_1-xGe_xThe doping concentration of the region is 2 multiplied by 10¹⁹cm^-3P-type heavily doped beta-Si_1-yC_yI.e. heavily doped with Si in the P-type_1-xGe_xThe left and right sides of the base region layer are deposited with the existing P-type heavily doped beta-Si_1-yC_y(cubic Si)_1-yC_y) The value of the component C, y, is 0.02<y<And 0.05, finally depositing metal on electrode contact windows of the emitter region, the base region and the collector region to be used as an emitter electrode, a base electrode and a collector, and finishing the manufacturing of the device, wherein the specific structure is shown in figure 2 e.

As a specific embodiment, in step S1, the N-type lightly doped monocrystalline silicon substrate is a semi-insulating monocrystalline silicon substrate having a (100) crystal plane, where the (100) crystal plane is a preferred crystal plane of a silicon-based process, and the surface state of the crystal plane is relatively small, and the lightly doped or semi-insulating monocrystalline silicon substrate is favorable for reducing the substrate leakage current.

Compared with the prior art, the mesa Schottky collector region NPN SiGe HBT device and the preparation method thereof provided by the invention have the following technical advantages:

1. using extremely thin layers of metal silicides, e.g. CoSi₂Forming Si/CoSi with the single crystal silicon of the base region₂The Schottky contact ensures excellent contact interface characteristics, can improve the switching speed and cut-off frequency of the device, is compatible with the conventional silicon-based process, and has relatively simple process;

2. in Si_1-xGe_xThe beta-Si is formed on two sides of the base region in the form of 'embedded' growth_1-yC_yIn the base contact region (note: forming a base metal electrode in contact with a metal) of (1) satisfying the condition of Si_1-xGe_xHas a lattice constant greater than that of Si_1-yC_yThe values of x and y can be flexibly designed under the condition of the lattice constant, so that the design freedom of the device is improved; in this case, Si on both sides is formed due to lattice mismatch_1-yC_yFor intermediate Si_1-xGe_xThe base region generates a transverse uniaxial tensile stress effect and a longitudinal compressive stress effect, wherein the longitudinal compressive stress can not only effectively improve the mobility of a base region cavity, but also improve the mobility of base region electrons, thereby reducing the base region transit time and improving the cut-off frequency of a device;

3. the method uses a very thin N-type doped monocrystalline silicon emitter region cap layer and a very thick N-type heavily doped polycrystalline silicon emitter region layer as a combined emitter structure, and adopts P-type heavily doped Si according to the principle of elastomechanics_1-xGe_xThe transverse uniaxial tensile stress of the base region layer can be conducted into the upper N-type doped monocrystalline silicon emitter cap layer to form a strained silicon layer with compressive strain, namely the N-type doped monocrystalline silicon emitter cap layer is also subjected to tensile strain Si_1-xGe_xUniaxial compressive strain silicon is formed under the influence of the base region, and the compressive strain silicon cap layer can further improve the injection efficiency of the emitter and the cut-off frequency and the direct-current amplification factor (gain) of the device.

Finally, the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all of them should be covered in the claims of the present invention.