阅读说明：本技术 一种氮化镓基场效应晶体管及其制备方法 (Gallium nitride-based field effect transistor and preparation method thereof ) 是由 于洪宇 曾凡明 汪青 林新鹏 周智辉 于 2019-11-19 设计创作，主要内容包括：本发明实施例公开了一种氮化镓基场效应晶体管及其制备方法,其中氮化镓基场效应晶体管结构包括：衬底、缓冲层、背势垒层、沟道层、势垒层、p型栅层和钝化层；与p型栅层接触的栅极,以及与势垒层接触的源极和漏极,其中,栅极位于第一区域,源极和漏极位于第二区域,p型栅层在第二区域的膜层中的p型掺杂剂未激活。显著改善了栅极刻蚀工艺,解决传统工艺中p型材料必须完全去除的问题,使得刻蚀的容错率更低,适合于大批量生产,这种技术方法增加了栅极刻蚀的工艺窗口宽度,不受刻蚀工艺精度限制,使得栅极刻蚀可控性高,重复性好。(The embodiment of the invention discloses a gallium nitride-based field effect transistor and a preparation method thereof, wherein the gallium nitride-based field effect transistor structure comprises: the device comprises a substrate, a buffer layer, a back barrier layer, a channel layer, a barrier layer, a p-type gate layer and a passivation layer; and a source and a drain in contact with the barrier layer, wherein the gate is located in the first region, the source and the drain are located in the second region, and the p-type dopant in the film layer of the p-type gate layer in the second region is not activated. The technical method increases the width of a process window of gate etching, is not limited by the precision of the etching process, and ensures high controllability and good repeatability of the gate etching.)

1. A gallium nitride-based field effect transistor, comprising:

the device comprises a substrate, a buffer layer, a back barrier layer, a channel layer, a barrier layer, a p-type gate layer and a passivation layer;

a gate in contact with the p-type gate layer, and a source and a drain in contact with the barrier layer, wherein the gate is in a first region, the source and the drain are in a second region, and the p-type dopant in the p-type gate layer in a film layer of the second region is not activated.

2. The gallium nitride-based field effect transistor of claim 1, wherein the p-type gate layer has a greater film thickness in the first region than in the second region.

3. The gallium nitride-based field effect transistor of claim 2, wherein the p-type gate layer has a film thickness in the second region in the range of 2nm to 300 nm.

4. The gallium nitride-based field effect transistor of claim 1, wherein the material of the p-type gate layer comprises at least one of p-GaN, p-AlGaN.

5. A preparation method of a gallium nitride-based field effect transistor is characterized by comprising the following steps:

providing an epitaxial wafer, wherein the epitaxial wafer comprises a substrate, a buffer layer, a back barrier layer, a channel layer, a barrier layer and a p-type gate layer; wherein the dopant in the p-type gate layer is not activated;

forming a grid mask on the surface of the p-type grid layer;

thinning the part of the p-type gate layer which is not covered by the gate mask;

removing the gate mask;

forming a dielectric isolation layer on the p-type gate layer;

etching the dielectric isolation layer to expose part of the p-type gate layer, wherein the exposed region of the p-type gate layer is a gate position region;

selectively activating dopants in a p-type gate layer of the gate location region;

forming a passivation layer on the p-type gate layer;

forming a grid electrode, a source electrode and a drain electrode; wherein the gate is formed in a first region, and the source and the drain are formed in a second region; in the first region, the p-type dopant of the p-type gate layer is activated, and in the second region, the p-type dopant of the p-type gate layer is not activated.

6. The method according to claim 5, wherein the forming a gate mask on the surface of the p-type gate layer comprises:

depositing a grid mask dielectric layer on the surface of the p-type grid layer;

manufacturing a photoresist mask on the surface of the grid mask dielectric layer;

and etching the grid mask dielectric layer to form a grid mask at the grid position, wherein the p-type grid layer which is not covered by the grid mask leaks out.

7. The method for manufacturing a gallium nitride-based field effect transistor according to claim 5, wherein the thinning of the portion of the p-type gate layer not covered by the gate mask comprises:

and etching the part of the p-type gate layer which is not covered by the gate mask so that the thickness of the part of the p-type gate layer which is not covered by the gate mask is smaller than that of the part of the p-type gate layer which is covered by the gate mask.

8. The method of claim 5, wherein the forming a gate in the first region comprises:

manufacturing a grid electrode contact window in the grid electrode position area in the first area through photoetching and etching, and activating the p-type grid electrode layer leaked from the grid electrode contact window;

and manufacturing a grid electrode in the grid electrode contact window, and making the grid electrode contact with the p-type grid electrode layer leaked from the contact window.

9. The method of manufacturing a gallium nitride-based field effect transistor according to claim 5, wherein forming the source electrode and the drain electrode in the second region comprises:

manufacturing an ohmic contact window at the source electrode position and the drain electrode position in the second region by etching; the ohmic contact window leaks out of a portion of the barrier layer;

evaporating ohmic contact metal at the source electrode position and the drain electrode position;

etching away metal materials except the ohmic contact metal on the source electrode position and the drain electrode position to form the source electrode and the drain electrode;

and annealing the source electrode and the drain electrode through an annealing process to form metal semiconductor ohmic contact.

10. The method of claim 5, wherein the forming the source and the drain in the second region comprises:

manufacturing an ohmic contact window at the source electrode position and the drain electrode position in the second region by etching; the ohmic contact window leaks out of a portion of the barrier layer;

forming a photoresist layer on the medium isolation layer;

removing the photoresist at the source electrode position and the drain electrode position;

evaporating ohmic contact metal at the source electrode position and the drain electrode position;

removing the photoresist layer;

and annealing the source electrode and the drain electrode through an annealing process to form metal semiconductor ohmic contact.

Technical Field

The embodiment of the invention relates to the technical field of semiconductor devices, in particular to a gallium nitride-based field effect transistor and a preparation method thereof.

Background

Conventional gallium nitride (GaN) -based heterojunction transistors are generally depletion-Mode normally-on structures (D-modes), and enhanced normally-off devices (E-modes) are more desirable in circuit design because circuits using such devices have high power-down safety and simple protection circuits. There are many conventional ways to implement an enhancement mode GaN-based heterojunction transistor, such as a trench gate structure, a gate bottom fluorine ion implantation, a metal insulator semiconductor gate structure incorporating a trench gate, a p-type gate structure, a stacked structure, and the like. The p-type gate structure is a common E-Mode structure, and is simple in structure and easy to process. The conventional process method for realizing the p-type gate is to use photoetching, dielectric deposition, corrosion and plasma dry etching (ICP) techniques to manufacture a mask at a gate prefabrication position, and then remove the p-type material in a region outside the gate prefabrication position by an etching method, thereby realizing the E-Mode device with the p-type gate structure.

Fig. 1 is a schematic diagram of a structure of a gan-based fet provided in the prior art, and referring to fig. 1, includes a substrate 10, a buffer layer 20, a back barrier layer 30, a channel layer 40, a barrier layer 50, a p-type gate layer 60, a passivation layer 70, a gate 80, a source 90, and a drain 100. It should be noted that after the epitaxial structure growth is completed, the conventional epitaxial wafer is annealed at high temperature under the nitrogen condition to activate the p-type dopant in the p-type gate layer, and the E-Mode field effect transistor with the p-type gate structure manufactured by adopting the etching process has some problems which are difficult to solve, although the E-Mode field effect transistor is easy to realize. In the etching of the p-gate, the very high etching selectivity ratio of the p-type gate layer to the barrier layer needs to be adjusted, so that the etching can be stopped on the surface of the barrier layer 50 after the p-type gate layer is completely removed. The over-etching of the barrier layer 50 may damage the barrier layer, and may also affect the two-dimensional electron gas concentration of the channel layer, reducing the device characteristics; if the etching is stopped before the barrier layer 50 is reached, the residual p-type gate layer material on the top of the barrier layer 50 is caused, and thus the two-dimensional electron gas in the channel layer is exhausted, and the current output capability of the device is reduced. The residue of p-type gate layer material can also lead to leakage between the gate and drain; although the etching conditions can be continuously improved, when the etching reaches the surface of the barrier layer, the material of the layer is damaged, so that the static and dynamic working characteristics of the device are deteriorated.

Disclosure of Invention

The embodiment of the invention provides a gallium nitride-based field effect transistor and a preparation method thereof, which can reduce the process fault tolerance and ensure the working characteristics of devices.

In a first aspect, an embodiment of the present invention provides a gallium nitride-based field effect transistor, including:

the device comprises a substrate, a buffer layer, a back barrier layer, a channel layer, a barrier layer, a p-type gate layer and a passivation layer;

the p-type gate layer is in contact with the p-type gate layer, and the source electrode and the drain electrode penetrate through the p-type gate layer and the passivation layer and are in contact with the barrier layer, wherein the gate electrode is located in a first region, the source electrode and the drain electrode are located in a second region, and p-type dopants in the p-type gate layer in a film layer of the second region are not activated.

Optionally, the film thickness of the p-type gate layer in the first region is greater than the film thickness of the second region.

Optionally, the thickness of the film layer of the p-type gate layer in the second region ranges from 2nm to 300 nm.

Optionally, the material of the p-type gate layer includes at least one of p-GaN and p-AlGaN.

In a second aspect, an embodiment of the present invention provides a method for manufacturing a gallium nitride-based field effect transistor, where the method includes:

providing an epitaxial wafer, wherein the epitaxial wafer comprises a stacked substrate, a buffer layer, a back barrier layer, a channel layer, a barrier layer and a p-type gate layer; wherein the dopant in the p-type gate layer is not activated;

forming a grid mask on the surface of the p-type grid layer;

thinning the part of the p-type gate layer which is not covered by the gate mask;

removing the gate mask;

forming a dielectric isolation layer on the p-type gate layer;

etching the dielectric isolation layer to expose part of the p-type gate layer, wherein the exposed region of the p-type gate layer is a gate position region;

selectively activating dopants in a p-type gate layer of the gate location region;

forming a passivation layer on the p-type gate layer;

forming a grid electrode, a source electrode and a drain electrode; wherein the gate is formed in a first region, and the source and the drain are formed in a second region; in the first region, the p-type dopant of the p-type gate layer is activated, and in the second region, the p-type dopant of the p-type gate layer is not activated.

Optionally, the forming a gate mask on the surface of the p-type gate layer includes:

depositing a grid mask dielectric layer on the surface of the p-type grid layer;

manufacturing a photoresist mask on the surface of the grid mask dielectric layer;

and etching the grid mask dielectric layer to form a grid mask at the grid position, wherein the p-type grid layer which is not covered by the grid mask leaks out.

Optionally, the thinning the portion of the p-type gate layer not covered by the gate mask includes:

and etching the part of the p-type gate layer which is not covered by the gate mask so that the thickness of the part of the p-type gate layer which is not covered by the gate mask is smaller than that of the part of the p-type gate layer which is covered by the gate mask.

Optionally, the forming a gate in the first region includes:

manufacturing a grid electrode contact window in the grid electrode position area in the first area through photoetching and etching, and activating the p-type grid electrode layer leaked from the grid electrode contact window;

and manufacturing a grid electrode in the grid electrode contact window, and making the grid electrode contact with the p-type grid electrode layer leaked from the contact window.

Optionally, the forming the source and the drain in the second region includes:

manufacturing an ohmic contact window at the source electrode position and the drain electrode position in the second region by etching; the ohmic contact window leaks out of a portion of the barrier layer;

evaporating ohmic contact metal at the source electrode position and the drain electrode position;

etching away metal materials except the ohmic contact metal on the source electrode position and the drain electrode position to form the source electrode and the drain electrode;

and annealing the source electrode and the drain electrode through an annealing process to form metal semiconductor ohmic contact.

Optionally, the forming the source and the drain in the second region includes:

manufacturing an ohmic contact window at the source electrode position and the drain electrode position in the second region by etching; the ohmic contact window leaks out of a portion of the barrier layer;

forming a photoresist layer on the medium isolation layer;

removing the photoresist at the source electrode position and the drain electrode position;

evaporating ohmic contact metal at the source electrode position and the drain electrode position;

removing the photoresist layer;

and annealing the source electrode and the drain electrode through an annealing process to form metal semiconductor ohmic contact.

The embodiment of the invention provides a gallium nitride-based field effect transistor and a preparation method thereof, wherein the gallium nitride-based field effect transistor comprises the following steps: the device comprises a laminated substrate, a buffer layer, a back barrier layer, a channel layer, a barrier layer, a p-type gate layer and a passivation layer; the p-type gate layer is in contact with the p-type gate layer, and the source electrode and the drain electrode penetrate through the p-type gate layer and the passivation layer and are in contact with the barrier layer, wherein the gate electrode is located in a first region, the source electrode and the drain electrode are located in a second region, and p-type dopants in the p-type gate layer in a film layer of the second region are not activated. The method has the advantages of good process repeatability, high controllability, no depletion of partial two-dimensional electron gas in the channel, no damage to the barrier layer and capability of avoiding the electric leakage phenomenon between the grid and the drain.

Drawings

FIG. 1 is a schematic diagram of a GaN-based field effect transistor provided in the prior art

Fig. 2 is a schematic structural diagram of a gallium nitride-based field effect transistor according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of another gallium nitride-based field effect transistor according to an embodiment of the present invention;

fig. 4A is a flowchart of a method for manufacturing a gallium nitride-based field effect transistor according to a second embodiment of the present invention;

fig. 4B-4J are cross-sectional views of structures of steps in a method for manufacturing a gallium nitride-based field effect transistor according to a second embodiment of the present invention;

fig. 5 is a flowchart of a method for forming a source and a drain in a second region according to a second embodiment of the invention;

fig. 6 is a flowchart of another method for forming a source and a drain in a second region according to a second embodiment of the invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

An embodiment of the present invention provides a gallium nitride-based field effect transistor, and referring to fig. 1, fig. 1 is a schematic structural diagram of a gallium nitride-based field effect transistor provided in an embodiment of the present invention, including:

a stacked substrate 10, a buffer layer 20, a back barrier layer 30, a channel layer 40, a barrier layer 50, a p-type gate layer 60, and a passivation layer 70;

a gate electrode 80 in contact with the p-type gate layer 60, and a source electrode 90 and a drain electrode 100 penetrating the p-type gate layer 60 and the passivation layer 70 and in contact with the barrier layer 50, wherein the gate electrode 80 is located in the first region 11, the source electrode 90 and the drain electrode 100 are located in the second region 12, and the p-type dopant in the p-type gate layer 60 in the film layer of the second region 12 is not activated.

Specifically, the epitaxial wafer in the gallium nitride-based field effect transistor comprises a substrate 10, a buffer layer 20, a back barrier layer 30, a channel layer 40, a barrier layer 50, a p-type gate layer 60 and a passivation layer 70 which are sequentially stacked from the bottom to the top of the structure; the substrate layer 10 may be a Si substrate, a sapphire substrate, or a GaN substrate; the buffer layer 20 can adopt a multilayer alternating periodic structure of AlN/GaN to realize stress release; the back barrier layer 30 may adopt an AlGaN barrier structure, in which the Al component is 5% to 35%; the channel layer 40 may employ GaN of this document as a channel layer; the barrier layer 50 may be made of AlGaN, wherein the composition of Al may be 5% to 35%; the p-type gate layer 60 is made of p-GaN or p-AlGaN material, wherein the p-type dopant can be Mg element, and the doping mode can be constant component doping, gradient doping, step doping or delta doping; the passivation layer 70 is made of a silicon nitride material;

a gate electrode 80 in contact with the p-type gate layer 60, and a source electrode 90 and a drain electrode 100 penetrating the p-type gate layer 60 and the passivation layer 70 and in contact with the barrier layer 50, wherein the gate electrode 80 is located in the first region 11, the source electrode 90 and the drain electrode 100 are located in the second region 12, the p-type dopant in the film layer of the second region 12 of the p-type gate layer 60 is not activated, and the p-type dopant in the film layer of the first region 11 is activated.

Compared with the problem that the p-type material at the top of the channel needs to be removed in the traditional process, the gallium nitride-based field effect transistor provided by the embodiment of the invention is changed into the proper p-type material (namely, the p-type gate layer of the second region is reserved), and even if the p-type gate layer is arranged in the second region, the p-type dopant in the p-type gate layer in the region is not activated, so that the gallium nitride-based field effect transistor can present a high-resistance state. In the prior art, a p-gate layer is activated first, and during etching of a p-gate, a very high etching selection ratio of a p-type gate layer to a barrier layer needs to be adjusted, so that after the p-type gate layer is completely removed, etching can be stopped on the surface of the barrier layer. The over-etching of the barrier layer can damage the barrier layer, so that the two-dimensional electron gas concentration of the channel layer can be influenced, and the characteristics of the device are reduced; if the etching is stopped before the barrier layer is not reached, the residual p-type gate layer material on the top of the barrier layer can be caused, so that the two-dimensional electron gas in the channel layer is exhausted, and the current output capacity of the device is reduced. The residue of p-type gate layer material can also lead to leakage between the gate and drain. In the embodiment of the invention, the p-type dopant in the p-type gate layer arranged in the second region is not activated and can be in a high-resistance state, so that the source electrode, the drain electrode and the gate electrode are in a blocking state, the characteristics of the device are not influenced, the barrier layer is not damaged in the process of etching the p-type gate layer to form the gate electrode, the process fault tolerance is lower, the precision of the etching process is not limited, the controllability is high, the repeatability is good, and the method is suitable for mass production.

Optionally, the film thickness of the p-type gate layer 60 in the first region 11 is greater than that of the second region 12.

Specifically, in the gate 80 etching process, during the etching process, the p-type gate layer 60 in the second region 12, the p-type gate layer 60 protruding from the first region 11, and the p-type gate layer 60 protruding from the first region 11 are required to be etched away, so as to prepare for manufacturing the gate 80, and thus the film thickness of the p-type gate layer 60 in the first region 11 is greater than that of the second region 12.

Optionally, the thickness of the p-type gate layer 60 in the second region 12 ranges from 2nm to 300 nm.

Specifically, the thickness of the p-type gate layer 60, which typically remains in the region beyond the gate 80 during the etching process, is about 5 nm. In practice, the remaining thickness of the p-type gate layer 60 is at least 2nm, at most the limit being that no gate etching process is used, i.e. the p-type gate layer 60 remains completely. The thickness of the p-type gate layer 60 is typically between 50-300nm, so the remaining thickness of the p-type gate layer 60 is in the range of 2-300 nm, and the remaining thickness of the second region 12 is determined by the original thickness of the p-type gate layer 60.

Optionally, the material of the p-type gate layer 60 includes at least one of p-GaN and p-AlGaN.

Specifically, p-GaN and p-AlGaN form polarization charges on the surface of the material or a heterointerface, so that high-concentration two-dimensional electron gas is generated, and the channel-to-point characteristic is excellent.

Optionally, referring to fig. 2, fig. 2 is a schematic structural diagram of another gallium nitride-based field effect transistor according to an embodiment of the present invention, and further includes a chip isolation region 110.

The embodiment of the invention provides a gallium nitride-based field effect transistor, which comprises: the device comprises a laminated substrate, a buffer layer, a back barrier layer, a channel layer, a barrier layer, a p-type gate layer and a passivation layer; and a source electrode and a drain electrode which penetrate through the p-type gate layer and the passivation layer and are in contact with the barrier layer, wherein the gate electrode is positioned in the first region, the source electrode and the drain electrode are positioned in the second region, and the p-type dopant of the p-type gate layer in the film layer of the second region is not activated. The selective area activation mode is adopted, so that only the p-type dopant at the position of the grid electrode is activated, the phenomenon that other residual p-type materials are activated to influence the characteristics of the device is avoided, the process repeatability is good, the controllability is high, the barrier layer is not damaged, the process window is wide, and the selective area activation method is very suitable for the mass production of the device.

Referring to fig. 4A, fig. 4A is a flowchart of a method for manufacturing a gallium nitride-based field effect transistor according to a second embodiment of the present invention, and fig. 4B to 4J are combined, where fig. 4B to 4J are structural cross-sectional views of steps in the method for manufacturing a gallium nitride-based field effect transistor according to the second embodiment of the present invention, and the method includes:

s10, providing an epitaxial wafer, wherein the epitaxial wafer comprises a laminated substrate, a buffer layer, a back barrier layer, a channel layer, a barrier layer and a p-type gate layer; wherein the dopant in the p-type gate layer is not activated.

Specifically, referring to fig. 4B, a buffer layer 20, a back barrier layer 30, a channel layer 40, a barrier layer 50, and an unactivated p-type gate layer 60 are sequentially formed on a substrate 10, wherein an AlN layer may be added between the barrier layer 50 and the channel layer 40 to optimize device characteristics. The substrate layer 10 may be a Si substrate, a sapphire substrate, or a GaN substrate; the buffer layer 20 can adopt a multilayer alternating periodic structure of AlN/GaN to realize stress release; the back barrier layer 30 may adopt an AlGaN barrier structure, in which the Al component is 5% to 35%; the channel layer 40 may employ GaN of this document as a channel layer; the barrier layer 50 may be made of AlGaN, wherein the composition of Al may be 5% to 35%; the p-type gate layer 60 is made of p-GaN or p-AlGaN material, wherein the p-type dopant can be Mg element, and the doping mode can be constant component doping, gradient doping, step doping or delta doping; the passivation layer 70 is made of silicon nitride material

And S20, forming a gate mask on the surface of the p-type gate layer.

Specifically, the gate mask formed on the surface of the p-type gate layer may be silicon oxide, silicon nitride or metal nickel, and the growth of the gate mask may be achieved by plasma enhanced vapor chemical deposition, electron beam evaporation or magnetron sputtering.

Optionally, forming a gate mask on the surface of the p-type gate layer includes:

depositing a grid mask dielectric layer on the surface of the p-type grid layer;

manufacturing a photoresist mask on the surface of the grid mask dielectric layer;

and etching the grid mask dielectric layer to form a grid mask at the grid position, and leaking the p-type grid layer which is not covered by the grid mask.

Exemplarily, referring to fig. 4C, a gate mask dielectric layer 61 is deposited on the surface of the p-type gate layer, the gate mask dielectric layer 61 is made of silicon oxide and formed to a thickness of 300nm, and the deposition is performed by PECVD using plasma enhanced chemical vapor deposition equipment; and (3) manufacturing a photoresist mask on the surface of the gate mask dielectric layer 61, referring to fig. 4D, etching the gate mask dielectric layer 61 by a dry etching method to manufacture a gate mask 62 at the gate position, wherein the photoresist can adopt a commonly used S1818, rihong 304 or AZ5214 photoresist.

And S30, thinning the part of the p-type gate layer which is not covered by the gate mask.

Specifically, referring to fig. 4E, portions of the p-type gate layer 60 in the second region 12 are removed by etching to thin the portions of the p-type gate layer not covered by the gate mask 62.

Optionally, thinning the portion of the p-type gate layer 60 not covered by the gate mask 62 includes:

the portion of the p-type gate layer 60 not covered by the gate mask 62 is etched such that the thickness of the p-type gate layer 60 not covered by the gate mask 62 is less than the thickness of the p-type gate layer 60 covered by the gate mask 62, i.e. the thickness of the p-type gate layer 60 in the second region 12 is less than the p-type gate layer 60 in the first region 11.

Specifically, after the gate mask 62 is manufactured, the epitaxial wafer is placed into a dry etching machine, the p-type gate layer 60 is etched, the portion not covered by the gate mask 62 is gradually etched and thinned, the portion with the gate mask 62 is completely reserved due to the blocking of the mask, the etching is completed, and the gate position is formed.

And S40, removing the gate mask.

Specifically, referring to fig. 4F, after the etching is completed, the gate position is formed, and the gate mask 62 is cleaned by wet etching.

And S50, forming a medium isolation layer on the p-type gate layer.

Specifically, referring to fig. 4G, after the gate mask 62 is cleaned by wet etching, a dielectric isolation layer 63 is deposited on the surface of the p-type gate layer 60, and the dielectric isolation layer 63 can be made of various high temperature resistant materials, such as aluminum oxide, silicon oxide, hafnium oxide, Indium Tin Oxide (ITO) and gallium oxide, for example, Al grown by using an atomic layer epitaxial ALD apparatus₂O₃The thin film forms a dielectric spacer 63 with a thickness of 200nm and a growth time of about 60 minutes. It should be noted, however, that reactants are avoided as much as possible from containing hydrogen during the growth of the material. In addition, the dielectric spacer 63 is not nitride to avoid the effects of nitrogen on the selective activation of the p-type dopant.

And S60, etching the medium isolation layer to expose part of the p-type gate layer, wherein the exposed region of the p-type gate layer is a gate position region.

Specifically, referring to fig. 4H, after the growth of the dielectric isolation layer 63 is completed, a gate top window is opened by photolithography and dry etching, so as to expose a portion of the p-type gate layer 60.

S70, selectively activating the dopant in the p-type gate layer in the gate location region.

Specifically, after a part of the p-type gate layer 60 is exposed, the epitaxial wafer is placed into an annealing furnace, annealing is carried out for 10-30 minutes in the range of 700-.

And S80, forming a passivation layer on the p-type gate layer.

Specifically, referring to fig. 4I, after the selective activation of the p-type dopant at the gate location is completed, the dielectric isolation layer 63 is removed, and a passivation layer 70 is formed on the p-type gate layer 60, and the passivation layer 70 is formed on the p-type gate layer 60, illustratively, by using silicon nitride, which serves as an insulating material.

S90, forming a grid electrode, a source electrode and a drain electrode; wherein a gate electrode is formed in the first region, and a source electrode and a drain electrode are formed in the second region, a p-type dopant of the p-type gate layer is activated in the first region, and a p-type dopant of the p-type gate layer is inactivated in the second region.

Specifically, referring to fig. 4J, the passivation layer 70 on the gate position of the first region 11 and the passivation layer 70 on the source electrode 11 and the drain electrode 12 in the second region 12 are removed, a gate metal is formed on the gate position of the first region 11 to form the gate electrode 80, and ohmic metals are formed on the source electrode 90 and the drain electrode 100 in the second region 12 to form the source electrode 90 and the drain electrode 100, respectively. Wherein the gate electrode 80 is formed in the first region 11, the p-type dopant of the p-type gate layer 60 in the film layer of the first region 11 is activated, the source electrode 90 and the drain electrode 100 are formed in the second region 12, and the p-type dopant of the p-type gate layer 60 in the film layer of the second region 12 is not activated.

Optionally, the forming a gate in the first region includes:

s91, manufacturing a gate contact window in the gate position area in the first area through photoetching and etching, and activating the p-type gate layer leaked from the gate window;

and S92, manufacturing a grid, wherein the grid is in contact with the leaked p-type grid layer through the grid contact window.

Illustratively, the gate 80 is formed in the first region 11, and the passivation layer 70 on the position where the gate 80 needs to be fabricated in the gate position region may be removed by a method combining a photolithography technique with a wet etching or a dry etching method to fabricate a gate contact window; and manufacturing a grid electrode at the position of the grid by photoetching and metal evaporation methods. The gate 80 and the p-type gate layer 60 may be ohmic contact or schottky contact; the electrode structure is preferably a laminated structure consisting of one or more of Ni, Ti, Al, Au, TiN, W, Pt, Pd and Mo. Wherein, the metal evaporation mode comprises a magnetron sputtering scheme, an electron beam evaporation scheme or an electroplating scheme.

Forming the source and drain in the second region includes various methods:

optionally, referring to fig. 5, fig. 5 is a flowchart of a method for forming a source and a drain in a second region according to a second embodiment of the present invention, where forming a source and a drain in a second region includes:

s93, manufacturing an ohmic contact window at the source electrode position and the drain electrode position in the second area through etching; the ohmic contact window leaks out of the barrier layer;

s94, evaporating ohmic contact metal at the source electrode position and the drain electrode position;

s95, etching away metal materials except the ohmic contact metal on the source electrode position and the drain electrode position to form a source electrode and a drain electrode;

and S96, annealing the source electrode and the drain electrode through an annealing process to form metal semiconductor ohmic contact.

Specifically, after the ohmic contact window is formed, the portion of the ohmic contact window that leaks out of the barrier layer 50 may leak out of the upper surface of the barrier layer 50, may leak out of the interior of the barrier layer 50, and may leak out of the surface of the channel layer 40 through the barrier layer 50, which is not limited herein; ohmic contact metal is evaporated at the source electrode position and the drain electrode position, then photoresist is coated on the passivation layer 70, the photoresist is left at the positions where the source electrode and the drain electrode are required to be manufactured in a photoetching exposure mode, then ohmic metal at the positions where the photoresist is not covered is removed through a dry etching or corrosion method, and metal at the positions where the photoresist is covered is left as source electrode 90 metal and drain electrode 100 metal. And the ohmic metal adopts high-temperature rapid annealing equipment to carry out thermal annealing on the source electrode 90 metal and the drain electrode 100 metal so as to realize a source-drain M contact structure. Depending on the material and composition of the metal electrode, the annealing temperature is generally 500 ℃ to 900 ℃, and the annealing environment is a nitrogen environment.

Optionally, referring to fig. 6, fig. 6 is a flowchart of another method for forming a source and a drain in a second region according to the second embodiment of the present invention, where forming a source and a drain in a second region includes:

s97, manufacturing an ohmic contact window at the source electrode position and the drain electrode position in the second area through etching; ohmic contact windows leak out of portions of the barrier layer;

s98, forming a photoresist layer on the medium isolation layer;

s99, removing the photoresist at the source electrode position and the drain electrode position;

s100, evaporating ohmic contact metal at the source electrode position and the drain electrode position;

s101, removing the photoresist layer;

and S102, annealing the source electrode and the drain electrode through an annealing process to form metal semiconductor ohmic contact.

Specifically, after the ohmic contact window is formed, the portion of the ohmic contact window that leaks out of the barrier layer 50 may leak out of the upper surface of the barrier layer 50, may leak out of the interior of the barrier layer 50, and may leak out of the surface of the channel layer 40 through the barrier layer 50, which is not limited herein; firstly, coating photoresist on the passivation layer 70, removing the photoresist at the positions where the source electrode 90 and the drain electrode 100 are required to be manufactured in a photoetching exposure mode, continuing to evaporate ohmic contact metal, and then removing the photoresist; in this way, ohmic contact metal exists only at the positions of the source and drain electrodes 90 and 100 to form the source and drain electrodes 90 and 100, and metal at other positions is removed along with the photoresist. And the ohmic metal adopts high-temperature rapid annealing equipment to carry out thermal annealing on the source electrode 90 metal and the drain electrode 100 metal so as to realize a source-drain M contact structure. Depending on the material and composition of the metal electrode, the annealing temperature is generally 500 ℃ to 900 ℃, and the annealing environment is a nitrogen environment.

The embodiment of the invention provides a preparation method of a gallium nitride-based field effect transistor, which comprises the following steps: providing an epitaxial wafer, wherein the epitaxial wafer comprises a laminated substrate, a buffer layer, a back barrier layer, a channel layer, a barrier layer and a p-type gate layer; wherein the dopant in the p-type gate layer is not activated; forming a grid mask on the surface of the p-type grid layer; thinning the part of the p-type gate layer which is not covered by the gate mask; removing the gate mask; forming a dielectric isolation layer on the p-type gate layer; etching the dielectric isolation layer to expose part of the p-type gate layer, wherein the exposed region of the p-type gate layer is a gate position region; selectively activating a dopant in a p-type gate layer of the gate location region; forming a passivation layer on the p-type gate layer; forming a grid electrode, a source electrode and a drain electrode; wherein a gate is formed in the first region, a p-type dopant in a film layer of the p-type gate layer is activated, a source and a drain are formed in the second region, and the p-type dopant in the film layer of the p-type gate layer is not activated. The method can improve the gate etching process, overcomes the problem that the p-type material at the top of the channel needs to be completely removed in the traditional process, can properly reserve the p-type material, can reduce the fault tolerance rate of etching because the p-type dopant is not activated and is in a high resistance state, and is suitable for mass production.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.