阅读说明：本技术 相变化记忆体结构
(Phase change memory structure
) 是由 吴昭谊 于 2019-07-04 设计创作，主要内容包括：一种相变化记忆体结构包括以下各项。基板。在基板上设置的底部电极。在底部电极上设置的绝缘层,绝缘层具有在绝缘层中定义的通孔。在通孔中设置的加热器。在加热器上设置的相变材料层。在相变材料层上设置的选择器层。在通孔上设置的中间层。此外,金属层设置在选择器层上。金属层宽于相变材料层。(A phase change memory structure includes the following. A substrate. A bottom electrode disposed on the substrate. An insulating layer is disposed on the bottom electrode, the insulating layer having a via defined therein. A heater disposed in the through hole. A phase change material layer disposed on the heater. A selector layer disposed on the phase change material layer. An intermediate layer disposed over the via. Further, a metal layer is disposed on the selector layer. The metal layer is wider than the phase change material layer.)
1. A phase change memory structure, comprising:
a substrate;
a bottom electrode disposed on the substrate;
an insulating layer disposed on the bottom electrode, the insulating layer having a via defined therein;
a heater disposed in the through hole;
a phase change material layer disposed on the heater;
a selector layer disposed on the phase change material layer;
an intermediate layer on the via; and
a metal layer disposed on the selector layer.
Technical Field
The present disclosure relates to Phase Change Random Access Memory (PCRAM) devices and methods of making the same. In particular, in some embodiments of the present disclosure, the present application discloses a Phase Change Random Access Memory (PCRAM) having an all-TaN Bottom Electrode (BE) structure and a method of fabricating the same.
Background
Phase Change Random Access Memory (PCRAM) is a non-volatile memory element that utilizes different resistive phases and thermally induced phase transitions between phases of phase change material including chalcogenide (chalcogenide) and resistive materials. Phase change random access memories are made up of a plurality of cells (cells), each of which functions independently. Phase change random access memory cells generally include a heater and a resistor, which is a data storage element made primarily of a reversible phase change material to provide at least two significantly different resistivities for a logic "0" state and a "1" state.
Disclosure of Invention
According to an embodiment of the present disclosure, a phase change memory structure is provided, which includes: the phase change memory device includes a substrate, a bottom electrode disposed on the substrate, an insulating layer disposed on the bottom electrode, wherein the insulating layer has a via defined in the insulating layer, a heater disposed in the via, a phase change material layer disposed on the heater, a selector layer disposed on the phase change material layer, an intermediate layer disposed on the via, and a metal layer disposed on the selector layer.
Drawings
The present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIG. 1(a) is a top view of a phase change random access memory according to one embodiment of the present disclosure, and FIG. 1(b) is a cross-sectional view of the phase change random access memory along line I-I' of FIG. 1 (a);
FIG. 2(a) is a top view of a phase change random access memory according to another embodiment of the present disclosure, and FIG. 2(b) is a cross-sectional view of the phase change random access memory along line I-I' of FIG. 2 (a);
FIG. 3(a) is a top view of a phase change random access memory according to another embodiment of the present disclosure, and FIG. 3(b) is a cross-sectional view of the phase change random access memory along line I-I' of FIG. 3 (a);
FIG. 4 is a cross-sectional view of a phase change random access memory according to another embodiment of the present disclosure;
FIG. 5(a) illustrates a cross-sectional view of a phase change random access memory according to another embodiment of the present disclosure, and FIG. 5(b) illustrates a cross-sectional view of an alternative embodiment of the phase change random access memory of FIG. 5 (a);
FIG. 6(a) shows a cross-sectional view of a phase change random access memory according to another embodiment of the present disclosure, and FIGS. 6(b) and 6(c) show cross-sectional views of alternative embodiments of the phase change random access memory of FIG. 6 (a);
FIG. 7(a), FIG. 7(b), FIG. 7(c), FIG. 7(d), FIG. 7(e), FIG. 7(f), and FIG. 7(g) illustrate sequential manufacturing operations for forming a phase change random access memory, in accordance with embodiments of the present disclosure;
FIGS. 8(a), 8(b), 8(c), 8(d), 8(e), 8(f), 8(g), 8(h), and 8(i) illustrate sequential manufacturing operations for forming a phase change random access memory according to embodiments of the present disclosure;
FIG. 9(a), FIG. 9(b), FIG. 9(c), FIG. 9(d), FIG. 9(e), FIG. 9(f), FIG. 9(g), and FIG. 9(h) illustrate sequential manufacturing operations for forming a phase change random access memory according to embodiments of the present disclosure;
FIG. 10(a), FIG. 10(b), FIG. 10(c), FIG. 10(d), FIG. 10(e), FIG. 10(f), and FIG. 10(g) illustrate sequential manufacturing operations for forming a phase change random access memory, in accordance with embodiments of the present disclosure;
FIG. 11 illustrates a method of forming a phase change random access memory, in accordance with an embodiment of the present disclosure;
12(a), 12(b), 12(c), 12(d), 12(e), and 12(f) illustrate successive manufacturing operations to form a heater in a via hole, according to embodiments of the present disclosure;
13(a), 13(b), 13(c), and 13(d) illustrate successive fabrication operations for depositing a two-dimensional layer on top of a heater in forming a phase change random access memory according to an embodiment of the present disclosure;
14(a) and 14(c) illustrate the structure of the top and bottom electrodes coupled to the heater; fig. 14(b) illustrates the element analysis result.
[ notation ] to show
100 substrate
110 metal layer
120 bottom electrode
120' top electrode
130 first phase change material layer
130' second phase change material layer
140 first heater
140' second heater
150 insulating layer
150' insulating layer
150' insulating layer
160 first selector layer
160' second selector layer
170 intermediate layer
170' intermediate layer
190 two-dimensional layer
h. h' through hole
S111 operation
S112 operation
S113 operation
S114 operation
S115 operation
S116 operation
S117 operation
S118 operation
Detailed Description
It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of the elements are not limited to the disclosed ranges or values, but may depend on the process conditions and/or the desired properties of the elements. Furthermore, forming a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed interposing the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for the sake of simplicity and clarity.
Additionally, spatially relative terms (such as "under," "below," "lower," "over," "upper," and the like) may be used herein for ease of description to describe one element or feature's relationship to another element (or elements) or feature (or features) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Furthermore, the term "made of … (made of)" may mean "comprising" or "consisting of … (stabilizing of)". In the present disclosure, the phrase "one of A, B and C" means "A, B and/or C" (A, B, C, a and B, a and C, B and C, or A, B and C), and does not mean one element from a, one element from B, and one element from C, unless otherwise described.
Generally, to read a state (data) from a phase change random access memory cell, a sufficiently small current is applied to the phase change material without triggering the heater to generate heat. In this way, the resistivity of the phase change material can be measured and the state representing the resistivity can be read, i.e., the "0" state is high resistivity or the "1" state is low resistivity. To write a state (data) into a phase change random access memory cell, for example, to write a "1" state representing a low resistivity phase of the phase change material, a moderate current is applied to a heater that generates heat to anneal the phase change material at a temperature above the crystallization temperature but below the melting temperature for a period of time to reach a crystalline phase. To write a "0" state representing a high resistivity phase of the phase change material, a very large current is applied to a heater to generate heat to melt the phase change material at a temperature higher than a melting temperature of the phase change material; and abruptly switching off the current to lower the temperature below the crystallization temperature of the phase change material to quench and stabilize the amorphous structure of the phase change material so as to reach a high resistance logic "0" state. Very large currents may therefore be in the form of pulses. In the present disclosure, phase change random access memories with improved cell structures are described.
Fig. 1(a) is a top view of a phase change random access memory having a substrate 100, a bottom electrode 120 (wherein the bottom electrode may be a bit line) formed on the substrate 100, a phase change material layer 130 formed on the bottom electrode 120, and a metal layer 110 formed on the phase change material layer 130. In this embodiment, the phase change material layer 130 is the same size as the overlapping area between the bottom electrode 120 and the metal layer 110 serving as the top electrode.
In some embodiments, the substrate 100 comprises a single crystal semiconductor material such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In certain embodiments, the substrate 100 is made of crystalline Si. In some embodiments, the metal layer 110 and the bottom electrode 120 are formed of the same material or different materials, including one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, carbon, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys (such as aluminum copper alloys), other suitable materials, and/or combinations thereof. In some embodiments, each of the metal layer 110 and the bottom electrode 120 has a thickness in the range of about 20 to about 2,000 nm. In some embodiments, the substrate 100 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate, fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods. In some embodiments, substrate 100 includes transistors, such as MOSFET planar transistors, fin field effect transistors (finfets), and Gate All Around (GAA) transistors, metal lines, such as polysilicon lines and interconnect metal lines, and transistors that control the operation of the phase change random access memory. In some embodiments, the bottom electrode 120 is a metal line connected to a transistor included in the substrate 100.
Fig. 1(b) shows a cross-sectional view of a phase change random access memory having an insulating layer 150 comprising a via h. In the through hole h, the heater 140 is formed. In some embodiments, the heater 140 is formed of a thin film material of TiN, TaN, or TiAlN having a thickness in a range of about 5 to about 15nm to provide joule heating to the phase change material layer 130. Further, the heater 140 may function as a heat sink during quenching (during sudden cut-off of current applied to the heater 140 to "freeze" the amorphous phase). The heater 140 fills the via h in the insulating layer 150, which prevents heat transfer between the phase change random access memory cells to avoid thermal disturbances that can disable the state retention (disable) or interrupt the read/write process.
In some embodiments, the insulating layer 150 is comprised of, but is not limited to: silicon oxide (SiO)2) Silicon nitride (Si)3N4) Silicon oxynitride (SiON), SiOCN, SiCN, Al2O3Fluorine doped silicate glass (FSG), low dielectric constant dielectric materials, or various other suitable dielectric materials used in the manufacture of semiconductor devices. The insulating layer 150 disposed on the patterned bottom electrode 120 is an electrical and thermal insulator, and in some embodiments, has a thickness in the range of about 5nm to about 350 nm.
The phase change material layer 130 receives heat generated by the heater 140, and a region (referred to as an "active region") near an interface between the phase change material layer 130 and the heater 140 undergoes a phase transition from a crystalline phase to an amorphous phase or vice versa, depending on the amount and duration of heat generated when current is applied to the heater 140. In the embodiment of fig. 1(b), the active region has a mushroom-shape (fig. 1(b)), while the region outside the active region does not undergo phase transition and may serve as a thermal insulation layer to preserve heat inside the mushroom-shaped active region. The smaller the active region, the less heat and therefore the less current required to write to the phase change random access memory cell. In some embodiments, the material of the phase change material layer 130 is: binary systems of Ga-Sb, In-Se, Sb-Te, Ge-Te, and Ge-Sb; ternary systems of Ge-Sb-Te, In-Sb-Te, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, and Ga-Sb-Te; or a quaternary system of Ag-In-Sb-Te, Ge-Sn-Sb-Te, Ge-Sb-Se-Te, Te-Ge-Sb-S, Ge-Sb-Te-O, and Ge-Sb-Te-N. In some embodiments, the material of the phase change material layer 130 is a chalcogenide alloy containing one or more elements from group IV of the periodic Table, such as having 5nm to 100nmOf a thickness of GST, Ge-Sb-Te alloy (e.g., Ge)2Sb2Te5). The phase change material layer 130 may include other phase change resistance materials such as metal oxides including tungsten oxide, nickel oxide, copper oxide, and the like. The phase transition between the crystalline and amorphous phases of the phase change material is related to the interaction between the long range order (long range order) and the short range order (short range order) of the structure of the phase change material. For example, collapse of long range order produces an amorphous phase. Long range order in the crystalline phase promotes conductivity, while the amorphous phase hinders conductivity and results in high resistance. In order to tune the properties of the phase change material layer 130 for different requirements, the material of the phase change material layer 130 may be doped with various elements (e.g., B, Al, As, Ga, or P) in different amounts to adjust the ratio of short-range order and long-range order inside the bonding structure of the material. The doping element may be any element that is doped by using a semiconductor, such as ion implantation.
The selector layer 160 is formed on the phase change material layer 130, and the metal layer 110 and the intermediate layer 170 are formed on the selector layer 160. In a phase change memory array (e.g., a cross-point array having hundreds or more memory cells), numerous problems can occur that interfere with proper operation of the memory cells. These problems can be electrical in nature, such as leakage currents, parasitic capacitances, and the like. These problems can also be thermal in nature, such as thermal perturbations between memory cells. To address the above issues, switching elements are used to reduce or avoid leakage currents from operating memory cells or from other memory cells passing along a resistive network. By using the switching element, the heaters of the other memory cells are not accidentally turned on by the leakage current, thereby erasing the state recorded in the memory cell. Using a switching element that functions like a diode element or a transistor element, allows only the desired phase change RAM cell to be selected for reading/writing, while the other phase change RAM cells are non-conducting, and reduces or prevents leakage current from the selected phase change RAM cell. To provide accurate read/write operations, it is desirable to form a layer of phase change material 130 having a high on-state conductivity and noneThe selector layer, which limits off-state resistance, reduces power dissipation, leakage current, and cross-talk disturbances in the resistance network of the phase change random access memory, ensuring that only selected phase change random access memory cells undergo read/write operations. In this way, a reliable phase change random access memory can be formed. In view of the size of the switching element, diode type (such as p-n junction diode, schottky diode, metal-insulator transition (MIT), and Ovonic Threshold Switch (OTS)) elements may have a smaller size than transistor type (such as MOSFET, metal oxide semiconductor field effect transistor) elements. The selector layer 160 may function as a diode type element with a diode junction formed within the selector layer 160. In fig. 1(b), the selector layer 160 is formed on the phase change material layer 130 formed of the above-mentioned materials and patterned to have the same size, thereby greatly reducing the space for the selector element in the phase change random access memory, which is considered to be a limiting factor in the scaling trend of the memory element. In some embodiments, the selector layer 160 provides current-voltage non-linearity to the phase change random access memory and reduces leakage current. In some embodiments, the selector layer 160 has a single or multi-layer structure. In some embodiments, selector layer 160 is made of a material that includes: SiO 2x、TiOx、AlOx、WOx、TixNyOz、HfOx、TaOx、NbOxOr the like, or a suitable combination thereof, wherein x, y and z are non-stoichiometric values. In some embodiments, the selector layer 160 is a solid electrolyte material containing one or more of the following: ge. Sb, S, Te or chalcogenides, such as N, P, S, Si and/or Te doped chalcogenides, such as N, P, S, Si and/or Te doped AsGeSe, i.e., AsGeSe (N, P, S, Si, Te), and N, P, S, Si and/or Te doped AsGeSeSi, i.e., AsGeSeSi (N, P, S, Si, Te). The thickness of selector layer 160 is in the range of about 0.5nm to about 50 nm. In some embodiments, the selector layer 160 is deposited by Chemical Vapor Deposition (CVD), pulsed laser deposition(PLD), sputtering, Atomic Layer Deposition (ALD), or any other thin film deposition method.
In some embodiments of the present disclosure, the intermediate layer 170 is formed on the via h and between the selector layer 160 and the metal layer 110. The intermediate layer 170 may be formed of carbon, titanium nitride, tungsten, and titanium tungsten with a thickness of about 1 to 50nm to prevent material diffusion and contamination of the phase change material layer 130. In some embodiments, the intermediate layer 170 is formed by any vapor deposition method, such as chemical vapor deposition, pulsed laser deposition, sputtering, atomic layer deposition, or any other thin film deposition method. In some embodiments, the intermediate layer 170 reduces the binding of species from the metal layer 110 to the selector layer 160 and the phase change material layer 130. In some embodiments of the present disclosure, the in-plane size of intermediate layer 170 is greater than the horizontal cross-sectional size of via h.
FIG. 2(a) is a top view of a phase change random access memory according to another embodiment of the present disclosure. The materials, configurations, dimensions, and/or processes illustrated in fig. 1(a) and 1(b) may be employed in the following embodiments, and detailed descriptions thereof may be omitted.
The phase change random access memory comprises a substrate 100, a bottom electrode 120 (wherein the bottom electrode can be a bit line) formed on the substrate 100, a phase change material layer 130 formed on the bottom electrode 120, and a metal layer 110 formed on the phase change material layer 130. In this embodiment, the phase change material layer 130 is smaller in size than the overlapping area between the bottom electrode 120 and the metal layer 110 serving as the top electrode. That is, the size of the phase change material layer 130 in the embodiment of fig. 2(a) is smaller than the size of the phase change material layer 130 in the embodiment of fig. 1 (a). The smaller phase change material layer 130 provides a reduced operating current that is supplied to the heater to heat the phase change material layer 130 for writing, thus significantly reducing the overall power consumption of a memory having more than one thousand phase change material layers 130.
FIG. 2(b) is a cross-sectional view of the phase change random access memory according to the embodiment shown in FIG. 2 (a). The phase change random access memory has an insulating layer 150 including a via h. In the through hole h, the heater 140 is formed. In some embodiments, the heater 140 is formed of a thin film material of TiN, TaN, or TiAlN having a thickness in a range from about 5 to about 15nm to provide joule heating to the phase change material layer 130. Further, during quenching (during a sudden cut-off of the current to the heater 140 to "freeze" the amorphous phase), the heater 140 may act as a heat sink. The heater 140 fills the via h in the insulating layer 150, which prevents heat transfer between the phase change random access memory cells to avoid thermal disturbances that can disable state retention or interrupt the read/write process. The phase change material layer 130 is formed in the through hole h and may contact the heater 140. In this way, the active region undergoing a phase transition in the phase change material layer 130 during writing to the memory cell is different from the active region having the mushroom shape in FIG. 1 (b). The selector layer 160 is formed on the phase change material layer 130, and the size of the selector layer 160 (width of about 25nm to about 100 nm) is greater than the size of the phase change material layer 130 in the via hole (width of about 10 nm). The metal layer 110 is formed on the selector layer 160 and serves as the top electrode for read/write operations of the phase change random access memory cell.
The phase change material layer 130 receives heat generated by the heater 140, and a region (referred to as an "active region") near an interface between the phase change material layer 130 and the heater 140 undergoes a phase transition from a crystalline phase to an amorphous phase or vice versa, depending on the amount and duration of heat generated when current is applied to the heater 140. In the embodiment of fig. 2(b), the active region has an elliptical shape (fig. 2(b)), while the region outside the active region does not undergo phase transition, and may serve as a thermal insulation layer to preserve heat inside the active region. The smaller the active region, the less heat and therefore the less current required to write to the phase change random access memory cell.
A selector layer 160 is formed on the phase change material layer 130, and a metal layer 110 is formed on the selector layer 160. In fig. 2(b), the selector layer 160 is formed on the phase change material layer 130 formed of the above-described materials to have a larger size than the phase change material layer 130, thereby greatly enhancing controllability and selectivity of the phase change material layer 130. In some embodiments, the selector layer 160 provides current and voltage non-linearities to the phase change random access memory and this reduces leakage current. The selector layer 160 has the above structure. In some embodiments, the selector layer 160 is made of the materials mentioned in the description of FIG. 1(b) above. The thickness of selector layer 160 ranges from about 0.5nm to about 50 nm. In some embodiments, the selector layer 160 is formed by chemical vapor deposition, pulsed laser deposition, sputtering, atomic layer deposition, or any other thin film deposition method.
In some embodiments, similar to fig. 1(a) and 1(b), an intermediate layer 170 is formed over the via h, and between the selector layer 160 and the metal layer 110.
FIG. 3(a) is a top view of a phase change random access memory according to another embodiment of the present disclosure. Materials, configurations, dimensions, and/or processes illustrated in fig. 1(a) and 2(b) may be employed in the following embodiments, and detailed explanations thereof may be omitted.
The phase change random access memory comprises a substrate 100, a bottom electrode 120 (wherein the bottom electrode can be a bit line) formed on the substrate 100, a phase change material layer 130 formed on the bottom electrode 120, and a metal layer 110 formed on the phase change material layer 130. In this embodiment, the phase change material layer 130 is smaller in size than the overlapping area between the bottom electrode 120 and the metal layer 110 serving as the top electrode. That is, the size of the phase change material layer 130 in the embodiment of fig. 3(a) is smaller than the size of the phase change material layer 130 in the embodiment of fig. 1 (a). The smaller phase change material layer 130 provides a reduced operating current that is supplied to the heater to heat the phase change material layer 130 for writing, thus significantly reducing the overall power consumption of a memory having more than one thousand phase change material layers 130.
Although the top view is the same as that shown in fig. 2(a), the element structure is different from that of fig. 2 (b). The phase change random access memory has an insulating layer 150 including a via h. In the through hole h, the heater 140 is formed. In some embodiments, the heater 140 is formed of a thin film material of TiN, TaN, or TiAlN having a thickness in a range of about 5 to about 15nm to provide joule heating to the phase change material layer 130. Further, during quenching (during a sudden cut-off of the current to the heater 140 to "freeze" the amorphous phase), the heater 140 may act as a heat sink. The heater 140 fills the via h provided in the insulating layer 150, which prevents heat transfer between the phase change random access memory cells to avoid thermal disturbances that can disable state retention or interrupt the read/write process.
In addition, as shown in the cross-sectional view of fig. 3(b), the selector layer 160 is formed in the via hole h, thereby greatly reducing the space occupied by the selector element in the phase change random access memory cell. The metal layer 110 is formed on the selector layer 160 and serves as the top electrode for read/write operations of the phase change random access memory cell.
A selector layer 160 is formed on the phase change material layer 130, and a metal layer 110 is formed on the selector layer 160. In fig. 3(b), the selector layer 160 is patterned on the phase change material layer 130 formed of the above-mentioned materials to have the same size, thereby greatly reducing the space for the selector element in the phase change random access memory, which is considered to be a limiting factor in the scaling trend of the memory element. In some embodiments, the selector layer 160 provides current and voltage non-linearities to the phase change random access memory and reduces leakage current. The selector layer 160 has the above structure. In some embodiments, the selector layer 160 is made of the materials mentioned in the description of FIG. 1(b) above. The thickness of selector layer 160 ranges from about 0.5nm to about 50 nm. In some embodiments, the selector layer 160 is formed by chemical vapor deposition, pulsed laser deposition, sputtering, atomic layer deposition, or any other thin film deposition method.
In some embodiments, similar to fig. 1(b) and 2(b), an intermediate layer 170 is formed between the selector layer 160 and the metal layer 110.
In some embodiments, stacked phase change random access memory structures significantly increase memory cell density and capacity. Fig. 4, 5(a), 5(b), and 6(a) to 6(c) illustrate various embodiments having a stacked three-dimensional (3D) structure. The materials, configurations, dimensions, and/or processes illustrated in fig. 1(a) to 3(b) may be employed in the following embodiments, and detailed descriptions thereof may be omitted.
FIG. 4 is a cross-sectional view of a stacked structure of a phase change random access memory including a bottom electrode 120 and a top electrode 120'. Insulating layers 150, 150', and 150 "are disposed between the bottom electrode 120 and the top electrode 120'. In some embodiments, the insulating layers 150, 150', and 150 ″ are formed of the same materials as described above with respect to fig. 1(b), 2(b), and 3 (b). The insulating layers 150, 150', and 150 ″ disposed on the patterned bottom electrode 120 are electrical and thermal insulators, and in some embodiments, each has a thickness in the range of about 5 to about 350 nm. Furthermore, in some embodiments, the insulating layers 150' and 150 "are formed as one layer in a single operation. The insulating layers 150, 150', and 150 ″ together with the top and bottom electrodes 120', 120 'enclose the first and second heaters 140 and 140', the first and second phase change material layers 130 and 130', the first and second selector layers 160 and 160', and the metal layer 110. The first and second heaters 140 and 140' are formed in the first and second through holes h and h ', respectively, and the other components occupy a large space provided in the insulating layer 150 '. Each of the vias h and h ' is formed between the first phase change material layer 130 and the top electrode 120' or between the second phase change material layer 130' and the bottom electrode 120.
In some embodiments of the present disclosure, the intermediate layer 170 is formed on the via h and between the selector layer 160 and the metal layer 110.
The embodiment shown in fig. 4 has a symmetrical structure in which the element parts are arranged with respect to the metal layer 110 and the intermediate layer 170. Each of the first phase change material layer 130 and the second phase change material layer 130' may be independently operated, and in this device structure, only three electrodes (e.g., the bottom electrode 120, the top electrode 120', and the metal layer 110) are required to operate the two phase change material layers 130 and 130', instead of four electrodes. In this way, the electrode is eliminated and the element thickness is reduced, and the element structure and process are simplified by reducing the manufacturing cost and simplifying the manufacturing operation. Furthermore, since the entire element is enclosed by the insulating layers 150, 150', and 150 ″, thermal and electrical disturbances (such as leakage currents) are advantageously reduced. Furthermore, due to the higher thermal insulation properties, the current used to write the memory cell is reduced in some embodiments, since the temperature of the phase transition within this highly insulating system can be achieved by a lower current. Depending on the selection of heater materials for heaters 140 and 140', in some embodiments, the efficiency of the entire stacked element may be substantially increased.
The embodiment in FIG. 4 stacks two elements of the embodiment of FIG. 1(a) along a vertical direction to form a stacked element; however, as appreciated by one of ordinary skill in the art, other possibilities are included in the present disclosure. For example, in some embodiments, the lower half of the device is formed by the structure of the embodiment in fig. 1(a), and the upper half of the device is formed by the structure of the embodiment in fig. 2(b), thereby forming an asymmetric 3D structure for phase change random access memory.
Fig. 5(a) illustrates a stacked element having a symmetrical stacked structure with respect to the metal layer 110. In some embodiments, the stacked element includes phase change material layers 130 and 130', the phase change material layers 130 and 130' being located at opposite sides of the metal layer 110, formed in the vias h and h ', and contacting the heaters 140 and 140'. In this way, the active region that undergoes a phase transition during writing to the memory cell is different from the active region having the mushroom shape in fig. 1(a) and 4. The smaller phase change material layers 130 and 130' significantly reduce the operating current and, in some embodiments, reduce the overall power consumption of a memory having more than one thousand phase change material layers. First and second selector layers 160 and 160 'are formed on the respective first and second phase change material layers 130 and 130'. The first and second selector layers 160 and 160 'are larger than the respective first and second phase change material layers 130 and 130'. In some embodiments, the second selector layer 160' is formed of the same material as the selector layer 160. In some embodiments, the second selector layer 160' is formed from a material from the group of materials described above from which the selector layer 160 is made, this material being different from the selector layer 160. In some embodiments, selector layer 160' has the same layered structure as selector layer 160. In some embodiments, selector layer 160 'has a different layered structure than selector layer 160, such as, but not limited to, selector layer 160' having a single layer structure and selector layer 160 having a multi-layer structure. In some embodiments of the present disclosure, the intermediate layer 170 is formed on the via h and between the selector layer 160 and the metal layer 110.
Fig. 5(b) illustrates an alternative embodiment to the embodiment shown in fig. 5 (a). Fig. 5(b) illustrates an asymmetric structure with respect to the metal layer 110, and fig. 5(a) illustrates a symmetric structure. In fig. 5(b), a second phase change material layer 130' is formed on the second heater 140' to be spaced apart from the second selector layer 160 '. In this embodiment, the second phase change material layer 130 'receives heat generated from the top surface of the second heater 140'. The arrangement of second phase change material layer 130 'on second heater 140' may enhance the overall efficiency of the element if heat transfer favors the upward direction. In this way, depending on the direction of heat transfer within the memory element, the arrangement of the phase change material layer relative to the heater can be tailored to meet different requirements for optimal efficiency. In some embodiments of the present disclosure, the intermediate layer 170 is formed on the via h and between the selector layer 160 and the metal layer 110.
Fig. 6(a), 6(b), and 6(c) illustrate embodiments with additional components, i.e., an intermediate layer 170'. Fig. 6(a) illustrates that in some embodiments of the present disclosure, an intermediate layer 170 is formed between the phase change material layer 130 and the metal layer 110 on the via hole h. In some embodiments of the present disclosure, an intermediate layer 170 is formed between the selector layer 160 and the metal layer 110.
Fig. 6(a) illustrates that in some embodiments of the present disclosure, a second phase change material layer 130' is formed between a second heater 140' and a second selector layer 160 '. Fig. 6(b) illustrates that in some embodiments of the present disclosure, a second phase change material layer 130 'is formed on the second heater 140' and between the second heater 140 'and the top electrode 120'. In some embodiments, an additional intermediate layer 170 'is formed on the second phase change material layer 130'. Fig. 6(c) illustrates that, in some embodiments of the present disclosure, an additional intermediate layer 170 'is formed on the second selector layer 160', a second phase change material layer 130 'is formed on the additional intermediate layer 170', and a second heater 140 'is formed on the second phase change material layer 130'. Depending on the direction of heat transfer, FIGS. 6(a) through 6(c) enhance the overall efficiency of the phase change random access memory device.
In fig. 6(a), 6(b), and 6(c), the intermediate layers 170 and 170' are formed of carbon, titanium nitride, tungsten, and titanium tungsten having a thickness of about 1 to 50 nm.
Fig. 7(a) to 7(f), fig. 8(a) to 8(i), fig. 9(a) to 9(h), and fig. 10(a) to 10(g) illustrate respective manufacturing operations for fabricating the phase change random access memory according to the above embodiment. It should be understood that additional operations may be provided before, during, and after the processes shown by fig. 7(a) -7 (f), 8(a) -8 (i), 9(a) -9 (h), and 10(a) -10 (g), and that some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations/processes is interchangeable. The materials, configurations, dimensions, and/or processes illustrated in fig. 1(a) to 6(c) may be employed in the following embodiments, and detailed descriptions thereof may be omitted.
Fig. 7(a) illustrates an operation of forming the bottom electrode 120 on the substrate 100. In some embodiments, the substrate 100 is any substrate that may be used for electronic memory elements, including single crystal semiconductor materials such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In certain embodiments, the substrate 100 is made of crystalline Si. In some embodiments, the bottom electrode 120 is formed by evaporation (evaporation) or any vapor deposition method, such as chemical vapor deposition, pulsed laser deposition, sputtering, atomic layer deposition, or any other thin film deposition method. The bottom electrode 120 may be formed by patterning a layer formed using a mask and an etching process, such as UV photolithography. To enhance the insulating properties between the phase change random access memory devices or cells, an insulating layer (not shown), such as silicon oxide, is formed on the substrate 100 by oxidation or any thin film deposition method prior to forming the bottom electrode 120 on the substrate 100.
FIG. 7(b) illustrates on the bottom electrode 120An operation of forming the insulating layer 150. The material of the insulating layer 150 is selected from silicon oxide (SiO)2) Silicon nitride (Si)3N4) Silicon oxynitride (SiON), SiOCN, SiCN, Al2O3Fluorine doped silicate glass (FSG), low-k dielectric materials, and other suitable dielectric materials for use in the manufacture of semiconductor devices. In some embodiments, for example, the insulating layer 150 is formed by: chemical vapor deposition such as Low Pressure Chemical Vapor Deposition (LPCVD), plasma chemical vapor deposition (plasma-CVD), or flowable chemical vapor deposition (flowableCVD); pulsed Laser Deposition (PLD); sputtering; atomic Layer Deposition (ALD); or any other thin film deposition method.
Fig. 7(c) illustrates an operation of forming a patterned photoresist layer 200 on the insulating layer 150. Fig. 7(d) illustrates the operation of etching the insulating layer 150 using anisotropic etching, wet etching, and/or dry etching. The etching forms a via hole h having a width of about 10nm in the insulating layer 150, thereby exposing the bottom electrode layer 120.
Fig. 7(e) illustrates an operation of forming the heater 140 in the through hole h. In some embodiments, the heater 140 is formed by depositing a metal alloy layer on the insulating layer 150, followed by Chemical Mechanical Polishing (CMP), such that the top surface of the heater 140 is coplanar with the top surface of the insulating layer 150. The heater 140 formed in fig. 7(e) is further etched to reduce the thickness in the via hole h, i.e., the embodiments formed in fig. 7(f) and 7 (g).
In some embodiments, the embodiment of FIG. 7(e) continues with the process of FIG. 8(a) to form the stacked phase change random access memory device of FIG. 8 (i). Fig. 8(a) illustrates the embodiment depicted in fig. 7 (e). Fig. 8(b) illustrates the operation of forming the patterned phase change material layer 130 on the heater 140 by one or more thin film deposition and patterning methods. Fig. 8(c) illustrates the operation of forming the patterned selector layer 160 by one or more thin film deposition and patterning methods. Fig. 8(d) illustrates the operations of forming the intermediate layer 170 on the selector layer 160 and forming the metal layer 110 on the selector layer 160 by a thin film deposition and patterning method. Alternatively, in other embodiments, layers 130, 160, 170, and 110 are formed together by forming multiple layers in a single step and then patterning them. In some embodiments of the present disclosure, the intermediate layer 170 is formed on the via h and between the selector layer 160 and the metal layer 110. The intermediate layer 170 may be formed of carbon, titanium nitride, tungsten, and titanium tungsten with a thickness of about 1 to 50nm, and serves to prevent diffusion of materials and contamination of the phase change material layer 130. In some embodiments, the intermediate layer 170 is formed by any vapor deposition method, such as chemical vapor deposition, pulsed laser deposition, sputtering, atomic layer deposition, or any other thin film deposition method. In some embodiments, the intermediate layer 170 reduces incorporation of species from the metal layer 110 into the selector layer 160 and the phase change material layer 130. In some embodiments of the present disclosure, the in-plane dimension of the intermediate layer 170 is greater than the horizontal cross-sectional dimension of the via h.
Fig. 8(e) illustrates an operation of forming and patterning the second selector layer 160 and the second phase change material layer 130' on the metal layer 110. In some embodiments, layers 130, 160, 170, 110, 160', and 130' are patterned by more than one etch process. Fig. 8(f) illustrates an operation of forming the insulating layer 150'. Fig. 8(g) illustrates an operation of forming the second via hole h' by forming a photoresist layer and etching the insulating layer 150 ″. In some embodiments, rather than forming two layers in two separate operations, the insulating layers 150' and 150 "are formed as one layer in one operation. The via hole h' is then formed by etching an insulating layer. In some embodiments, insulating layers 150, 150', and 150 ″ are formed of the same materials described above. Fig. 8(h) illustrates an operation of forming the second heater 140'. Fig. 8(i) illustrates an operation of forming the top electrode 120'. In this manner, in the element formed in fig. 8(i), the insulating layers 150, 150', and 150 "together with the top and bottom electrodes 120', 120" enclose the other components in this element, providing excellent electrical and thermal insulating properties, and reducing thermal and crosstalk perturbations.
In some embodiments, the embodiment in fig. 7(f) continues in the process in fig. 9(a) to form the embodiment in fig. 9(h), and in other embodiments, the embodiment in fig. 7(g) continues in the process in fig. 10(a) to form the embodiment in fig. 10 (g). Fig. 9(a) illustrates the embodiment depicted in fig. 7 (f). Fig. 9(b) illustrates an operation of forming the phase change material layer 130 in the via hole h and on the heater 140 by one or more thin film deposition methods. Fig. 9(c) illustrates the formation of the patterned selector layer 160, intermediate layer 170, and metal layer 110 by one or more thin film deposition and patterning methods. In some embodiments of the present disclosure, the intermediate layer 170 is formed on the via h and between the selector layer 160 and the metal layer 110. The intermediate layer 170 may be formed of carbon, titanium nitride, tungsten, and titanium tungsten with a thickness of about 1 to 50nm, and serves to prevent diffusion of materials and contamination of the phase change material layer 130. In some embodiments, the intermediate layer 170 is formed by any vapor deposition method, such as chemical vapor deposition, pulsed laser deposition, sputtering, atomic layer deposition, or any other thin film deposition method. In some embodiments, the intermediate layer 170 reduces incorporation of species from the metal layer 110 into the selector layer 160 and the phase change material layer 130. In some embodiments of the present disclosure, the in-plane dimension of the intermediate layer 170 is greater than the horizontal cross-sectional dimension of the via h.
Fig. 9(d) illustrates the operation of forming the second selector layer 160' by one or more thin film deposition and patterning methods. Alternatively, in other embodiments, the three layers 160, 110, and 160' are formed by a thin film deposition method and then patterned together in a patterning method. Fig. 9(e) illustrates an operation of forming the insulating layer 150'. Fig. 9(f) illustrates an operation of forming the second via hole h'. In some embodiments, the second via hole h' is formed by photolithography and etching operations. In some embodiments, insulating layers 150, 150', and 150 ″ are formed of the same materials described above. Furthermore, in some embodiments, the insulating layers 150' and 150 "are formed as one layer in one operation. Fig. 9(g) illustrates an operation of forming the second heater 140 'in the second through hole h'. Fig. 9(h) illustrates an operation of forming the top electrode 120'. In this manner, in the element formed in fig. 9(h), the insulating layers 150, 150', and 150 "along with the top and bottom electrodes 120', 120" enclose the other components in this element, thereby providing excellent electrical and thermal insulating properties and reducing thermal and crosstalk perturbations.
Fig. 10(a) illustrates the embodiment depicted in fig. 7 (g). Fig. 10(b) illustrates an operation of forming the first phase change material layer 130 and the first selector layer 160 in the via hole h and on the heater 140 by one or more thin film deposition and patterning methods. Fig. 10(c) illustrates the operation of forming the patterned metal layer 110, the intermediate layer 170, and the patterned second selector layer 160' by one or more thin film deposition and patterning methods. Alternatively, in other embodiments, layers 110, 170, and 160' are formed and then patterned together using a patterning method. In some embodiments of the present disclosure, the intermediate layer 170 is formed on the via h and between the selector layer 160 and the metal layer 110. The intermediate layer 170 may be formed of carbon, titanium nitride, tungsten, and titanium tungsten with a thickness of about 1 to 50nm, and serves to prevent diffusion of materials and contamination of the phase change material layer 130. In some embodiments, the intermediate layer 170 is formed by any vapor deposition method, such as chemical vapor deposition, pulsed laser deposition, sputtering, atomic layer deposition, or any other thin film deposition method. In some embodiments, the intermediate layer 170 reduces incorporation of species from the metal layer 110 into the selector layer 160 and the phase change material layer 130. In some embodiments of the present disclosure, the in-plane dimension of the intermediate layer 170 is greater than the horizontal cross-sectional dimension of the via h.
Fig. 10(d) illustrates an operation of forming the insulating layer 150'. Fig. 10(e) illustrates another operation of forming a second via h 'in the insulating layer 150' using a photolithography and etching operation in some embodiments. In some embodiments, the insulating layers 150' and 150 "are formed as one layer in a single operation. Fig. 10(f) illustrates an operation of forming the second heater 140 'in the second through hole h'. Fig. 10(g) illustrates an operation of forming the top electrode 120'. In some embodiments, insulating layers 150, 150', and 150 ″ are formed of the same materials described above. In this way, in the element in fig. 10(g), the insulating layers 150, 150', and 150 "together with the top and bottom electrodes 120', 120" enclose the other components in this element, thereby providing excellent electrical and thermal insulating properties and reducing thermal and crosstalk perturbations.
FIG. 11 illustrates a flow chart of a method of forming an embodiment of the present disclosure. The method includes operation S111: forming a bottom electrode on the substrate, S112: forming an insulating layer on the bottom electrode, S113: forming a via hole in the insulating layer, S114: forming a heater in the through hole, S115: forming a phase change material layer on the heater, S116: forming a selector layer on the phase change material layer, S117: forming an intermediate layer on the selector layer, and S118: a metal layer is formed on the intermediate layer.
In particular, operation S115 may include forming a phase change material layer on the insulating layer and on the heater, or forming a phase change material layer in the via hole of the insulating layer and on the heater. In addition, operation S116 may include forming a selector layer on the insulating layer and on the heater, or forming a selector layer in the via hole of the insulating layer and on the heater. The processing conditions of the etching operation include details of embodiments disclosed herein. Materials, configurations, dimensions, and/or processes illustrated in fig. 1(a) to 11 may be employed in the following embodiments, and detailed descriptions thereof may be omitted.
Fig. 12(a), 12(b), 12(c), 12(d), 12(e), and 12(f) illustrate successive manufacturing operations for forming a heater in a via according to embodiments of the present disclosure. In some embodiments, fig. 12(a) corresponds to fig. 7(d), and fig. 12(f) corresponds to fig. 7(e), and fig. 12(b), 12(c), 12(d), and 12(e) illustrate successive manufacturing operations for forming the heater 140 in the through-hole h. As shown in fig. 12(b), 12(c), 12(d), and 12(e), the material (e.g., metal alloy) forming the heater 140 in the via hole h may be deposited in more than one step (e.g., in four steps). In each step, a layer of material may be deposited in the via h, for example, at the bottom and sides of the via h, and may also be deposited on top of the insulating layer 150. Fig. 12(b), 12(c), 12(d), and 12(e) correspond to depositing one, two, three, and four layers, respectively. In some examples, after depositing the four layers, the via hole h may be filled and the heater 140 may be formed. In some embodiments, in each step, a deposition process (e.g., atomic layer deposition) may be used to deposit 40 angstroms of material, and the sequential deposition of multiple layers may continue until via h is filled. In some embodiments, after filling the via hole h, chemical mechanical polishing may be applied on fig. 12(e) so that the top surface of the heater 140 becomes coplanar with the top surface of the insulating layer 150, as shown in fig. 12 (f).
Fig. 13(a), 13(b), 13(c), and 13(d) illustrate successive fabrication operations for depositing a two-dimensional layer on top of a heater in forming a phase change random access memory according to an embodiment of the present disclosure. Materials, configurations, dimensions, and/or processes illustrated in fig. 1(a) to 12(f) may be employed in the following embodiments, and detailed descriptions thereof may be omitted.
In some embodiments, fig. 13(a) is consistent with fig. 8(d), and fig. 13(b) and 13(c) illustrate successive fabrication operations for forming a two-dimensional layer 190 on top of the heater 140. The two-dimensional layer 190 of fig. 13(b) may be made of, for example, graphene or molybdenum disulfide (MoS)2) Having a thickness of about 0nm to about 2nm, in some embodiments, a two-dimensional layer 190 may be deposited on top of the heater 140 and on top of the insulating layer 150. In other embodiments, the thickness of the two-dimensional layer 190 is in a range from about 0.5nm to about 1 nm. Subsequently, as shown in fig. 13(c), the two-dimensional layer 190 may be patterned to have top surface dimensions that match the phase change material layer 130, which will be deposited on top of the two-dimensional layer 190. As shown in fig. 13(d), other layers, which may include the selector layer 160, the intermediate layer 170, and the metal layer 110, may be deposited on top of the phase change material layer 130. In some embodiments, after the two-dimensional layer 190 is formed as shown in fig. 13(b), the layers for the phase change material layer 130, the selector layer 160, the intermediate layer 170, and the metal layer 110 are sequentially formed, and then the stacked layers are patterned by using one or more lithography and etching operations to form the structure shown in fig. 13 (d). In some embodiments, the operations performed in fig. 13(b) and 13(c) may be added between fig. 8(a) and 8 (b).
Fig. 14(a), 14(b) and 14(c) illustrate the structure of the top and bottom electrodes coupled to the heater. Fig. 14(a) illustrates a heater D2, consistent with heater 140 of fig. 1(b), coupled between top electrode D1 and bottom electrode D3. The top electrode D1 and the bottom electrode D3 correspond to the metal layer 11 and the bottom electrode 120 of fig. 1(b), respectively. Fig. 14(b) illustrates a diagram of elements included in the top electrode D1, the heater D2, and the bottom electrode D3 along the direction D shown in fig. 14 (a). As shown, the top electrode D1 includes Ti and N, and thus may include titanium nitride (TiN). The bottom electrode D3 may comprise copper (Cu) and the heater D2 may comprise Ta, Si, and N, and thus may comprise titanium nitride (TiN) in a silicon substrate. FIG. 14(c) illustrates the structure of a memory cell having a top electrode D1, a bottom electrode D3, and a heater D2, the memory cell also including a phase change material layer 130 between the top electrode D1 and the heater D2, and the memory cell structure deposited on the substrate 100. In some embodiments, the memory cell structure of FIG. 14(c) is used in Phase Change Random Access Memory (PCRAM), variable resistive memory (ReRAM), Magnetic Random Access Memory (MRAM), and the like. In some embodiments, a two-dimensional layer, such as two-dimensional layer 190 of fig. 13(D), is included between heater D2 and phase change material layer 130. In some embodiments, the selector layer 160 and/or the intermediate layer 170 may be included between the phase change material layer 130 and the top electrode D1. In some examples, a material having a higher resistivity than TiN (such as amorphous carbon) may be used as the heater 140. The resistivity of amorphous carbon 3.5E-3(ohm-cm) is greater than that of TiN 3.0E-4(ohm-cm), although the resistivity of amorphous carbon is less than that of TaN (7.0E-2 (ohm-cm)). The amorphous carbon has a thermal conductivity of 1.1(W/m-k), which is less than the thermal conductivity of 20(W/m-k) of TiN, and also less than the thermal conductivity of 3(W/m-k) of TaN.
Embodiments according to the present disclosure include a memory device having a substrate, a bottom electrode disposed on the substrate, and an insulating layer disposed on the bottom electrode. The insulating layer has a via defined therein. The heater is disposed in the through hole. The phase change material layer is disposed on the heater. The selector layer is disposed on the phase change material layer, the intermediate layer is disposed on the via, and the metal layer is disposed on the selector layer. In some embodiments, the intermediate layer is wider than the diameter of the via. In some embodiments, the metal layer is formed wider than the phase change material layer. In some embodiments, the phase change material layer is disposed in the via. In some embodiments, the selector layer is disposed in the via. In some embodiments, the intermediate layer contacts the metal layer. In some embodiments, the intermediate layer is formed of one of carbon and tungsten. In some embodiments, a metal layer is used as the top electrode.
Another embodiment according to the present disclosure includes a memory device having a substrate, a bottom electrode disposed on the substrate, and a first heater disposed on the bottom electrode. The first phase change material layer is disposed on the first heater. The first selector layer is disposed on the first phase change material layer. An intermediate layer (170) is disposed on the first selector layer (160). A metal layer is disposed on the first selector layer. The second selector layer is disposed on the metal layer. A second heater and a second phase change material layer are disposed on the second selector layer. The top electrode is disposed on the second heater and the second phase change material layer, and an insulating layer between the bottom electrode and the top electrode encloses the first and second heaters, the first and second selector layers, the first and second phase change material layers, and the metal layer together with the bottom electrode and the top electrode. In some embodiments, the metal layer is formed wider than the first phase change material layer. In some embodiments, a second heater is disposed on the second phase change material layer. In some embodiments, a second phase change material layer is disposed on the second heater. In some embodiments, the intermediate layer is wider than the first and second heaters. In some embodiments, the intermediate layer contacts the metal layer. In some embodiments, the intermediate layer is formed of one of carbon and tungsten.
Another embodiment according to the present disclosure is a method of fabricating a memory device. The method includes forming a bottom electrode on a substrate, forming an insulating layer on the bottom electrode, and forming a via in the insulating layer. A heater is formed in the through hole. A phase change material layer is formed on the heater. A selector layer is formed on the phase change material layer. An intermediate layer (170) is formed on the selector layer (160), and a metal layer is formed on the selector layer. In some embodiments, the intermediate layer (170) contacts the metal layer (110). In some embodiments, the phase change material layer is formed in the via. In some embodiments, the intermediate layer is formed of at least one of carbon and tungsten.
The foregoing outlines features of several embodiments or examples so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that the present disclosure may be readily utilized as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
