Four-input-four-output multifunctional encoder circuit based on memristor
阅读说明：本技术 一种基于忆阻器的四输入-四输出多功能编码器电路 (Four-input-four-output multifunctional encoder circuit based on memristor ) 是由 孙军伟 陈志武 李盼龙 杨宇理 杨秦飞 梁恩豪 王延峰 王英聪 黄春 方洁 张勋 于 2019-09-26 设计创作，主要内容包括：本发明提出了一种基于忆阻器的四输入-四输出多功能编码器电路,包含以忆阻器为基础的14个与门逻辑功能电路、5个或门逻辑功能电路以及9个非门逻辑功能电路构建四条电路通道；具有两种编码器功能,利用忆阻器、运算放大器、参考电压等元件,实现了与、或、非、异或等逻辑运算,通过四条通道电路得到四路信号,电路对输入信号进行编码,经过处理输出一个编码结果,所输出的编码结果表示对输入信号所作出的编码操作；所输出的结果是基于忆阻器的编码器组合逻辑电路对输入信号进行编码,能够实现特定编码功能的基于忆阻器的编码器电路具有十分重要的现实意义。本发明的电路集成度更高、运算速度更高、功耗更低,极大的提升了编码器的性能。(The invention provides a four-input-four-output multifunctional encoder circuit based on a memristor, which comprises 14 AND gate logic function circuits, 5 OR gate logic function circuits and 9 NOT gate logic function circuits based on the memristor, wherein four circuit channels are constructed; the four-channel circuit has two encoder functions, logical operations such as AND, OR, NOT, XOR and the like are realized by utilizing elements such as a memristor, an operational amplifier, a reference voltage and the like, four channels of signals are obtained through four channels of circuits, the circuits encode input signals, an encoding result is output after processing, and the output encoding result represents encoding operation made on the input signals; the output result is that the encoder combinational logic circuit based on the memristor encodes the input signal, and the encoder circuit based on the memristor and capable of realizing a specific encoding function has very important practical significance. The circuit of the invention has higher integration level, higher operation speed and lower power consumption, and greatly improves the performance of the encoder.)
1. A four-input-four-output multifunctional encoder circuit based on a memristor is characterized by comprising four input ports I3、I2、I1、I0And four output ports O3、O2、O1、O0Input port I3、I2、I1And I0Through first channel circuit based on memristor and output port O3Connected, input port I3、I2、I1And I0Through a second channel circuit based on a memristor and an output port O2The second channel circuit is connected with the output port O through a third channel circuit based on the memristor1Connected, input port I0Through a fourth channel circuit based on memristor and an output port O0Are connected.
2. The memristor-based four-input-four-output multifunctional encoder circuit according to claim 1, wherein the outputPort O3、O2And O1Output input port I in binary form3、I2、I1And I0The number of logic '1's in the formed input signal, input port I3、I2、I1And I0The composed input signal odd-even number passes through the output port O0Output, and when the input signal is even number, the output port O0Output logic '1', whereas when the input signal is odd, the output port O0A logic "0" is output.
3. The memristor-based four-input-four-output multifunctional encoder circuit according to claim 1, wherein the four output ports O3、O2、O1、O0The logical expressions of (a) are respectively:
O3＝I3·I2·I1·I0，
4. the memristor-based four-input-four-output multifunctional encoder circuit according to any one of claims 1 to 3, wherein the first channel circuit is a memristor-based four-input logic AND gate circuit with an input port I3、I2、I1And I0Are all connected with a four-input logic AND gate circuit which is connected with an output port O3Connecting; the second channel circuit comprises a first logic AND gate circuit, a second logic AND gate circuit and a third logic AND gate circuit based on memristorsThe gate circuit, the first logic exclusive-OR circuit, the second logic exclusive-OR circuit, the third logic exclusive-OR circuit and the logic OR gate circuit are arranged on the input port I3、I2Are all connected with a first logic AND gate circuit and have an input port I1And I0Are connected with a second logic AND gate circuit, a first logic AND gate circuit and a second logic AND gate circuit are connected with a first logic exclusive OR circuit, and an input port I3、I2Are all connected with a second logic exclusive-OR circuit and have an input port I1And I0Are all connected with a third logic exclusive-OR circuit, the second logic exclusive-OR circuit and the third logic exclusive-OR circuit are all connected with a third logic AND circuit, the output end of the third logic AND circuit and the output end of the first logic exclusive-OR circuit are all connected with a logic OR gate circuit, and the output end of the logic OR gate circuit is an output port O2(ii) a The third channel circuit comprises a fourth logic exclusive-OR circuit based on a memristor, the second logic exclusive-OR circuit is connected with the third logic exclusive-OR circuit, the third logic exclusive-OR circuit and the fourth logic exclusive-OR circuit are both connected with the fourth logic AND circuit, and the output end connected with the fourth logic AND circuit is an output port O1(ii) a The fourth channel circuit comprises a memristor-based logic NOT gate circuit with an input port I0The output end of the logic NOT gate circuit is an output port O4。
5. The memristor-based four-input-four-output multifunctional encoder circuit according to claim 4, wherein the four-input logic AND gate circuit comprises 3 memristor-based first, second and third AND gate circuits, and the input port I is3And an input port I2Connected with two input ends of the first AND circuit respectively, and input port I1And the output end of the first AND gate circuit is connected with the input end of the second AND gate circuit respectively, and the input port I0The output end of the second AND gate circuit is respectively connected with two input ends of a third AND gate circuit, and the output end of the third AND gate circuit is an output port O3(ii) a The first AND gate circuit comprises a memristor M43Memristor M42And operational amplifier OP24Input port I3And an input port I2Respectively and memristor M43Memristor M42Is connected with the negative pole of the memristor M43Memristor M42Is connected with an operational amplifier OP24Are connected to the non-inverting input terminal of an operational amplifier OP24Is connected with a reference voltage Vref1.07An operational amplifier OP24The output end of the first and-gate circuit is connected with a first and-gate circuit; the second AND gate circuit comprises a memristor M44Memristor M45And operational amplifier OP25Input port I1And operational amplifier OP24Respectively with memristor M45Memristor M44Is connected with the negative pole of the memristor M45Memristor M44Is connected with an operational amplifier OP25Are connected to the non-inverting input terminal of an operational amplifier OP25Is connected with a reference voltage Vref1.08An operational amplifier OP25The output end of the first and-gate circuit is connected with a first and-gate circuit; the third AND gate circuit comprises a memristor M47Memristor M46And operational amplifier OP26Input port I0And operational amplifier OP25Respectively with memristor M47Memristor M46Is connected with the negative pole of the memristor M46Memristor M47Is connected with an operational amplifier OP26Are connected to the non-inverting input terminal of an operational amplifier OP26Is connected with a reference voltage Vref1.09An operational amplifier OP26The output end of (2) is an output port O3。
6. The memristor-based four-input-four-output multifunctional encoder circuit according to claim 4 or 5, wherein the first logic AND gate circuit is a memristor-based fourth AND gate circuit, and the fourth AND gate circuit comprises a memristor M49Memristor M48And operational amplifier OP27Input port I3And an input port I2Respectively and memristor M49Memristor M48Is connected with the negative pole of the memristor M49Memristor M48Is connected with an operational amplifier OP27Are connected to the non-inverting input terminal of an operational amplifier OP27Is connected with a reference voltage Vref1.10An operational amplifier OP27The output end of the first logic exclusive or circuit is connected with the first logic exclusive or circuit; the second logic AND gate circuit is a fifth AND gate circuit based on a memristor, and the fifth AND gate circuit comprises a memristor M51Memristor M50And operational amplifier OP28Input port I1And an input port I0Respectively and memristor M51Memristor M50Is connected with the negative pole of the memristor M51Memristor M50Is connected with an operational amplifier OP28Are connected to the non-inverting input terminal of an operational amplifier OP28Is connected with a reference voltage Vref1.11An operational amplifier OP27Is connected to the first logic exclusive or circuit.
7. The memristor-based four-input-four-output multi-function encoder circuit of claim 6, the first logic exclusive-OR circuit comprises a first NOT gate circuit, a second NOT gate circuit, a sixth AND gate circuit, a seventh AND gate circuit and a first OR gate circuit which are based on a memristor, wherein the output ends of the fourth AND gate circuit and the fifth AND gate circuit are respectively connected with the first NOT gate circuit and the second NOT gate circuit; the first NOT gate circuit comprises a memristor M52And operational amplifier OP29Memristor M52Negative pole of (2) and operational amplifier OP27Is connected with the output end of the memristor M52Positive electrode of and operational amplifier OP29ToThe phase input terminals are connected, an operational amplifier OP29The non-inverting input end of the voltage regulator is connected with a reference voltage Vref3.06An operational amplifier OP29The output end of the first AND-gate circuit is connected with the input end of the sixth AND-gate circuit; the second NOT-gate circuit comprises a memristor M53And operational amplifier OP30Memristor M53Negative pole of (2) and operational amplifier OP28Is connected with the output end of the memristor M53Positive electrode of and operational amplifier OP30Are connected to the inverting input terminal of an operational amplifier OP30The non-inverting input end of the voltage regulator is connected with a reference voltage Vref3.07An operational amplifier OP30The output end of the first AND-gate circuit is connected with the input end of the seventh AND-gate circuit; the sixth AND gate circuit comprises a memristor M54Memristor M55And operational amplifier OP31An operational amplifier OP29And operational amplifier OP28Respectively with memristor M54Memristor M55Is connected with the negative pole of the memristor M54Memristor M55Is connected with an operational amplifier OP31Are connected to the non-inverting input terminal of an operational amplifier OP31Is connected with a reference voltage Vref1.12An operational amplifier OP31The output end of the first switch is connected with a first OR gate circuit; the seventh AND gate circuit comprises a memristor M56Memristor M57And operational amplifier OP32An operational amplifier OP27And operational amplifier OP30Respectively with memristor M56Memristor M57Is connected with the negative pole of the memristor M56Memristor M57Is connected with an operational amplifier OP32Are connected to the non-inverting input terminal of an operational amplifier OP32Is connected with a reference voltage Vref1.13An operational amplifier OP32The output end of the first switch is connected with a first OR gate circuit; the first OR gate comprises a memristor M58Memristor M59And operational amplifier OP33An operational amplifier OP31And operational amplifier OP32Respectively with memristor M58Memristor M59Is connected to the negative electrodeResistor M58Memristor M59Is connected with an operational amplifier OP33Are connected to the non-inverting input terminal of an operational amplifier OP33Is connected with a reference voltage Vref2.10An operational amplifier OP33The output end of the first logic AND circuit is connected with a third logic AND circuit; the second logic exclusive-OR circuit comprises a third NOT gate circuit, a fourth NOT gate circuit, an eighth AND gate circuit, a ninth AND gate circuit and a second OR gate circuit based on memristors, and an input port I3And an input port I2Is respectively connected with a third NOT gate circuit, a fourth NOT gate circuit, an output end and an input port I of the third NOT gate circuit2Connected with two input ends of the eighth AND gate circuit, the output end of the fourth NOT gate circuit and the input port I respectively3The output ends of the eighth AND gate circuit and the ninth AND gate circuit are respectively connected with two input ends of a second OR gate circuit, and the output end of the second OR gate circuit is connected with a third logic AND gate circuit; the third NOT gate circuit comprises a memristor M60And operational amplifier OP34Memristor M60Negative electrode and input port I3Connected, memristor M60Positive electrode of and operational amplifier OP34Are connected to the inverting input terminal of an operational amplifier OP34The non-inverting input end of the voltage regulator is connected with a reference voltage Vref3.08An operational amplifier OP34The output end of the first and-gate circuit is connected with the input end of the second and-gate circuit; the fourth NOT gate circuit comprises a memristor M61And operational amplifier OP35Memristor M61Negative electrode and input port I2Connected, memristor M61Positive electrode of and operational amplifier OP35Are connected to the inverting input terminal of an operational amplifier OP35The non-inverting input end of the voltage regulator is connected with a reference voltage Vref3.09An operational amplifier OP35The output end of the first and-gate circuit is connected with the input end of the ninth and-gate circuit; the eighth AND gate circuit comprises a memristor M62Memristor M63And operational amplifier OP36An operational amplifier OP34Output terminal and input port I2Respectively and memristor M62Memristor M63Is connected with the negative pole of the memristor M62Memristor M63Is connected with an operational amplifier OP36Are connected to the non-inverting input terminal of an operational amplifier OP36Is connected with a reference voltage Vref1.14An operational amplifier OP36The output end of the first or gate circuit is connected with a first or gate circuit; the ninth AND gate circuit comprises a memristor M64Memristor M65And operational amplifier OP37An operational amplifier OP35Output terminal and input port I3Respectively and memristor M65Memristor M64Is connected with the negative pole of the memristor M65Memristor M64Is connected with an operational amplifier OP37Are connected to the non-inverting input terminal of an operational amplifier OP37Is connected with a reference voltage Vref1.15An operational amplifier OP37The output end of the first or gate circuit is connected with a first or gate circuit; the second OR gate comprises a memristor M66Memristor M67And operational amplifier OP38An operational amplifier OP36And operational amplifier OP37Respectively with memristor M66Memristor M67Is connected with the negative pole of the memristor M66Memristor M67Is connected with an operational amplifier OP38Are connected to the non-inverting input terminal of an operational amplifier OP38Is connected with a reference voltage Vref2.11An operational amplifier OP38The output end of the first logic AND circuit is connected with a third logic AND circuit; the third logic exclusive-OR circuit comprises a fifth NOT gate circuit, a sixth NOT gate circuit, a tenth AND gate circuit, an eleventh AND gate circuit and a third OR gate circuit, and an input port I0And an input port I1Connected with the fifth NOT gate circuit and the sixth NOT gate circuit respectively, and having output terminal and input terminal I1Connected with two input ends of a tenth AND gate circuit, an output end of a sixth NOT gate circuit and an input port I respectively3The output ends of the tenth AND gate circuit and the eleventh AND gate circuit are respectively connected with two input ends of a third OR gate circuit, and the third AND gate circuitThe output end of the OR gate is connected with a third logic AND gate circuit; the fifth NOT gate circuit comprises a memristor M68And operational amplifier OP39Memristor M68Negative electrode and input port I0Connected, memristor M68Positive electrode of and operational amplifier OP39Are connected to the inverting input terminal of an operational amplifier OP39The non-inverting input end of the voltage regulator is connected with a reference voltage Vref3.10An operational amplifier OP39The output end of the first and-gate circuit is connected with the input end of the tenth and-gate circuit; the sixth NOT gate circuit comprises a memristor M69And operational amplifier OP40Memristor M69Negative electrode and input port I1Connected, memristor M69Positive electrode of and operational amplifier OP40Are connected to the inverting input terminal of an operational amplifier OP40The non-inverting input end of the voltage regulator is connected with a reference voltage Vref3.11An operational amplifier OP40The output end of the first and-gate circuit is connected with the input end of the eleventh and-gate circuit; the tenth AND gate circuit comprises a memristor M70Memristor M71And operational amplifier OP41An operational amplifier OP39Output terminal and input port I1Respectively and memristor M70Memristor M71Is connected with the negative pole of the memristor M70Memristor M71Is connected with an operational amplifier OP41Are connected to the non-inverting input terminal of an operational amplifier OP41Is connected with a reference voltage Vref1.16An operational amplifier OP41The output end of the first or gate circuit is connected with a third or gate circuit; the eleventh AND gate circuit comprises a memristor M72Memristor M73And operational amplifier OP42An operational amplifier OP40Output terminal and input port I0Respectively and memristor M73Memristor M72Is connected with the negative pole of the memristor M73Memristor M72Is connected with an operational amplifier OP42Are connected to the non-inverting input terminal of an operational amplifier OP42Is connected with a reference voltage Vref1.17An operational amplifier OP42The output end of the first or gate circuit is connected with a third or gate circuit; the third OR gate circuit comprises memoryResistor M74Memristor M75And operational amplifier OP43An operational amplifier OP41And operational amplifier OP42Respectively with memristor M74Memristor M75Is connected with the negative pole of the memristor M74Memristor M75Is connected with an operational amplifier OP43Are connected to the non-inverting input terminal of an operational amplifier OP43Is connected with a reference voltage Vref2.12An operational amplifier OP43The output end of the first logic AND circuit is connected with a third logic AND circuit; the third logic AND gate circuit is a twelfth AND gate circuit based on a memristor, and the twelfth AND gate circuit comprises a memristor M76Memristor M77And operational amplifier OP44An operational amplifier OP38And operational amplifier OP43Respectively with memristor M76Memristor M77Is connected with the negative pole of the memristor M76Memristor M77Is connected with an operational amplifier OP44Are connected to the non-inverting input terminal of an operational amplifier OP44Is connected with a reference voltage Vref1.18An operational amplifier OP44The output end of the voltage regulator is connected with a logic OR gate circuit; the logic OR gate circuit is a fourth OR gate circuit which comprises a memristor M78Memristor M79And operational amplifier OP45An operational amplifier OP33And operational amplifier OP44Respectively with memristor M78Memristor M79Is connected with the negative pole of the memristor M78Memristor M79Is connected with an operational amplifier OP45Are connected to the non-inverting input terminal of an operational amplifier OP45Is connected with a reference voltage Vref2.13An operational amplifier OP45Output port O of2。
8. The memristor-based four-input-four-output multifunctional encoder circuit according to claim 4 or 7, wherein the fourth logical exclusive-or circuit comprises a seventh NOT gateThe output end of the second logic exclusive-OR circuit is an operational amplifier OP38And the output of the third logic exclusive-or circuit, i.e. the operational amplifier OP43Respectively connected to the seventh not-gate circuit and the eighth not-gate circuit, the output terminal of the seventh not-gate circuit and the operational amplifier OP43Respectively connected to two input terminals of a thirteenth AND circuit, an output terminal of an eighth NOT circuit and an operational amplifier OP38The output ends of the thirteenth and gate circuit and the fourteenth and gate circuit are respectively connected with two input ends of a fifth or gate circuit, and the output end of the fifth or gate circuit is an output port O1(ii) a The seventh NOT gate circuit comprises a memristor M80And operational amplifier OP46Memristor M80Negative pole of (2) and operational amplifier OP38Is connected with the output end of the memristor M80Positive electrode of and operational amplifier OP46Are connected to the inverting input terminal of an operational amplifier OP39The non-inverting input end of the voltage regulator is connected with a reference voltage Vref3.12An operational amplifier OP46The output end of the first and-gate circuit is connected with the input end of the thirteenth and-gate circuit; the eighth NOT gate circuit comprises a memristor M81And operational amplifier OP47Memristor M81Negative pole of (2) and operational amplifier OP43Is connected with the output end of the memristor M81Positive electrode of and operational amplifier OP47Are connected to the inverting input terminal of an operational amplifier OP47The non-inverting input end of the voltage regulator is connected with a reference voltage Vref3.13An operational amplifier OP47The output end of the first and-gate circuit is connected with the input end of the fourteenth and-gate circuit; the thirteenth AND gate circuit comprises a memristor M82Memristor M83And operational amplifier OP48An operational amplifier OP46And operational amplifier OP43Respectively with memristor M82Memristor M83Is connected with the negative pole of the memristor M82Memristor M83Is connected with an operational amplifier OP48Are connected with the non-inverting input terminal ofOperational amplifier OP48Is connected with a reference voltage Vref1.19An operational amplifier OP48The output end of the first switch is connected with a fifth OR gate circuit; the fourteenth AND gate circuit comprises a memristor M84Memristor M85And operational amplifier OP49An operational amplifier OP47And operational amplifier OP38Respectively with memristor M85Memristor M84Is connected with the negative pole of the memristor M84Memristor M85Is connected with an operational amplifier OP49Are connected to the non-inverting input terminal of an operational amplifier OP49Is connected with a reference voltage Vref1.20An operational amplifier OP49The output end of the first switch is connected with a fifth OR gate circuit; the fifth OR gate comprises a memristor M86Memristor M87And operational amplifier OP50An operational amplifier OP48And operational amplifier OP49Respectively with memristor M86Memristor M87Is connected with the negative pole of the memristor M86Memristor M87Is connected with an operational amplifier OP50Are connected to the non-inverting input terminal of an operational amplifier OP50Is connected with a reference voltage Vref2.14An operational amplifier OP50The output end of (2) is an output port O1。
9. The memristor-based four-input-four-output multifunctional encoder circuit, wherein the logic not gate circuit is a ninth not gate circuit based on a memristor, the ninth not gate circuit comprising a memristor M88And operational amplifier OP51Input port I0AND memristor M88Is connected with the negative pole of the memristor M88Is connected with an operational amplifier OP51Are connected to the inverting input terminal of an operational amplifier OP51The non-inverting input end of the voltage regulator is connected with a reference voltage Vref3.14An operational amplifier OP51The output end of (2) is an output port O0。
10. Root of herbaceous plantThe memristor-based four-input-four-output multifunctional encoder circuit according to claim 9, wherein the operational amplifier OP24-51The highest limiting voltage is 5V, and the lowest limiting voltage is 0V; the reference voltage Vref1.07、Vref1.08、Vref1.09、Vref1.10、Vref1.11、Vref1.12、Vref1.13、Vref1.14、Vref1.15、Vref1.16、Vref1.17、Vref1.18、Vref1.19、Vref1.20Are all 4V, reference voltage Vref2.10、Vref2.11、Vref2.12、Vref2.13、Vref2.14、Vref3.06、Vref3.07、Vref3.08、Vref3.09、Vref3.10、Vref3.11、Vref3.12、Vref2.14、Vref3.13、Vref3.14All are 2V.
Technical Field
The invention relates to the technical field of digital-analog circuits, in particular to a four-input-four-output multifunctional encoder circuit based on a memristor.
Background
In recent years, with the development of society, the degree of industrial production automation is continuously deepened, the market puts higher demands on the encoder, simple and simple signal compilation and conversion cannot meet the requirements of modern automation industry, the basic signal compilation and conversion capability is met, and the encoder has the characteristics of high integration level, low cost, low power consumption and high speed, and is the development direction of future encoders.
The resistance with the memory property is prepared in a laboratory by hewlett packard company in 2008, and the fifth kind of memristor of the passive electronic component, which is predicted to exist before many years, is called from Nature journal. Memristors have very fast speed and very low power consumption, and are capable of boolean operations, so many researchers have begun to study memristor-based logic circuits.
Disclosure of Invention
Aiming at the technical problems of single function, low integration level and high power consumption of the existing encoder, the invention provides a memristor-based four-input-four-output multifunctional encoder circuit which can encode information input into the circuit so as to output a signal representing an encoding result and has the functions of counting the number of logic 1 signals in an input signal and judging the parity of binary numbers of the input signal.
In order to achieve the purpose, the technical scheme of the invention is realized as follows: a four-input-four-output multifunctional encoder circuit based on a memristor comprises four input ports I3、I2、I1、I0And four output ports O3、O2、O1、O0Input port I3、I2、I1And I0Through first channel circuit based on memristor and output port O3Connected, input port I3、I2、I1And I0Through a second channel circuit based on a memristor and an output port O2The second channel circuit is connected with the output port O through a third channel circuit based on the memristor1Connected, input port I0Through a fourth channel circuit based on memristor and an output port O0Are connected.
The output port O3、O2And O1Output input port I in binary form3、I2、I1And I0The number of logic '1's in the formed input signal, input port I3、I2、I1And I0The composed input signal odd-even number passes through the output port O0Output, and when the input signal is even number, the output port O0Output logic '1', whereas when the input signal is odd, the output port O0A logic "0" is output.
The four output ports O3、O2、O1、O0The logical expressions of (a) are respectively:
O3＝I3·I2·I1·I0，
the first channel circuit is a four-input logic AND gate circuit based on a memristor, and an input port I3、I2、I1And I0Are all connected with a four-input logic AND gate circuit which is connected with an output port O3Connecting; the second channel circuit comprises a first logic AND gate circuit, a second logic AND gate circuit, a third logic AND gate circuit, a first logic exclusive OR circuit, a second logic exclusive OR circuit, a third logic exclusive OR circuit and a logic OR gate circuit based on memristors, and the input port I3、I2Are all connected with a first logic AND gate circuit and have an input port I1And I0Are connected with a second logic AND gate circuit, a first logic AND gate circuit and a second logic AND gate circuit are connected with a first logic exclusive OR circuit, and an input port I3、I2Are all connected with a second logic exclusive-OR circuit and have an input port I1And I0Are all connected with a third logic exclusive-OR circuit, the second logic exclusive-OR circuit and the third logic exclusive-OR circuit are all connected with a third logic AND circuit, the output end of the third logic AND circuit and the output end of the first logic exclusive-OR circuit are all connected with a logic OR gate circuit, and the output end of the logic OR gate circuit is an output port O2(ii) a The third channel circuit comprises a fourth logic exclusive-OR circuit based on a memristor, the second logic exclusive-OR circuit is connected with the third logic exclusive-OR circuit, the third logic exclusive-OR circuit and the fourth logic exclusive-OR circuit are both connected with the fourth logic AND circuit, and the output end connected with the fourth logic AND circuit is an output port O1(ii) a The fourth channel circuit comprises a memristor-based logic NOT gate circuit with an input port I0The output end of the logic NOT gate circuit is an output port O4。
The four-input logic AND gate circuit comprises 3 first AND gate circuits, a second AND gate circuit and a third AND gate circuit based on memristors, and an input port I3And an input port I2Connected with two input ends of the first AND circuit respectively, and input port I1And the output end of the first AND gate circuit is connected with the input end of the second AND gate circuit respectively, and the input port I0The output end of the second AND gate circuit is respectively connected with two input ends of a third AND gate circuit, and the output end of the third AND gate circuit is an output port O3(ii) a The first AND gate circuit comprises a memristor M43Memristor M42And operational amplifier OP24Input port I3And an input port I2Respectively and memristor M43Memristor M42Is connected with the negative pole of the memristor M43Memristor M42Is connected with an operational amplifier OP24Are connected to the non-inverting input terminal of an operational amplifier OP24Is connected with a reference voltage Vref1.07An operational amplifier OP24The output end of the first and-gate circuit is connected with a first and-gate circuit; the second AND gate circuit comprises a memristor M44Memristor M45And operational amplifier OP25Input port I1And operational amplifier OP24Respectively with memristor M45Memristor M44Is connected with the negative pole of the memristor M45Memristor M44Is connected with an operational amplifier OP25Are connected to the non-inverting input terminal of an operational amplifier OP25Is connected with a reference voltage Vref1.08An operational amplifier OP25The output end of the first and-gate circuit is connected with a first and-gate circuit; the third AND gate circuit comprises a memristor M47Memristor M46And operational amplifier OP26Input port I0And operational amplifier OP25Respectively with memristor M47Memristor M46Is connected with the negative pole of the memristor M46Memristor M47Is connected with an operational amplifier OP26Are connected to the non-inverting input terminal of an operational amplifier OP26Is connected with a reference voltage Vref1.09An operational amplifier OP26The output end of (2) is an output port O3。
The first logic AND gate circuit is a fourth AND gate circuit based on a memristor, and the fourth AND gate circuit comprises a memristor M49Memristor M48And operational amplifier OP27Input port I3And an input port I2Respectively and memristor M49Memristor M48Is connected with the negative pole of the memristor M49Memristor M48Is connected with an operational amplifier OP27Are connected to the non-inverting input terminal of an operational amplifier OP27Is connected with a reference voltage Vref1.10An operational amplifier OP27The output end of the first logic exclusive or circuit is connected with the first logic exclusive or circuit; the second logic AND gate circuit is a fifth AND gate circuit based on a memristor, and the fifth AND gate circuit comprises a memristor M51Memristor M50And operational amplifier OP28Input port I1And an input port I0Respectively and memristor M51Memristor M50Is connected with the negative pole of the memristor M51Memristor M50Is connected with an operational amplifier OP28Are connected to the non-inverting input terminal of an operational amplifier OP28Is connected with a reference voltage Vref1.11An operational amplifier OP27Is connected to the first logic exclusive or circuit.
The first logic exclusive-OR circuit comprises a first NOT gate circuit, a second NOT gate circuit, a sixth AND gate circuit, a seventh AND gate circuit and a first OR gate circuit which are based on a memristor, the output ends of the fourth AND gate circuit and the fifth AND gate circuit are respectively connected with the first NOT gate circuit and the second NOT gate circuit, the output ends of the first NOT gate circuit and the fifth AND gate circuit are respectively connected with the input end of the sixth AND gate circuit, and the second NOT gate circuit and the fourth AND gate circuit are respectively connected with the input end of the sixth AND gate circuitThe output end of the sixth AND circuit and the output end of the seventh AND circuit are respectively connected with two input ends of a first OR gate circuit, and the output end of the first OR gate circuit is connected with a logic OR gate circuit; the first NOT gate circuit comprises a memristor M52And operational amplifier OP29Memristor M52Negative pole of (2) and operational amplifier OP27Is connected with the output end of the memristor M52Positive electrode of and operational amplifier OP29Are connected to the inverting input terminal of an operational amplifier OP29The non-inverting input end of the voltage regulator is connected with a reference voltage Vref3.06An operational amplifier OP29The output end of the first AND-gate circuit is connected with the input end of the sixth AND-gate circuit; the second NOT-gate circuit comprises a memristor M53And operational amplifier OP30Memristor M53Negative pole of (2) and operational amplifier OP28Is connected with the output end of the memristor M53Positive electrode of and operational amplifier OP30Are connected to the inverting input terminal of an operational amplifier OP30The non-inverting input end of the voltage regulator is connected with a reference voltage Vref3.07An operational amplifier OP30The output end of the first AND-gate circuit is connected with the input end of the seventh AND-gate circuit; the sixth AND gate circuit comprises a memristor M54Memristor M55And operational amplifier OP31An operational amplifier OP29And operational amplifier OP28Respectively with memristor M54Memristor M55Is connected with the negative pole of the memristor M54Memristor M55Is connected with an operational amplifier OP31Are connected to the non-inverting input terminal of an operational amplifier OP31Is connected with a reference voltage Vref1.12An operational amplifier OP31The output end of the first switch is connected with a first OR gate circuit; the seventh AND gate circuit comprises a memristor M56Memristor M57And operational amplifier OP32An operational amplifier OP27And operational amplifier OP30Respectively with memristor M56Memristor M57Is connected with the negative pole of the memristor M56Memristor M57Is equal to the positive pole of the operational amplifierDevice OP32Are connected to the non-inverting input terminal of an operational amplifier OP32Is connected with a reference voltage Vref1.13An operational amplifier OP32The output end of the first switch is connected with a first OR gate circuit; the first OR gate comprises a memristor M58Memristor M59And operational amplifier OP33An operational amplifier OP31And operational amplifier OP32Respectively with memristor M58Memristor M59Is connected with the negative pole of the memristor M58Memristor M59Is connected with an operational amplifier OP33Are connected to the non-inverting input terminal of an operational amplifier OP33Is connected with a reference voltage Vref2.10An operational amplifier OP33The output end of the first logic AND circuit is connected with a third logic AND circuit; the second logic exclusive-OR circuit comprises a third NOT gate circuit, a fourth NOT gate circuit, an eighth AND gate circuit, a ninth AND gate circuit and a second OR gate circuit based on memristors, and an input port I3And an input port I2Is respectively connected with a third NOT gate circuit, a fourth NOT gate circuit, an output end and an input port I of the third NOT gate circuit2Connected with two input ends of the eighth AND gate circuit, the output end of the fourth NOT gate circuit and the input port I respectively3The output ends of the eighth AND gate circuit and the ninth AND gate circuit are respectively connected with two input ends of a second OR gate circuit, and the output end of the second OR gate circuit is connected with a third logic AND gate circuit; the third NOT gate circuit comprises a memristor M60And operational amplifier OP34Memristor M60Negative electrode and input port I3Connected, memristor M60Positive electrode of and operational amplifier OP34Are connected to the inverting input terminal of an operational amplifier OP34The non-inverting input end of the voltage regulator is connected with a reference voltage Vref3.08An operational amplifier OP34The output end of the first and-gate circuit is connected with the input end of the second and-gate circuit; the fourth NOT gate circuit comprises a memristor M61And operational amplifier OP35Memristor M61Negative electrode and input port I2Connected, memristorMachine M61Positive electrode of and operational amplifier OP35Are connected to the inverting input terminal of an operational amplifier OP35The non-inverting input end of the voltage regulator is connected with a reference voltage Vref3.09An operational amplifier OP35The output end of the first and-gate circuit is connected with the input end of the ninth and-gate circuit; the eighth AND gate circuit comprises a memristor M62Memristor M63And operational amplifier OP36An operational amplifier OP34Output terminal and input port I2Respectively and memristor M62Memristor M63Is connected with the negative pole of the memristor M62Memristor M63Is connected with an operational amplifier OP36Are connected to the non-inverting input terminal of an operational amplifier OP36Is connected with a reference voltage Vref1.14An operational amplifier OP36The output end of the first or gate circuit is connected with a first or gate circuit; the ninth AND gate circuit comprises a memristor M64Memristor M65And operational amplifier OP37An operational amplifier OP35Output terminal and input port I3Respectively and memristor M65Memristor M64Is connected with the negative pole of the memristor M65Memristor M64Is connected with an operational amplifier OP37Are connected to the non-inverting input terminal of an operational amplifier OP37Is connected with a reference voltage Vref1.15An operational amplifier OP37The output end of the first or gate circuit is connected with a first or gate circuit; the second OR gate comprises a memristor M66Memristor M67And operational amplifier OP38An operational amplifier OP36And operational amplifier OP37Respectively with memristor M66Memristor M67Is connected with the negative pole of the memristor M66Memristor M67Is connected with an operational amplifier OP38Are connected to the non-inverting input terminal of an operational amplifier OP38Is connected with a reference voltage Vref2.11An operational amplifier OP38The output end of the first logic AND circuit is connected with a third logic AND circuit; the third logic exclusive-OR circuit comprises a fifth NOT gate circuit, a sixth NOT gate circuit, a tenth AND gate circuit and an eleventh AND gateCircuit and third OR gate circuit, input port I0And an input port I1Connected with the fifth NOT gate circuit and the sixth NOT gate circuit respectively, and having output terminal and input terminal I1Connected with two input ends of a tenth AND gate circuit, an output end of a sixth NOT gate circuit and an input port I respectively3The output ends of the tenth AND gate circuit and the eleventh AND gate circuit are respectively connected with two input ends of a third OR gate circuit, and the output end of the third OR gate circuit is connected with a third logic AND gate circuit; the fifth NOT gate circuit comprises a memristor M68And operational amplifier OP39Memristor M68Negative electrode and input port I0Connected, memristor M68Positive electrode of and operational amplifier OP39Are connected to the inverting input terminal of an operational amplifier OP39The non-inverting input end of the voltage regulator is connected with a reference voltage Vref3.10An operational amplifier OP39The output end of the first and-gate circuit is connected with the input end of the tenth and-gate circuit; the sixth NOT gate circuit comprises a memristor M69And operational amplifier OP40Memristor M69Negative electrode and input port I1Connected, memristor M69Positive electrode of and operational amplifier OP40Are connected to the inverting input terminal of an operational amplifier OP40The non-inverting input end of the voltage regulator is connected with a reference voltage Vref3.11An operational amplifier OP40The output end of the first and-gate circuit is connected with the input end of the eleventh and-gate circuit; the tenth AND gate circuit comprises a memristor M70Memristor M71And operational amplifier OP41An operational amplifier OP39Output terminal and input port I1Respectively and memristor M70Memristor M71Is connected with the negative pole of the memristor M70Memristor M71Is connected with an operational amplifier OP41Are connected to the non-inverting input terminal of an operational amplifier OP41Is connected with a reference voltage Vref1.16An operational amplifier OP41The output end of the first or gate circuit is connected with a third or gate circuit; the eleventh AND gate circuit comprises a memristor M72Memristor M73And operational amplifierAmplifier OP42An operational amplifier OP40Output terminal and input port I0Respectively and memristor M73Memristor M72Is connected with the negative pole of the memristor M73Memristor M72Is connected with an operational amplifier OP42Are connected to the non-inverting input terminal of an operational amplifier OP42Is connected with a reference voltage Vref1.17An operational amplifier OP42The output end of the first or gate circuit is connected with a third or gate circuit; the third OR gate comprises a memristor M74Memristor M75And operational amplifier OP43An operational amplifier OP41And operational amplifier OP42Respectively with memristor M74Memristor M75Is connected with the negative pole of the memristor M74Memristor M75Is connected with an operational amplifier OP43Are connected to the non-inverting input terminal of an operational amplifier OP43Is connected with a reference voltage Vref2.12An operational amplifier OP43The output end of the first logic AND circuit is connected with a third logic AND circuit; the third logic AND gate circuit is a twelfth AND gate circuit based on a memristor, and the twelfth AND gate circuit comprises a memristor M76Memristor M77And operational amplifier OP44An operational amplifier OP38And operational amplifier OP43Respectively with memristor M76Memristor M77Is connected with the negative pole of the memristor M76Memristor M77Is connected with an operational amplifier OP44Are connected to the non-inverting input terminal of an operational amplifier OP44Is connected with a reference voltage Vref1.18An operational amplifier OP44The output end of the voltage regulator is connected with a logic OR gate circuit; the logic OR gate circuit is a fourth OR gate circuit which comprises a memristor M78Memristor M79And operational amplifier OP45An operational amplifier OP33And operational amplifier OP44Respectively with memristor M78Memristor M79Is connected with the negative pole of the memristor M78Memristor M79Is connected with an operational amplifier OP45Are connected to the non-inverting input terminal of an operational amplifier OP45Is connected with a reference voltage Vref2.13An operational amplifier OP45Output port O of2。
The fourth logic exclusive-OR circuit comprises a seventh NOT gate circuit, an eighth NOT gate circuit, a thirteenth AND gate circuit, a fourteenth AND gate circuit and a fifth OR gate circuit, and the output end of the second logic exclusive-OR circuit is an operational amplifier OP38And the output of the third logic exclusive-or circuit, i.e. the operational amplifier OP43Respectively connected to the seventh not-gate circuit and the eighth not-gate circuit, the output terminal of the seventh not-gate circuit and the operational amplifier OP43Respectively connected to two input terminals of a thirteenth AND circuit, an output terminal of an eighth NOT circuit and an operational amplifier OP38The output ends of the thirteenth and gate circuit and the fourteenth and gate circuit are respectively connected with two input ends of a fifth or gate circuit, and the output end of the fifth or gate circuit is an output port O1(ii) a The seventh NOT gate circuit comprises a memristor M80And operational amplifier OP46Memristor M80Negative pole of (2) and operational amplifier OP38Is connected with the output end of the memristor M80Positive electrode of and operational amplifier OP46Are connected to the inverting input terminal of an operational amplifier OP39The non-inverting input end of the voltage regulator is connected with a reference voltage Vref3.12An operational amplifier OP46The output end of the first and-gate circuit is connected with the input end of the thirteenth and-gate circuit; the eighth NOT gate circuit comprises a memristor M81And operational amplifier OP47Memristor M81Negative pole of (2) and operational amplifier OP43Is connected with the output end of the memristor M81Positive electrode of and operational amplifier OP47Are connected to the inverting input terminal of an operational amplifier OP47The non-inverting input end of the voltage regulator is connected with a reference voltage Vref3.13An operational amplifier OP47The output end of the first and-gate circuit is connected with the input end of the fourteenth and-gate circuit; the thirteenth AND gate circuit comprises a memristor M82Memristor M83And operational amplifier OP48An operational amplifier OP46And operational amplifier OP43Respectively with memristor M82Memristor M83Is connected with the negative pole of the memristor M82Memristor M83Is connected with an operational amplifier OP48Are connected to the non-inverting input terminal of an operational amplifier OP48Is connected with a reference voltage Vref1.19An operational amplifier OP48The output end of the first switch is connected with a fifth OR gate circuit; the fourteenth AND gate circuit comprises a memristor M84Memristor M85And operational amplifier OP49An operational amplifier OP47And operational amplifier OP38Respectively with memristor M85Memristor M84Is connected with the negative pole of the memristor M84Memristor M85Is connected with an operational amplifier OP49Are connected to the non-inverting input terminal of an operational amplifier OP49Is connected with a reference voltage Vref1.20An operational amplifier OP49The output end of the first switch is connected with a fifth OR gate circuit; the fifth OR gate comprises a memristor M86Memristor M87And operational amplifier OP50An operational amplifier OP48And operational amplifier OP49Respectively with memristor M86Memristor M87Is connected with the negative pole of the memristor M86Memristor M87Is connected with an operational amplifier OP50Are connected to the non-inverting input terminal of an operational amplifier OP50Is connected with a reference voltage Vref2.14An operational amplifier OP50The output end of (2) is an output port O1。
The logic NOT gate circuit is a ninth NOT gate circuit based on a memristor, and the ninth NOT gate circuit comprises a memristor M88And operational amplifier OP51Input port I0AND memristor M88Is connected with the negative pole of the memristor M88Is connected with an operational amplifier OP51Are connected to the inverting input terminal of an operational amplifier OP51The non-inverting input end of the voltage regulator is connected with a reference voltage Vref3.14An operational amplifier OP51The output end of (2) is an output port O0。
The operational amplifier OP24-51The highest limiting voltage is 5V, and the lowest limiting voltage is 0V; the reference voltage Vref1.07、Vref1.08、Vref1.09、Vref1.10、Vref1.11、Vref1.12、Vref1.13、Vref1.14、Vref1.15、Vref1.16、Vref1.17、Vref1.18、Vref1.19、Vref1.20Are all 4V, reference voltage Vref2.10、Vref2.11、Vref2.12、Vref2.13、Vref2.14、Vref3.06、Vref3.07、Vref3.08、Vref3.09、Vref3.10、Vref3.11、Vref3.12、Vref2.14、Vref3.13、Vref3.14All are 2V.
The invention has the beneficial effects that: the four-channel circuit has two encoder functions based on the memristor, utilizes elements such as the memristor, the operational amplifier and the reference voltage to realize logic operations such as AND, OR, NOT and XOR, obtains four-channel signals through four-channel circuits, encodes the input signals, outputs an encoding result after processing, and the output encoding result represents encoding operation made on the input signals; the output result is that the encoder combinational logic circuit based on the memristor encodes the input signal, and the encoder circuit based on the memristor and capable of realizing a specific encoding function has very important practical significance; having 4 input ports I3、I2、I1、I04 output ports O3、O2、O1、O0The circuit comprises 14 AND gate logic function circuits, 5 OR gate logic function circuits and 9 NOT gate logic function circuits based on memristors, wherein 47 memristors, 28 operational amplifiers and 28 reference voltages are used in total to construct four circuit channels; the first channel corresponds to the output port O3The second channel corresponds to the output port O2The third channel corresponds to the output port O1The fourth pathCorresponding output port O0. Compared with the traditional encoder, the circuit of the invention has higher integration level, higher operation speed and lower power consumption, and greatly improves the performance of the encoder.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a circuit configuration diagram of a first channel circuit of the present invention.
FIG. 2 is a circuit diagram of a first module of a second channel circuit according to the present invention.
FIG. 3 is a circuit diagram of a second module of the second channel circuit of the present invention.
FIG. 4 is a circuit diagram of a third module of the second channel circuit according to the present invention.
FIG. 5 is a circuit diagram of a fourth module of the second channel circuit according to the present invention.
Fig. 6 is a circuit configuration diagram of a third channel circuit of the present invention.
Fig. 7 is a circuit configuration diagram of a fourth channel circuit of the present invention.
FIG. 8 is a simulation of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.
A four-input-four-output multifunctional encoder circuit based on a memristor comprises four input ports I3、I2、I1、I0And four output ports O3、O2、O1、O0Input port I3、I2、I1And I0Through first channel circuit based on memristor and output port O3Connected, input port I3、I2、I1And I0Through a second channel circuit based on a memristor and an output port O2The second channel circuit is connected with the output port O through a third channel circuit based on the memristor1Connected, input port I0Through a fourth channel circuit based on memristor and an output port O0Are connected. The design idea of the invention is to determine a memristor model and parameters; building a logic AND gate circuit, a logic OR gate circuit and a logic NOT gate circuit based on the memristor; the mixed realization is based on the XOR logic function circuit of the memristor; the combination enables a more complex memristor-based encoder logic function circuit.
The output port O3、O2And O1Output input port I in binary form3、I2、I1And I0The number of logic '1's in the formed input signal, input port I3、I2、I1And I0The composed input signal odd-even number passes through the output port O0Output, and when the input signal is even number, the output port O0Output logic '1', whereas when the input signal is odd, the output port O0A logic "0" is output.
The four logical expressions correspond to the four output ports of the encoder circuit, respectively. The four output ports O3、O2、O1、O0The logical expressions of (a) are respectively:
O3＝I3·I2·I1·I0，
the first channel circuit is a four-input logic AND gate circuit based on a memristor, and an input port I3、I2、I1And I0Are all connected with a four-input logic AND gate circuit which is connected with an output port O3Connecting; the second channel circuit comprises a first logic AND gate circuit, a second logic AND gate circuit, a third logic AND gate circuit, a first logic exclusive OR circuit, a second logic exclusive OR circuit, a third logic exclusive OR circuit and a logic OR gate circuit based on memristors, and the input port I3、I2Are all connected with a first logic AND gate circuit and have an input port I1And I0Are connected with a second logic AND gate circuit, a first logic AND gate circuit and a second logic AND gate circuit are connected with a first logic exclusive OR circuit, and an input port I3、I2Are all connected with a second logic exclusive-OR circuit and have an input port I1And I0Are all connected with a third logic exclusive-OR circuit, the second logic exclusive-OR circuit and the third logic exclusive-OR circuit are all connected with a third logic AND circuit, the output end of the third logic AND circuit and the output end of the first logic exclusive-OR circuit are all connected with a logic OR gate circuit, and the output end of the logic OR gate circuit is an output port O2(ii) a The third channel circuit comprises a fourth logic exclusive-OR circuit based on a memristor, the second logic exclusive-OR circuit is connected with the third logic exclusive-OR circuit, the third logic exclusive-OR circuit and the fourth logic exclusive-OR circuit are both connected with the fourth logic AND circuit, and the output end connected with the fourth logic AND circuit is an output port O1(ii) a The fourth channel circuit comprises a memristor-based logic NOT gate circuit with an input port I0The output end of the logic NOT gate circuit is an output port O4. The invention comprises a logic AND gate circuit, a logic OR gate circuit, a logic NOT gate circuit and a logic exclusive OR based on memristorsThe OR circuit has two functions, wherein the function I is logic 1 number statistics and can count the input port I at a certain moment3、I2、I1And I0The number of logic '1' signals in the 4 input signals is counted, the statistical results are output in a binary form, the output results are respectively '000', '001', '010', '011' and '100', and the corresponding output port is O3、O2、O1(ii) a Parity judgment of function two being four-bit binary number when input port I3、I2、I1And I0When the input signal is even number, the output signal is logic '1', otherwise, when the input signal is odd number, the output signal is logic '0', and the corresponding output port is O0。
As shown in fig. 1, the four-input logic and gate circuit includes 3 memristor-based first and gate circuits, second and gate circuits, and third and gate circuits, where the first and gate circuits, the second and gate circuits, and the third and gate circuits all implement the function of a logical and, and an input port I3And an input port I2Connected with two input ends of the first AND circuit respectively, and input port I1And the output end of the first AND gate circuit is connected with the input end of the second AND gate circuit respectively, and the input port I0The output end of the second AND gate circuit is respectively connected with two input ends of a third AND gate circuit, and the output end of the third AND gate circuit is an output port O3(ii) a The first AND gate circuit comprises a memristor M43Memristor M42And operational amplifier OP24Input port I3And an input port I2Respectively and memristor M43Memristor M42The negative electrode, namely the M port, is connected with the memristor M43Memristor M42Is the P port of the positive electrode and the operational amplifier OP24Are connected to the non-inverting input terminal of an operational amplifier OP24Is connected with a reference voltage Vref1.07Realize "I3·I2"logical AND" operation shown, operational amplifier OP24The output terminal of which is connected to a second and circuit. The second AND gate circuit comprises a memristor M44Memristor M45And operational amplifier OP25Input port I1And operational amplifier OP24Respectively with memristor M45Memristor M44Is connected with the negative pole of the memristor M45Memristor M44Is connected with an operational amplifier OP25Are connected to the non-inverting input terminal of an operational amplifier OP25Is connected with a reference voltage Vref1.08An operational amplifier OP25The output end of the first and-gate circuit is connected with a first and-gate circuit; realize' I3·I2·I1The logical and operation shown. The third AND gate circuit comprises a memristor M47Memristor M46And operational amplifier OP26Input port I0And operational amplifier OP25Respectively with memristor M47Memristor M46Is connected with the negative pole of the memristor M46Memristor M47Is connected with an operational amplifier OP26Are connected to the non-inverting input terminal of an operational amplifier OP26Is connected with a reference voltage Vref1.09An operational amplifier OP26The output end of (2) is an output port O3Realize "I3·I2·I1·I0The logical and operation shown. The first channel circuit realizes the logic expression' O3＝I3·I2·I1·I0"logical operation shown, containing 6 memristors M42、M43、M44、M45、M46、M473 operational amplifiers OP24、OP25、OP26And 3 reference voltages Vref 1.07、Vref 1.08、Vref 1.09。
The second channel circuit is composed of 9 AND gate logic function circuits, 4 OR gate logic function circuits and 6 NOT gate logic function circuits based on memristors, and a logic expression is realized
The first block of the first channel circuit comprises a first logic and gate circuit, a second logic and gate circuit and a first logic exclusive or circuit, as shown in fig. 2, the first logic and gate circuit is a fourth and gate circuit based on a memristor, and the fourth and gate circuit comprises a memristor M49Memristor M48And operational amplifier OP27Input port I3And an input port I2Respectively and memristor M49Memristor M48Is connected with the negative pole of the memristor M49Memristor M48Is connected with an operational amplifier OP27Are connected to the non-inverting input terminal of an operational amplifier OP27Is connected with a reference voltage Vref1.10Realize "I3·I2"logical" and "operation as shown; operational amplifier OP27Is connected to the first logic exclusive or circuit. The second logic AND gate circuit is a fifth AND gate circuit based on a memristor, and the fifth AND gate circuit comprises a memristor M51Memristor M50And operational amplifier OP28Input port I1And an input port I0Respectively and memristor M51Memristor M50Is connected with the negative pole of the memristor M51Memristor M50And operational amplifierOP28Are connected to the non-inverting input terminal of an operational amplifier OP28Is connected with a reference voltage Vref1.11Realize "I1·I0"logical" and "operation as shown; operational amplifier OP27Is connected to the first logic exclusive or circuit.
The first logic exclusive-OR circuit comprises a first NOT gate circuit, a second NOT gate circuit, a sixth NOT gate circuit, a seventh AND gate circuit and a first OR gate circuit which are based on a memristor, wherein the output ends of the fourth AND gate circuit and the fifth AND gate circuit are respectively connected with the first NOT gate circuit and the second NOT gate circuit, the output ends of the first NOT gate circuit and the fifth AND gate circuit are respectively connected with the input end of the sixth AND gate circuit, the output ends of the second NOT gate circuit and the fourth AND gate circuit are respectively connected with the input end of the seventh AND gate circuit, the output end of the sixth AND gate circuit and the output end of the seventh AND gate circuit are respectively connected with two input ends of the first OR gate circuit, and the output end of the first OR gate circuit is connected with the logic OR gate circuit. The first NOT gate circuit comprises a memristor M52And operational amplifier OP29Memristor M52Negative pole of (2) and operational amplifier OP27Is connected with the output end of the memristor M52Positive electrode of and operational amplifier OP29Are connected to the inverting input terminal of an operational amplifier OP29The non-inverting input end of the voltage regulator is connected with a reference voltage Vref3.06Realize thatThe illustrated logical not operation; operational amplifier OP29And the output end of the second and circuit is connected with the input end of the sixth and circuit. The second NOT-gate circuit comprises a memristor M53And operational amplifier OP30Memristor M53Negative pole of (2) and operational amplifier OP28Is connected with the output end of the memristor M53Positive electrode of and operational amplifier OP30Are connected to the inverting input terminal of an operational amplifier OP30The non-inverting input end of the voltage regulator is connected with a reference voltage Vref3.07Realize that
The second block of the second channel circuit comprises a second logical exclusive-or circuit, as shown in fig. 3, which comprises a memristor-based third not gate circuit, a fourth not gate circuit, an eighth and gate circuit, a ninth and gate circuit and a second or gate circuit, and an input port I3And an input port I2Is respectively connected with a third NOT gate circuit, a fourth NOT gate circuit, an output end and an input port I of the third NOT gate circuit2Connected with two input ends of the eighth AND gate circuit, the output end of the fourth NOT gate circuit and the input port I respectively3The output ends of the eighth AND gate circuit and the ninth AND gate circuit are respectively connected with two input ends of a second OR gate circuit, and the output end of the second OR gate circuit is connected with a third logic AND gate circuit; the third NOT gate circuit comprises a memristor M60And operational amplifier OP34Memristor M60Negative electrode and input port I3Connected, memristor M60Positive electrode of and operational amplifier OP34Are connected to the inverting input terminal of an operational amplifier OP34The non-inverting input end of the voltage regulator is connected with a reference voltage Vref3.08Realize that
The third module of the second channel circuit includes a third exclusive-or circuit, as shown in fig. 4, the third exclusive-or circuit includes a fifth not gate circuit, a sixth not gate circuit, a tenth and gate circuit, an eleventh and gate circuit, and a third or gate circuit, and the input port I is0And an input port I1Connected with the fifth NOT gate circuit and the sixth NOT gate circuit respectively, and having output terminal and input terminal I1Connected with two input ends of a tenth AND gate circuit, an output end of a sixth NOT gate circuit and an input port I respectively3The output ends of the tenth AND gate circuit and the eleventh AND gate circuit are respectively connected with two input ends of a third OR gate circuit, and the output end of the third OR gate circuit is connected with a third logic AND gate circuit. The fifth NOT gate circuit comprises a memristor M68And operational amplifier OP39Memristor M68Negative electrode and input port I0Connected, memristor M68Positive electrode of and operational amplifier OP39Are connected to the inverting input terminal of an operational amplifier OP39The non-inverting input end of the voltage regulator is connected with a reference voltage Vref3.10Realize that
The fourth module of the second channel circuit comprises a third logic AND gate circuit and a logic OR gate circuit, as shown in FIG. 5, the third logic AND gate circuit is a twelfth memristor-based AND gate circuit, and the twelfth AND gate circuit comprises a memristor M76Memristor M77And operational amplifier OP44An operational amplifier OP38And operational amplifier OP43Respectively with memristor M76Memristor M77Is connected with the negative pole of the memristor M76Memristor M77Is connected with an operational amplifier OP44Are connected to the non-inverting input terminal of an operational amplifier OP44Is connected with a reference voltage Vref1.18An operational amplifier OP44The output end of the voltage regulator is connected with a logic OR gate circuit; realize that
The third channel circuit comprises a fourth logic exclusive-OR circuit, is composed of 2 AND gate logic function circuits based on memristors, 1 OR gate logic function circuit and 2 NOT gate logic function circuits, and realizes a logic expression
The fourth channel circuit is composed of 1 NOT gate logic function circuit based on the memristor, and the realization is that
Examples illustrate that:
1) the maximum limiting voltage of all the operational amplifiers included in the invention is 5V, and the minimum limiting voltage is 0V. First channel reference voltage Vref 1.07、Vref 1.08、Vref 1.09Are all 4V; reference voltage V of the second channelref 1.10、Vref 1.11、Vref 1.12、Vref 1.13、Vref 1.14、Vref 1.15、Vref 1.16、Vref 1.17、Vref 1.18Are all 4V, reference voltage Vref 2.10、Vref 2.11、Vref 2.12、Vref 2.13、Vref 3.06、Vref 3.07、Vref 3.08、Vref 3.09、Vref 3.10、Vref 3.11Are all 2V; third channel reference voltage Vref 1.19、Vref 1.20Are all 4V, Vref 2.14、Vref 3.12、Vref 3.13Are all 2V; fourth channel reference voltage Vref 3.14Is 2V.
2) Memristor M of first channel circuit42、M43、M44、M45、M46、M47An operational amplifier OP24、OP25、OP26And a reference voltage Vref 1.07、Vref 1.08、Vref 1.09And realizing four-input logic AND operation. Memristor M of second channel circuit48、M49An operational amplifier OP27And a reference voltage Vref 1.10Realizing logic AND operation; memristor M50、M51An operational amplifier OP28And a reference voltage Vref 1.11Realizing logic AND operation; memristor M52、M53、M54、......、M58、M59An operational amplifier OP29、OP30、OP31、OP32、OP33And a reference voltage Vref 3.06、Vref 3.07、Vref 1.12、Vref 1.13、Vref 2.10Realizing logic exclusive-or operation; memristor M60、M61、M62、......、M66、M67An operational amplifier OP34、OP35、OP36、OP37、OP38And a reference voltage Vref 3.08、Vref 3.09、Vref 1.14、Vref 1.15、Vref 2.11Realizing logic exclusive-or operation; memristor M68、M69、M70、......、M74、M75An operational amplifier OP39、OP40、OP41、OP42、OP43And a reference voltage Vref 3.10、Vref 3.11、Vref 1.16、Vref 1.17、Vref 2.12Realizing logic exclusive-or operation; memristor M76、M77An operational amplifier OP44And a reference voltage Vref 1.18Realizing logic AND operation; memristor M78、M79An operational amplifier OP45And a reference voltage Vref 2.13A logical or operation is implemented. Memristor M of third channel circuit80、M81、M82、......、M86、M87An operational amplifier OP46、OP47、OP48、OP49、OP50Reference voltage Vref 3.12、Vref 3.13、Vref 1.19、Vref 1.20、Vref 2.14A logical xor operation is implemented. Memristor M of fourth channel circuit88Operational amplifier OP51And a reference voltage Vref 3.14A logical not operation is implemented.
The four channels are connected together and the initial value is (0, 0, 0, 0). The invention utilizes elements such as memristors, operational amplifiers, reference voltages and the like to realize logical operations such as AND, OR, NOT, XOR and the like, four paths of signals are obtained through four paths of circuits, the circuits encode input signals, a coding result is output after processing, the output coding result represents coding operation made on the input signals, and SPICE simulation software is used for verification, as shown in figure 8. I is3、I2、I1、I0Is an input end of a signal, O3、O2、O1、O0Is the output end of the signal.
(1) Passing I in a time period of 0us to 0.1us3、I2、I1、I0The input signal of the port is 0V and passes through O3、O2、O1The output signals of the ports are all 0V and pass through O0The output signal of the port is 5V;
(2) passing I in a time period of 0.1us to 0.2us3、I2、I1Input signal of port is 0V, passing through I0The input signal to the port is 5V, which is then passed through O3、O2、O0Output signal of port is 0V, through O1The output signal of the port is 5V;
(3) passing I in a time period of 0.2us to 0.3us3、I2、I0Input signal of port is 0V, passing through I1The input signal to the port is 5V, which is then passed through O3、O2Output signal of port is 0V, through O1、O0The output signal of the port is 5V;
(4) over a time period of 0.3us to 0.4usPer I3、I2Input signal of port is 0V, passing through I1、I0The input signal to the port is 5V, which is then passed through O3、O1、O0Output signal of port is 0V, through O2The output signal of the port is 5V;
(5) passing I in a time period of 0.4us to 0.5us3、I1、I0Input signal of port is 0V, passing through I2The input signal to the port is 5V, which is then passed through O3、O2Output signal of port is 0V, through O1、O0The output signal of the port is 5V;
(6) passing I in a time period of 0.5us to 0.6us3、I1Input signal of port is 0V, passing through I2、I0The input signal to the port is 5V, which is then passed through O3、O1、O0Output signal of port is 0V, through O2The output signal of the port is 5V;
(7) passing I in a time period of 0.6us to 0.7us3、I0Input signal of port is 0V, passing through I2、I1The input signal to the port is 5V, which is then passed through O3、O1Output signal of port is 0V, through O2、O0The output signal of the port is 5V;
(8) passing through the port I for a period of 0.7us to 0.8us3Is 0V, via I2、I1、I0The input signal to the port is 5V, which is then passed through O3、O0Output signal of port is 0V, through O2、O1The output signal of the port is 5V;
(9) passing I in a time period of 0.8us to 0.9us2、I1、I0Input signal of port is 0V, passing through I3The input signal to the port is 5V, which is then passed through O3、O2Output signal of port is 0V through port O1、O0The output signal of (2) is 5V;
(10) passing I in a time period of 0.9us to 1.0us2、I1Port(s)Is 0V, via I3、I0The input signal to the port is 5V, which is then passed through O3、O1、O0Output signal of port is 0V, through O2The output signal of the port is 5V;
(11) over a period of 1.0us to 1.1us, I2、I0Input signal of port is 0V, passing through I3、I1The input signal to the port is 5V, which is then passed through O3、O1Output signal of port is 0V, through O2、O0The output signal of the port is 5V;
(12) over a period of 1.1us to 1.2us, I2Input signal of port is 0V, passing through I3、I1、I0The input signal to the port is 5V, which is then passed through O3、O0Output signal of port is 0V, through O2、O1The output signal of the port is 5V;
(13) over a period of 1.2us to 1.3us, I1、I0Input signal of port is 0V, passing through I3、I2The input signal to the port is 5V, which is then passed through O3、O1Output signal of port is 0V, through O2、O0The output signal of the port is 5V;
(14) over a period of 1.3us to 1.4us, I1Input signal of port is 0V, passing through I3、I2、I0The input signal to the port is 5V, which is then passed through O3、O0Output signal of port is 0V, through O2、O1The output signal of the port is 5V;
(15) passing through the port I for a period of 1.4us to 1.5us0Is 0V, via I3、I2、I1The input signal to the port is 5V, which is then passed through O3Output signal of port is 0V, through O2、O1、O0The output signal of the port is 5V;
(16) over a period of 1.5us to 1.6us, I3、I2、I1、I0Port(s)Is 5V, when passing through O2、O1、O0Output signal of port is 5V, passing through O3The output signal of the port is 5V.
The invention is formed by combining an AND gate logic function circuit, an OR gate logic function circuit, an NOT gate logic function circuit and an XOR logic function circuit which are based on memristors, wherein 47 memristors, 28 operational amplifiers and 28 reference voltages are used in total, the invention comprises 14 AND gate logic function circuits, 5 OR gate logic function circuits and 9 NOT gate logic function circuits which are based on memristors, and 4 XOR logic function circuits exist. The encoder circuit has the characteristics of high integration level, low power consumption and high speed, and greatly improves the performance of the encoder.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
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