阅读说明：本技术 与解码窗口的信号通信 (Signal communication with decoding window ) 是由 文森特·皮埃尔·马蒂内斯 于 2019-07-05 设计创作，主要内容包括：本公开的方面涉及处理从不同源接收的信号,例如可关于基于相应信号经过的距离和/或由于振荡器时钟失配而接收具有相应时间偏移的信号。如可根据一个或多个实施例实施,为并行接收的通信中的相应通信中的符号生成相应快速傅立叶变换(FFT)级数。对于接收器正试图解码的每个消息,对所述相应FFT级数执行信道估计,并且基于指示针对所述特定消息的所述相应FFT级数中的干扰的度量来选择所述FFT级数中的一个。基于所述选定FFT级数来设置解码计时窗口,且对所述选定FFT级数进行解码。(Aspects of the present disclosure relate to processing signals received from different sources, e.g., signals having respective time offsets may be received with respect to based on a distance traveled by the respective signals and/or due to oscillator clock mismatch. As can be implemented in accordance with one or more embodiments, respective Fast Fourier Transform (FFT) series are generated for symbols in respective ones of the concurrently received communications. For each message that a receiver is attempting to decode, performing channel estimation on the respective FFT bin and selecting one of the FFT bins based on a metric indicative of interference in the respective FFT bin for the particular message. A decoding timing window is set based on the selected FFT bin and the selected FFT bin is decoded.)

1. An apparatus, comprising:

an antenna circuit configured and arranged to receive communications from a plurality of sources in parallel; and

an Orthogonal Frequency Division Multiplexing (OFDM) receiver circuit configured and arranged to:

generate respective Fast Fourier Transform (FFT) series for symbols in respective ones of the received communications,

performing channel estimation for a first one of the FFT levels,

performing channel estimation for a second one of the FFT levels,

selecting one of the first and second FFT levels based on a metric indicative of interference for the first and second FFT levels,

setting a decoding timing window based on said selected FFT stage number, an

And decoding the selected FFT level and outputting the decoding result.

2. The apparatus of claim 1, wherein the OFDM receiver circuit is configured and arranged to set a timing window for decoding having an offset relative to a synchronous clock, the timing window corresponding to a propagation delay of the selected one of the first and second FFT stages.

3. The apparatus of any of claims 1-2, wherein the first and second ones of the FFT stages correspond to an original communication and a reflection of the communication from one of the sources, respectively, and the OFDM receiver circuit is configured and arranged to select the FFT stage corresponding to the original communication based on the metric.

4. The apparatus of any of claims 1 to 3, wherein the OFDM receiver circuitry is configured and arranged to select one of the first and second FFT levels based on one of the plurality of sources from which the FFT levels are to be decoded and a metric of the FFT levels corresponding to the one of the plurality of sources.

5. The apparatus of any of claims 1 to 4, wherein the OFDM receiver circuit is configured and arranged to select the first or second FFT stage number based on a metric indicative of one or both of: a signal-to-noise ratio (SNR) of the corresponding FFT bin, and a Time Offset Estimate (TOE) of the corresponding FFT bin.

6. The apparatus of any of claims 1 to 5, wherein the OFDM receiver circuit is configured and arranged to set the decoding time window by setting an offset of a clock synchronized with the OFDM receiver circuit.

7. The apparatus of any of claims 1-6, wherein the OFDM receiver circuitry is configured and arranged to perform the channel estimation using different time windows, and to select one of the first and second FFT levels for the one of the different time windows set to the decoding timing window.

8. The device of claim 7, wherein the OFDM receiver circuit is configured and arranged to scan the time window across a range of offset values relative to a clock to which the OFDM receiver circuit is synchronized.

9. The apparatus of any of claims 1-8, wherein the OFDM receiver circuit comprises:

respective FFT circuits each configured and arranged to generate one of the respective FFT levels from the parallel communications received by the antenna;

respective channel estimation circuits each configured and arranged to provide channel estimation data for an FFT stage number received from one of the FFT circuits; and

a gating circuit configured and arranged to indicate receipt of the metric of interference from the channel estimation circuit and to select the one of the first and second FFT bin numbers based on the received metric.

10. A method, comprising:

for communications received in parallel from multiple sources, generating respective Fast Fourier Transform (FFT) series for symbols in respective ones of the received communications;

performing channel estimation for a first one of the FFT levels;

performing channel estimation for a second one of the FFT levels;

selecting one of the first and second ones of the FFT levels based on a metric indicative of interference for the first and second ones of the FFT levels;

setting a decoding timing window based on the selected FFT bin number; and

and decoding the selected FFT level and outputting the decoding result.

Technical Field

The present disclosure relates to Orthogonal Frequency Division Multiplexing (OFDM), and more particularly, to selective processing of OFDM signals from respective sources.

Background

In various communication systems, synchronization and timing are important to ensure that communications are accurately received and decoded. This is relevant for various different types of communication systems. For example, in a synchronization system, such as the 3 rd generation partnership project (3GPP) internet of vehicles (V2X), it is inherently a synchronization system, meaning that all users are assumed to be synchronized on a common reference timing. However, achieving such timing can be challenging.

In a synchronous system, the transmitter may align its messages with Global Navigation Satellite System (GNSS) timing. In such OFDM systems, the receiver may locate its receive Fast Fourier Transform (FFT) window based on GNSS timing, however, timing mismatch may occur. Thus, certain methods, such as those involving Cyclic Prefix (CP), may be used to avoid inter-symbol interference (ISI). For example, the end of an Orthogonal Frequency Division Multiplexing (OFDM) symbol IQ is sampled and a CP is added at the beginning to absorb the delay. However, when the propagation delay extends beyond the CP duration, interference may occur. Receiving messages under conditions where the transmitter-to-receiver distance is large becomes more challenging.

These and other things have challenged the efficacy and efficiency of signal communication for a variety of applications.

Disclosure of Invention

According to a first aspect of the invention, there is provided an apparatus comprising:

an antenna circuit configured and arranged to receive communications from a plurality of sources in parallel; and

an Orthogonal Frequency Division Multiplexing (OFDM) receiver circuit configured and arranged to:

generate respective Fast Fourier Transform (FFT) series for symbols in respective ones of the received communications,

performing channel estimation for a first one of the FFT levels,

performing channel estimation for a second one of the FFT levels,

selecting one of the first and second FFT levels based on a metric indicative of interference for the first and second FFT levels,

setting a decoding timing window based on said selected FFT stage number, an

And decoding the selected FFT level and outputting the decoding result.

In one or more embodiments, the OFDM receiver circuit is configured and arranged to set a timing window for decoding having an offset relative to a synchronous clock, the timing window corresponding to a propagation delay of the selected one of the first and second FFT stages.

In one or more embodiments, the first and second ones of the FFT stages correspond to an original communication and a reflection of the communication, respectively, from one of the sources, and the OFDM receiver circuit is configured and arranged to select the FFT stage corresponding to the original communication based on the metric.

In one or more embodiments, the OFDM receiver circuit is configured and arranged to select one of the first and second FFT stages based on one of the plurality of sources from which the FFT stage is to be decoded and a metric of the FFT stage corresponding to the one of the plurality of sources.

In one or more embodiments, the OFDM receiver circuit is configured and arranged to select the first FFT stage number or the second FFT stage number based on a metric indicative of one or both of: a signal-to-noise ratio (SNR) of the corresponding FFT bin, and a Time Offset Estimate (TOE) of the corresponding FFT bin.

In one or more embodiments, the OFDM receiver circuit is configured and arranged to set the decoding time window by setting an offset of a clock synchronized with the OFDM receiver circuit.

In one or more embodiments, the OFDM receiver circuit is configured and arranged to perform the channel estimation using different time windows, and to select one of the first and second FFT stage numbers for the one of the different time windows set to the decoding timing window.

In one or more embodiments, the OFDM receiver circuit is configured and arranged to scan the time window across a range of offset values relative to a clock to which the OFDM receiver circuit is synchronized.

In one or more embodiments, the OFDM receiver circuit includes:

respective FFT circuits each configured and arranged to generate one of the respective FFT levels from the parallel communications received by the antenna;

respective channel estimation circuits each configured and arranged to provide channel estimation data for an FFT stage number received from one of the FFT circuits; and

a gating circuit configured and arranged to indicate receipt of the metric of interference from the channel estimation circuit and to select the one of the first and second FFT bin numbers based on the received metric.

In one or more embodiments, the apparatus includes an equalization circuit configured and arranged to equalize the selected one of the first and second FFT bins; and

a channel decoding circuit configured and arranged to decode a selected one of the equalized of the first and second FFT bins.

According to a second aspect of the invention, there is provided a method comprising:

for communications received in parallel from multiple sources, generating respective Fast Fourier Transform (FFT) series for symbols in respective ones of the received communications;

performing channel estimation for a first one of the FFT levels;

performing channel estimation for a second one of the FFT levels;

selecting one of the first and second ones of the FFT levels based on a metric indicative of interference for the first and second ones of the FFT levels;

setting a decoding timing window based on the selected FFT bin number; and

and decoding the selected FFT level and outputting the decoding result.

In one or more embodiments, setting the decoding timing window includes setting the timing window with an offset relative to a synchronous clock, the timing window corresponding to a propagation delay of the selected one of the first and second FFT bins.

In one or more embodiments, selecting the one of the first and second FFT stages comprises selecting one of the first and second FFT stages based on a metric comprising one or both of a Time Offset Estimate (TOE) or a signal-to-noise ratio (SNR) of the respective FFT stage.

In one or more embodiments, selecting the one of the first and second FFT orders comprises selecting one of the first and second FFT orders based on one of the plurality of sources from which the FFT order is to be decoded and a metric of the FFT order corresponding to the one of the plurality of sources.

In one or more embodiments, the step of performing channel estimation comprises performing channel estimation on each of the FFT levels in each of the different time windows, or by scanning the time windows across a range of offset values relative to a clock synchronization signal on which the respective communication is transmitted, and

selecting the one of the first and second FFT bin numbers comprises selecting one of the FFT bin numbers for one of the different time windows set to the decoding timing window.

These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter.

Drawings

Various exemplary embodiments may be more completely understood in consideration of the following detailed description in connection with the accompanying drawings, in which:

FIGS. 1A and 1B constitute system level diagrams in accordance with the present disclosure showing example circuits and associated methods for selecting a signal upon which signal processing is based, where FIG. 1A shows a circuit for selecting and processing one of two or more received signals by an equalizer, and where FIG. 1B shows additional processing of the selected signal;

FIG. 2 illustrates a time-based plot of a receiver and corresponding transmitter as may be implemented in accordance with the present disclosure;

FIG. 3 illustrates a graph of decoding performance as may be implemented in accordance with the present disclosure; and

fig. 4 illustrates a graph of decoding performance for respective time windows, as may be implemented in accordance with one or more embodiments.

While the various embodiments discussed herein are capable of undergoing modifications and alternative forms, various aspects of the various embodiments have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the disclosure to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the invention, including aspects defined in the claims. In addition, the term "example" as used throughout this application is for illustration only, and not for limitation.

Detailed Description

Aspects of the present disclosure are believed to be applicable to a variety of different types of apparatuses, systems, and methods involving selection and processing of signals, such as may be implemented for adjusting time windows for processing delayed signals generated using synchronous and/or common clocks. In certain implementations, aspects of the present disclosure have been shown to be beneficial when used in the context of V2X communications, where individual transmitters located at different distances from the receiver operate on a common clock synchronization and, due to distance, receive respective signals at different time offsets. Such an aspect is also beneficial in the case of reflected V2X signals received from a common source, which may be due to reflections of structures such as buildings. In some embodiments, relative to common clock synchronization, characteristics of respective signals are used to align reception of a particular signal with a time window offset in order to facilitate accurate reception of one of the signals. For example, these approaches may address challenges such as those characterized in the summary section herein. While various aspects may be understood through the following discussion using non-limiting examples of exemplary scenarios, it is not necessarily limited thereto.

Thus, in the following description, numerous specific details are set forth to describe specific examples presented herein. It should be apparent, however, to one skilled in the art that one or more other examples and/or variations of these examples may be practiced without all of the specific details set forth below. In other instances, well-known features have not been described in detail so as not to obscure the description of the examples herein. For ease of illustration, the same reference numbers may be used in different drawings to refer to the same elements or to additional examples of the same elements. Moreover, although aspects and features may be described in some cases in separate figures, it should be appreciated that features from one figure or embodiment may be combined with features of another figure or embodiment, even if the combination is not explicitly shown or explicitly described as a combination.

Various embodiments relate to the implementation of various types of communication networks, such as networks that relate to a collaborative environment in which respective communication nodes communicate with each other. In one such embodiment, the communication nodes autonomously and cooperatively select their resources according to a Decentralized Congestion Control (DCC) scheme without having to use a master node or base station. For example, long term evolution internet of vehicles (LTE-V2X) "mode 4" is an example of a cooperative type configuration. LTE-V2X may be implemented as part of an Intelligent Transport System (ITS) system. In such networks, a common clock for (e.g., sidelink) users may be extracted from Global Navigation Satellite System (GNSS) signals. In addition, such users may periodically send synchronization subframes such that surrounding users that are unable to receive GNSS signals may still obtain a reference clock.

Certain embodiments may relate to the 3GPP sidelink Rel-14 and Rel-15 standards, such as "mode 3" and "mode 4" designed for V2X applications, and their implementation in mobile environments (e.g., automobiles, motorcycles, bicycles, trains, pedestrian handsets, or emergency vehicles). In addition to LTE-V2X, various other Orthogonal Frequency Division Multiplexing (OFDM) standards, such as 5G, may also be used in this context. In various contexts, OFDM may refer to a series of OFDM waveforms, and may involve OFDM (e.g., IEEE 802.11p), Orthogonal Frequency Division Multiple Access (OFDMA) (e.g., LTE downlink), or single carrier frequency division multiple access (SC-FDMA) (e.g., LTE uplink or LTE sidelink). Various embodiments may involve decoding of one or more of a physical side link broadcast channel (PSBCH or BCH), a physical side link shared channel (PSSCH) for data signals, and a physical side link control channel (PSCCH) for control signals.

Thus, various aspects may be implemented with various criteria, such as: 4G LTE-D2D Rel-12, 4G LTE-V2XRel-14, 4G LTE-V2X Rel-15 and 5G NR-V2X Rel-15/16. For 4G LTE-V2X Rel-14 and Rel-15, a control channel (PSCCH) and a data channel (PSSCH) may be utilized. In addition, various embodiments relate to 3GPP CellularV2X, such as LTE Rel-14, LTE Rel-15, and 5G NR V2X, which may facilitate reception and additionally facilitate an increase in the range of LTE-V2X receivers (e.g., from 700 meters to 2100 meters). Such embodiments may be performed with a reasonable increase in signal processing complexity (e.g., 1.2 times). In some embodiments, several Fast Fourier Transform (FFT) stages are used to reduce the amount of inter-symbol interference (ISI) observed when the Transceiver (TX) and Receiver (RX) are far apart, and therefore experience a significant time offset. Channel estimation duplication may be partially suppressed by selecting one of two or more signals based on an early channel estimation function. With this approach, more comprehensive functions such as heavy duty equalization and channel decoding (e.g., primarily Turbo decoding) can be performed on a particular signal being processed. This avoids unnecessary additional processing of signals that are not specific to a particular situation, such as signals from other vehicles or reflected signals from a target vehicle.

Various embodiments help mitigate timing errors in LTE V2X systems. For example, due to such timing errors, the receiver may place its FFT window in the "half CP" position. The "half CP" start index helps to combat possible negative time offsets (from RX perspective). This may occur if the transmitter does not properly "advance" synchronization, or the receiver does not properly "delay" synchronization. If the transmitter is located further away, the receiver may "delay" collecting its information due to the propagation time of the signal in the air, and ISI (inter-symbol interference) may be generated due to the mismatch between the TX message timing and the RX positioning window. Thus, various methods as characterized herein reduce timing error by selecting a signal and setting a decoding timing window based on the selected signal, such as may be applicable in such cases.

In a more specific embodiment, data from different FFT orders for respective signals is used to limit the amount of ISI by focusing on the timing window of the signal to be received. For example, a portion of the channel estimation may be performed on respective FFT series, and one of the series may be selected based on a metric indicative of ISI. A decoding timing window may then be set and used for a selected one of the FFT stages. The selected FFT stage is then decoded without having to decode another FFT stage or other FFT stages, which facilitates reception while reducing excessive signal processing overhead.

Various aspects of the present disclosure may be implemented for vehicle communications involving LTE-V2X implementations with two types of subframes, data subframes, and synchronization subframes. The data sub-frame vias PSCCH and PSCCH channels carry the data payload of the user. The PSCCH and PSCCH may include demodulation reference signal (DMRS) symbols. The DMRS provides a channel estimation pilot for demodulating PSCCH or PSCCH. The data payload may be constructed by the MAC layer as a CAM (cooperative awareness message) or DENM (decentralized environment notification message) and may include speed, location, heading, and/or traffic information. The synchronization subframe transmits PSS, SSS (primary and secondary synchronization signal), DMRS and BCH. PSS and SSS indicate frame timing for frequency and time synchronization of V2X users. The DMRS provides a channel estimation pilot for demodulating the BCH. The BCH carries information about carrier parameters such as system bandwidth (e.g., 1.4, 3, 5, 10, 15, or 20MHz), Frequency Division Duplex (FDD) or Time Division Duplex (TDD) mode, details such as subframe configuration and special subframe organization for the TDD mode, frame and subframe numbers of BCH, PSS and SSS transmission periods, and Boolean (Boolean) flag indicating whether User Equipment (UE) is in or out of base station coverage.

As may be implemented in accordance with one or more embodiments, an apparatus comprises: an antenna circuit to receive communications from multiple sources in parallel; and an Orthogonal Frequency Division Multiplexing (OFDM) receiver circuit that generates respective Fast Fourier Transform (FFT) series for symbols in respective ones of the received communications. The OFDM circuit performs channel estimation for respective FFT stages and selects one of the respective FFT stages based on a metric indicative of interference for the FFT stages. Such metrics may, for example, indicate one or both of signal-to-noise ratio (SNR) or Time Offset Estimate (TOE) for the respective FFT stage. The respective FFT orders may emanate, for example, from respective individual sources located at different distances, or may correspond to the original source and its reflections. Thus, the OFDM receiver circuit may select an FFT stage number that corresponds to the closest one of the original sources, a target one of the original sources, or the original source relative to a reflection of the signal it generates. The OFDM circuit additionally sets a decoding timing window based on the selected FFT stage number, and decodes the selected FFT stage number and outputs a result of the decoding.

In some schemes, such as the LTE access scheme, there may be multiple users per subframe, and metrics such as TOE, SNR, etc. may be set for each message (or each user). Thus, one of the FFT levels may be selected for each message or each user based on such metrics. Within a particular subframe, the OFDM receiver may decide to use a first FFT stage for a first user and a second FFT stage for a second user (and so on for subsequent users). This approach may be used for access schemes that transmit several messages on different subcarrier sets during the same subframe. Thus, the metric, gating, equalization, and channel decoding may be performed per message/per user (e.g., the front-end FFT is common to the users).

The decoding timing window may be set in a variety of ways. In some implementations, the decoding timing window is provided with an offset relative to the synchronous clock, where the offset may additionally correspond to a propagation delay of a selected one of the FFT stages.

In some implementations, different time windows are used for channel estimation, and one of the FFT stage numbers is selected for one of the different time windows set as the decoding timing window. For example, channel estimation may be performed for each FFT bin using a respective time window offset from the clock source by a predefined value. Using the aforementioned metrics, the "best" one of the FFT bins may be selected as the bin indicating the strongest signal, relative to the selected and other FFT bins in each of the respective time windows. This method may involve scanning a time window across a range of offset values relative to a clock to which the OFDM receiver circuit is synchronized.

In some implementations, the aforementioned OFDM receiver circuitry includes respective FFT circuitry, channel estimation circuitry, and gating circuitry. The FFT circuits each generate one of a respective FFT stage number from the parallel communications received by the antennas. A respective channel estimation circuit provides channel estimation data for FFT stage numbers received from one of the FFT circuits, and a gating circuit receives a metric indicative of interference from the channel estimation circuit and selects an FFT stage number based on the received metric. The OFDM circuit may additionally include an equalization circuit that equalizes a selected FFT stage, and a channel decoding circuit that decodes a selected one of the equalization of the first FFT stage and the second FFT stage.

According to an embodiment based on certain methods, the method proceeds as follows. For communications received in parallel from multiple sources, respective Fast Fourier Transform (FFT) bins are generated for symbols in respective ones of the received communications, and channel estimation is performed for each generated FFT bin. For each message attempting to decode, one of the FFT bins is selected based on a metric indicative of interference for the FFT bin. Such metrics may include, for example, one or both of a Time Offset Estimate (TOE) or a signal-to-noise ratio (SNR) for the respective FFT stage. A decoding timing window is set based on the selected FFT bin and used to decode the selected FFT bin. The decoding timing window may be provided with an offset relative to the synchronous clock, the timing window corresponding to a propagation delay of a selected one of the first and second FFT stages. The decoded result is then provided as output.

In some implementations, channel estimation is performed on each of the FFT levels in each of the different time windows and different sets of metrics, e.g., Time Offset Estimates (TOE) or signal-to-noise ratios (SNR), are generated accordingly. The different FFT levels represent various time windows across a range of offset values relative to the clock synchronization signal on which the respective communications are transmitted.

According to another embodiment, an apparatus includes respective FFT circuits that generate respective Fast Fourier Transform (FFT) series for symbols in respective ones of received communications. The respective channel estimation circuit provides channel estimation data for the FFT stage number received from one of the FFT circuits. The gating circuitry selects one of the respective FFT stages based on the metric received from the respective channel estimation circuitry, and the timing circuitry sets a decoding timing window based on the selected one of the respective FFT stages. In some implementations, the gating circuitry selects one of the respective FFT stages based on a metric that includes one or both of a Time Offset Estimate (TOE) or a signal-to-noise ratio (SNR) of the respective FFT stage. In addition, the timing circuit may set the decode timing window by setting an offset relative to a received clock synchronization signal on which a respective one of the communications is received. In some implementations, the apparatus additionally includes an equalization circuit to equalize the selected one of the respective FFT bin numbers and a channel decoding circuit to decode the equalized selected one of the respective FFT bin numbers.

Turning now to the drawings, fig. 1A and 1B illustrate a system 100 with exemplary circuitry, and associated method, for selecting a signal upon which signal processing is based, according to the present disclosure. Fig. 1A shows circuitry for selecting and processing one of two or more received signals by an equalizer, and fig. 1B shows additional processing of the selected signal beyond the equalizer and involving channel decoding. At blocks 110 and 120, the antenna input is processed (e.g., multiplied by e)^{j2πΔf，Δf＝7.5kHz}) To generate respective FFT levels from different signal sources, such as two different original sources or an original source and its reflection, and it should be understood that additional such blocks may be implemented to generate FFT levels from additional signal sources. Next, at blocks 112 and 122, channel estimation is performed on the DMRS symbols for each respective FFT stage. At block 130, based on the slave channelThe provided metric is estimated, one of the respective FFTs is selected (e.g., using a gating function), and the selected FFT stage number is provided to a second signal processing step, where the interpretation weights are provided at block 140 and equalization is performed at block 150, which block 150 is provided with data symbols from the appropriate FFT stage number. Referring to fig. 1B, the output of the equalizer is provided at 150 as an input to a channel decoding block 160, which decodes the FFT stages and provides a decoded output therefrom.

Thus, blocks 110 and 120 may be implemented generally for all users, and thus, a large number of subcarriers (e.g., 600 subcarriers for a 10MHz carrier size) may be output. The 600 sub-carriers may be divided into several subsets related to various users. Subsequent blocks (112, 122, 130, 150, 160) may thus be performed for each message (or each user) on the subset of subcarriers associated with a given user. In addition, while the first part of the channel estimation process is performed for each FFT stage, the second part of the channel estimation, which may be heavier in terms of signal processing complexity, and the equalizer and channel decoding functions are not repeated for each respective FFT stage. This helps to reduce complexity.

It should be noted that although a particular channel estimation function is present within each of blocks 112 and 122, various channel estimation functions may be performed to suit particular applications. By way of example, see channel estimation block 112, H in FIG. 1A_rawBlock 113 may generate a vector with the original channel estimates, Time Offset Estimation (TOE) block 114 may perform estimation of the time offset for the FFT bins, and Frequency Offset Estimation (FOE) block 115 may perform estimation of the frequency offset for the FFT bins. Block 116 is a window filter that provides a channel estimate to equalizer 150. Block 117 also provides an N estimated output to equalizer 150. At block 118, a signal-to-noise ratio (SNR) estimate is generated.

Selection of one of the FFT stages may be made using various metrics. By way of example, the dashed line illustrates a method of selecting one of the FFT levels using the outputs from the TOE block 114 and/or the SNR block 118. Thus, either or both of these outputs may be used in this context.

Referring specifically to fig. 1B, channel decoding at block 160 may be implemented in various ways. By way of example, an Inverse Discrete Fourier Transform (IDFT) is shown as being performed at block 161, and subsequent symbol demapping (also sometimes referred to as log-likelihood ratio (LLR) generation) is performed at block 162 and descrambling of the signal is performed at block 163. The descrambled signal is deinterleaved at block 164, rate dematching at block 165, and decoded (by Viterbi or Turbo decoding as shown by way of example) at block 166. A Cyclic Redundancy Check (CRC) may be performed at block 167.

The apparatus shown in fig. 1A and 1B, according to certain embodiments, is implemented as follows. Blocks 110 and 120 are implemented as respective FFT circuits that generate respective Fast Fourier Transform (FFT) series for symbols in respective ones of the received communications. Blocks 112 and 122 are respective channel estimation circuits that provide channel estimation data for the FFT bins received from one of the FFT circuits. Block 130 is a gating circuit that selects one of the respective FFT stages based on the metric received from the respective channel estimation circuit. A timing circuit is implemented with block 160 implemented as a decoding circuit and sets a decoding timing window based on a selected one of the respective FFT stages. In some implementations, the gating circuitry selects one of the respective FFT stages based on a metric that includes one or both of a Time Offset Estimate (TOE) or a signal-to-noise ratio (SNR) of the respective FFT stage. In addition, the timing circuit may set the decode timing window by setting an offset relative to a received clock synchronization signal on which a respective one of the communications is received. In some implementations, block 150 is an equalization circuit that equalizes a selected one of the respective FFT stages and a channel decoding circuit that decodes the equalized selected one of the respective FFT stages.

Fig. 2 illustrates a time-based plot 200 of a receiver and corresponding transmitter as may be implemented in accordance with the present disclosure. By way of example, receiver 210 "a" (e.g., in a car) is shown receiving respective transmissions from transmitters 220 "B" and 230 "C" (e.g., also cars) located 300 meters and 1200 meters from the receiver, respectively. Each of the transmitter and receiver are synchronized to a common clock synchronization source 202. Two OFDM symbols (N and N +1) are shown at the respective time window placement option of the receiver 210 above the actual time based position of the respective symbols as received from the transmitters 220 and 230, each of which exhibits a propagation delay (e.g., 1 μ s and 4 μ s). The first portion of each transmitted symbol includes a cyclic prefix (CP, mentioned above), as mentioned, for example, at 232, with the symbol from transmitter 230.

Four different FFT window placement options are shown for receiver 210, including "0/2" CP (RX FFT window starts at the left edge of RXCP), "1/2" CP (RX FFT window starts at the middle of RX CP), "2/2" CP (RX FFT window starts at the right edge of RX CP), and "3/2" CP (RX FFT window starts at 1 half edge of RX CP). Thus, when processing signals for respective transmitters 220 and 230, FFT window placement may be set to align with transmitter 220 to facilitate reception, and then the FFT bins from transmitter 220 may be processed accordingly. For example, the TX-RX time offset may be swept from-6 to +9 microseconds in increments of 0.5 microseconds, and decoding performance may be compared.

Fig. 3 illustrates a graph 300 of decoding performance as may be implemented in accordance with the present disclosure. In this context, performance is with respect to a signal-to-noise ratio (SNR) level required to achieve a desired level, which may correspond to a given block error rate (BLER) level (e.g., 10% BLER or 1% BLER). Performance degradation relates to an increase in SNR required to achieve a given performance (e.g., 10% BLER or 1% BLER). The performance degradation is shown on the vertical axis and the TX-RX time offset value is shown on the horizontal axis. By way of example, a plot of the start of the receiver FFT window for 1/2CP is shown, which may be relevant to the embodiment characterized in fig. 2. The FFT stage number performs well in the range of-2.5 to + 2.5. mu.s.

Fig. 4 illustrates a graph of decoding performance for respective time windows, as may be implemented in accordance with one or more embodiments. As with fig. 3, performance degradation is shown on the vertical axis and time offset is shown on the horizontal axis. Graphs 400, 410, 420, and 430 respectively show that the receiver FFT windows begin at 0/2CP, 1/2CP, 2/2CP, and 3/2 CP. Moving the FFT to the right helps to obtain larger (positive) time offset values while reducing negative time offset values.

Unless otherwise indicated, those skilled in the art will recognize that various terms as used in the specification, including the claims, are meant to have their ordinary meaning in the art. For example, this specification describes and/or illustrates aspects of the disclosure that may be used to implement the claimed disclosure by means of various circuits or circuitry, which may be shown or using terms such as blocks, modules, devices, systems, units, controllers, equalizers, decoders, estimators, and/or other circuit type depictions (e.g., reference numerals 110, 112-118, 130, 140, 150, and 160 of fig. 1A and 1B depict blocks/modules as described herein). Such circuits (circuits/circuits) are used in conjunction with other elements to illustrate how certain embodiments may be implemented in form or structure, steps, functions, operations, activities, and so forth. For example, in some of the above-described embodiments, one or more modules are discrete logic circuits or programmable logic circuits configured and arranged to carry out these operations/activities, as may be performed in the methods illustrated in the figures and described herein. In certain embodiments, such programmable circuitry is one or more computer circuits, including memory circuitry (and/or serving as configuration data to define how the programmable circuitry is executed) for storing and accessing programs to be executed as a set (or sets) of instructions, and the programmable circuitry performs associated steps, functions, operations, activities, etc. using an algorithm or process as described in connection with fig. 1A and 1B. Depending on the application, the instructions (and/or configuration data) may be configured to be implemented in logic circuits, where the instructions (whether characterized in the form of object code, firmware, or software) are stored in and accessible from memory (circuits). As another example, where the specification may refer to "a first [ structure type ]," a second [ structure type ], "etc., where [ structure type ] may be replaced with terms such as [" circuit/circuit "etc. ], the adjectives" first "and" second "are not used to imply any structural description or to provide any material meaning; rather, such adjectives are merely english antecedents to distinguish one similarly named structure from another (e.g., "a first circuit configured to convert.

Based on the foregoing discussion and illustrations, those skilled in the art will readily recognize that various modifications and changes may be made to the various embodiments without strictly following the exemplary embodiments and applications illustrated and described herein. For example, a method as illustrated in the figures may involve steps performed in various orders, with one or more aspects of embodiments herein maintained, or may involve fewer or more steps. For example, some embodiments are implemented by the portion of fig. 1A related to selecting an FFT bin number, and that portion may be coupled with other embodiments/circuits. As another example, the graphs shown in fig. 3 and 4 may be implemented in the methods and/or circuits shown in fig. 1A, 1B, and 2 or in other methods and/or circuits. Such modifications do not depart from the true spirit and scope of the various aspects of the present disclosure, including the aspects set forth in the claims.