阅读说明：本技术 一种锁相环 (Phase-locked loop ) 是由 刘术彬 阮予 韩昊霖 朱樟明 杨银堂 于 2019-08-27 设计创作，主要内容包括：本发明公开了一种锁相环,所述锁相环包括鉴频鉴相器、双模复用相位检测器、第一逻辑电路、第二逻辑电路、可编程电荷泵、环路滤波器、压控振荡器、分频器、第一延时电路、第二延时电路和锁定检测器。本发明通过双模复用相位检测器的设计,实现了锁相环的快速锁定和电荷泵的校准,相较于传统的方法,大大缩短了锁相环锁定和校准时间。(The invention discloses a phase-locked loop which comprises a phase frequency detector, a dual-mode multiplexing phase detector, a first logic circuit, a second logic circuit, a programmable charge pump, a loop filter, a voltage-controlled oscillator, a frequency divider, a first delay circuit, a second delay circuit and a lock detector. The invention realizes the fast locking of the phase-locked loop and the calibration of the charge pump through the design of the dual-mode multiplexing phase detector, and greatly shortens the locking and calibration time of the phase-locked loop compared with the traditional method.)

1. A phase locked loop, comprising: a phase frequency detector, a dual-mode multiplexing phase detector, a first logic circuit, a second logic circuit, a programmable charge pump, a loop filter, a voltage-controlled oscillator, a frequency divider, a first delay circuit, a second delay circuit, and a lock detector,

the input end of the phase frequency detector is connected with the first signal input end and the second signal input end, the output end of the phase frequency detector is connected with the input end of the dual-mode multiplexing phase detector, the output end of the dual-mode multiplexing phase detector is connected with the input end of the first logic circuit, the input end of the second logic circuit, the input end of the first delay circuit, the input end of the second delay circuit and the input end of the programmable charge pump, the output end of the first logic circuit and the output end of the second logic circuit are respectively connected with the input end of the programmable charge pump, the output end of the programmable charge pump is connected with the input end of the loop filter, the output end of the loop filter is connected with the input end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator is connected with the signal output end, the output end of the voltage-, The input of frequency divider is connected, the output of frequency divider with the input of lock detector, the input of lock detector still with the output of first delay circuit, the output of second delay circuit is connected, the output of lock detector with the input of phase frequency detector, the input of the multiplexing phase detector of bimodulus, the input of first logic circuit, the input of second logic circuit, the input of programmable charge pump, the input of loop filter is connected, the input of first delay circuit still with first signal input end is connected, the input of second delay circuit still with second signal input end is connected.

2. The phase locked loop of claim 1, wherein the dual-mode multiplexing phase detector comprises Delay circuits Delay 0-13, flip-flops DFF 0-13, Buffer1, and Buffer2, wherein,

the signal input end of the Delay circuit Delay0 is connected to the first output end of the phase frequency detector and the signal input ends of the flip-flops DFF7 to DFF13, the signal input ends of the Delay circuit Delay1 to Delay circuit Delay6 are sequentially connected to the output ends of the Delay circuit Delay0 to Delay circuit Delay5, the signal input end of the Delay circuit Delay7 is connected to the second output end of the phase frequency detector and the signal input ends of the flip-flops DFF0 to DFF6, the signal input ends of the Delay circuit Delay8 to Delay circuit Delay13 are sequentially connected to the output ends of the Delay circuit Delay7 to Delay circuit Delay12, the enable input ends of the Delay circuits Delay0 to Delay13 are further connected to the output end of the lock detector, the signal input end of the Delay circuit Delay13 to the output end of the flip-flop DFF0 to DFF 73742, clock input ends of the flip-flop DFF0 to the flip-flop DFF6 are respectively connected to a second output end of the phase frequency detector, clock input ends of the flip-flop DFF7 to the flip-flop DFF13 are respectively connected to a first output end of the phase frequency detector, first signal output ends of the flip-flop DFF0 to the flip-flop DFF5 are sequentially connected to output ends of the Delay circuit Delay1 to the Delay circuit Delay6 and first signal output ends of the flip-flop DFF1 to the flip-flop DFF6, first signal output ends of the flip-flop DFF7 to the flip-flop DFF12 are sequentially connected to output ends of the Delay circuit Delay8 to the Delay circuit Delay13 and first signal output ends of the flip-flop DFF8 to the flip-flop DFF13, a first signal output end of the flip-flop df 0 7 to the flip-flop DFF6 is further connected to the input end of the first logic circuit Delay circuit, and the first signal output end of the flip-flop DFF7 and the first signal output ends of the flip-flop DFF13 to the flip-flop DFF 3668 are further connected to the first signal output ends of the flip-flop DFF13 to the flip-flop DFF 36, The input ends of the second Delay circuits are connected, the first signal output ends of the flip-flops DFF 0-DFF 13 are all suspended, the output end of the Delay circuit Delay6 is further connected with the input end of the Buffer1, the output end of the Delay circuit Delay13 is further connected with the input end of the Buffer2, and the output end of the Buffer1 and the output end of the Buffer2 are respectively connected with the input end of the programmable charge pump.

3. The phase locked loop of claim 2 wherein the Delay circuit Delay 0-13 each include a transistor M0-M13, wherein,

a gate of the transistor M1 is connected to the output terminal of the lock detector, a source of the transistor M1 is connected to a source of the transistor M0, a gate of the transistor M0, a gate of the transistor M4, a gate of the transistor M5, a gate of the transistor M6, a drain of the transistor M2 and a gate of the transistor M2, a drain of the transistor M1 is connected to a source of the transistor M2, a drain of the transistor M3 and a gate of the transistor M3, a drain of the transistor M0 is connected to a drain of the transistor M4, a source of the transistor M5 and a source of the transistor M6, a source of the transistor M3 is connected to a source of the transistor M11, a drain of the transistor M12 and a drain of the transistor M13, a source of the transistor M4 is connected to a drain of the transistor M11, a gate of the transistor M11, The gate of the transistor M12 and the gate of the transistor M13 are connected, the drain of the transistor M5 is connected to the source of the transistor M7, the drain of the transistor M6 is connected to the source of the transistor M8, the drain of the transistor M7 is connected to the gate of the transistor M8, the source of the transistor M9 and the gate of the transistor M10, the drain of the transistor M9 is connected to the source of the transistor M12, and the drain of the transistor M10 is connected to the source of the transistor M13.

4. The phase locked loop of claim 2 wherein the phase frequency detector comprises a flip flop DFF14, a flip flop DFF15, a selector MUX, a third delay circuit, a fourth delay circuit, and a third logic circuit, wherein,

a clock input terminal of the flip-flop DFF14 is connected to the first signal input terminal, a clock input terminal of the flip-flop DFF15 is connected to the second signal input terminal, a signal input terminal of the flip-flop DFF14 and a signal input terminal of the flip-flop DFF15 are both connected to VB, a first signal output terminal of the flip-flop DFF14 and a first signal output terminal of the flip-flop DFF15 are both floating, a first signal output terminal of the flip-flop DFF14 is connected to a signal input terminal of the Delay circuit Delay0, clock input terminals of the flip-flops DFF0 to DFF6 and a first input terminal of the third Logic circuit, a first signal output terminal of the flip-flop DFF15 is connected to a signal input terminal of the Delay circuit Delay7, clock input terminals of the flip-flops DFF7 to DFF13, a second input terminal of the third Logic circuit, and an output terminal of the third Logic circuit 3 is connected to a signal input terminal of the third Delay circuit, The input end of the fourth delay circuit is connected, the output end of the third delay circuit is connected with the first signal input end of the selector MUX, the output end of the fourth delay circuit is connected with the second signal input end of the selector MUX, the enabling input end of the selector MUX is connected with the output end of the lock detector, and the output end of the selector MUX is respectively connected with the signal zero clearing end of the trigger DFF14 and the signal zero clearing end of the trigger DFF 15.

5. The phase locked loop of claim 4 wherein the delay time of the third delay circuit is T₁The delay time of the fourth delay circuit is T₂And T is₁＞T₂。

6. The phase locked loop of claim 2 wherein the programmable charge pump includes a plurality of programmable circuits, each of the programmable circuits including a pull-up circuit and a pull-down circuit, the pull-up circuit including a pull-up primary current source, a first programmable current source bank, a pull-up first switch, a pull-up second switch, and a pull-up third switch, the pull-down circuit including a pull-down primary current source, a second programmable current source bank, a pull-down first switch, a pull-down second switch, and a pull-down third switch, the first programmable current source bank including a pull-up first auxiliary current source, a pull-up second auxiliary current source, and the second programmable current source bank including a pull-down first auxiliary current source, and a pull-down second auxiliary current source, wherein,

the input end of the pull-up main current source, the input end of the pull-up first auxiliary current source, the input end of the pull-up second auxiliary current source are all connected with VDD, the output end of the pull-up second auxiliary current source is connected with one end of the pull-up third switch, the output end of the pull-up first auxiliary current source is connected with one end of the pull-up second switch, the output end of the pull-up main current source is connected with the output end of the Buffer1, one end of the pull-up first switch, the other end of the pull-up second switch, the other end of the pull-up third switch, the other end of the pull-up first switch is connected with one end of the pull-down first switch, the output end of the Buffer2 and the input end of the loop filter, the other end of the pull-down first switch is connected with the input end of the pull-down main current source and one end of the pull-down second switch, One end of the pull-down third switch is connected, the other end of the pull-down second switch is connected with the input end of the pull-down first auxiliary current source, the other end of the pull-down third switch is connected with the input end of the pull-down second auxiliary current source, and the output end of the pull-down main current source, the output end of the pull-down first auxiliary current source and the output end of the pull-down second auxiliary current source are all grounded.

7. The phase locked loop of claim 6 wherein the lock detector comprises flip-flops DFF16 through DFF19, a fourth logic circuit, a fifth delay circuit, and a sixth delay circuit, wherein,

an input end of the fifth delay circuit is connected with an output end of the frequency divider and an output end of the first delay circuit, an output end of the fifth delay circuit is connected with a signal input end of the flip-flop DFF16 and a signal input end of the flip-flop DFF17, an input end of the sixth delay circuit is connected with an output end of the second delay circuit and a clock input end of the flip-flop DFF16, an output end of the sixth delay circuit is connected with a clock input end of the flip-flop DFF17, a first signal output end of the flip-flop DFF16 and a first signal output end of the flip-flop DFF17 are both floating, a first signal output end of the flip-flop DFF16 and a first signal output end of the flip-flop DFF17 are respectively connected with an input end of the fourth logic circuit, and an output end of the fourth logic circuit is connected with a signal input end of the flip-flop DFF18 and a signal clear end of the flip-flop DFF18, the clock input of the flip-flop DFF18 is connected to the clock input of the flip-flop DFF19, a first signal output of the flip-flop DFF18 is connected to a signal input of the flip-flop DFF19, to an input of the fifth logic circuit, the input of said fifth logic circuit is further connected to a first signal output of said flip-flop DFF19, a first signal output terminal of the flip-flop DFF19 and a first signal output terminal of the flip-flop DFF19 are both floating, the output end of the fifth logic circuit is connected with the enable input end of the selector MUX, the enable input ends of the Delay circuits Delay 0-Delay 13, the enable input end of the first logic circuit, the enable input end of the second logic circuit, the pull-up third switch in the programmable charge pump, the pull-down third switch in the programmable charge pump and the input end of the loop filter.

8. Phase locked loop according to claim 7, characterized in that the clock signal at the lock detector input is T_aThe clock signals input by the clock input end of the flip-flop DFF18 and the clock input end of the flip-flop DFF17 are T_b，T_aIs T_bN is an integer greater than 0.

9. The phase locked loop of claim 8 wherein N is 32.

10. The phase-locked loop of claim 1, wherein the voltage-controlled oscillator is a class C voltage-controlled oscillator.

Background

A Phase Locked Loop (PLL) is one of the key components of a radio frequency transceiver system for wireless communication, and the excellent performance of the PLL is a precondition for ensuring high-quality communication. The phase-locked loop can effectively reduce the signal error rate, reduce the phase noise, improve the working efficiency and the like, but the phase-locked speed and the low excitation of the phase-locked loop are important problems of high-precision wireless data transmission.

At present, bandwidth switching is widely applied to a fast-locking phase-locked loop, which widens the bandwidth of a loop during phase locking, narrows the bandwidth when the loop reaches a phase-locked state, and suppresses or reduces the problem of frequency overshoot by dynamically changing the frequency division ratio of a frequency divider in a phase-locked loop circuit, but frequency adjustment is dynamically compensated, which corresponds to the frequency division ratio of the frequency divider, rather than a phase error, and when the phase-locked loop provides different frequencies, the phase error compensation is reduced. A programmable Charge Pump (CP) is used as one of the main sources of Phase-locked loop nonlinearity, where mismatch and imbalance of the CP cause excitation and spectral performance degradation, a Phase Frequency Detector (PFD) is generally used to detect a Phase error, and a set of CP currents of the programmable charge pump is generated in a locked state of the Phase-locked loop, and a micro-programmable compensation current is used to calibrate the mismatch and imbalance of the CP currents of the programmable charge pump.

The phase-locked loop has the problem of long locking and calibration time of the phase-locked loop in both the locking and phase error calibration of the phase-locked loop by the bandwidth switching method and the locking and phase error calibration of the phase-locked loop by the BBPD method.

Disclosure of Invention

In order to solve the above problems in the prior art, the present invention provides a phase-locked loop.

An embodiment of the present invention provides a phase-locked loop, including:

a phase frequency detector, a dual-mode multiplexing phase detector, a first logic circuit, a second logic circuit, a programmable charge pump, a loop filter, a voltage-controlled oscillator, a frequency divider, a first delay circuit, a second delay circuit, and a lock detector,

the input end of the phase frequency detector is connected with the first signal input end and the second signal input end, the output end of the phase frequency detector is connected with the input end of the dual-mode multiplexing phase detector, the output end of the dual-mode multiplexing phase detector is connected with the input end of the first logic circuit, the input end of the second logic circuit, the input end of the first delay circuit, the input end of the second delay circuit and the input end of the programmable charge pump, the output end of the first logic circuit and the output end of the second logic circuit are respectively connected with the input end of the programmable charge pump, the output end of the programmable charge pump is connected with the input end of the loop filter, the output end of the loop filter is connected with the input end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator is connected with the signal output end, the output end of the voltage-, The input of frequency divider is connected, the output of frequency divider with the input of lock detector, the input of lock detector still with the output of first delay circuit, the output of second delay circuit is connected, the output of lock detector with the input of phase frequency detector, the input of the multiplexing phase detector of bimodulus, the input of first logic circuit, the input of second logic circuit, the input of programmable charge pump, the input of loop filter is connected, the input of first delay circuit still with first signal input end is connected, the input of second delay circuit still with second signal input end is connected.

In one embodiment of the present invention, the dual-mode multiplexing phase detector comprises Delay circuits Delay 0-13, flip-flops DFF 0-13, Buffer buffers 1 and Buffer buffers 2, wherein,

the signal input end of the Delay circuit Delay0 is connected to the first output end of the phase frequency detector and the signal input ends of the flip-flops DFF7 to DFF13, the signal input ends of the Delay circuit Delay1 to Delay circuit Delay6 are sequentially connected to the output ends of the Delay circuit Delay0 to Delay circuit Delay5, the signal input end of the Delay circuit Delay7 is connected to the second output end of the phase frequency detector and the signal input ends of the flip-flops DFF0 to DFF6, the signal input ends of the Delay circuit Delay8 to Delay circuit Delay13 are sequentially connected to the output ends of the Delay circuit Delay7 to Delay circuit Delay12, the enable input ends of the Delay circuits Delay0 to Delay13 are further connected to the output end of the lock detector, the signal input end of the Delay circuit Delay13 to the output end of the flip-flop DFF0 to DFF 73742, clock input ends of the flip-flop DFF0 to the flip-flop DFF6 are respectively connected to a second output end of the phase frequency detector, clock input ends of the flip-flop DFF7 to the flip-flop DFF13 are respectively connected to a first output end of the phase frequency detector, first signal output ends of the flip-flop DFF0 to the flip-flop DFF5 are sequentially connected to output ends of the Delay circuit Delay1 to the Delay circuit Delay6 and first signal output ends of the flip-flop DFF1 to the flip-flop DFF6, first signal output ends of the flip-flop DFF7 to the flip-flop DFF12 are sequentially connected to output ends of the Delay circuit Delay8 to the Delay circuit Delay13 and first signal output ends of the flip-flop DFF8 to the flip-flop DFF13, a first signal output end of the flip-flop df 0 7 to the flip-flop DFF6 is further connected to the input end of the first logic circuit Delay circuit, and the first signal output end of the flip-flop DFF7 and the first signal output ends of the flip-flop DFF13 to the flip-flop DFF 3668 are further connected to the first signal output ends of the flip-flop DFF13 to the flip-flop DFF 36, The input ends of the second Delay circuits are connected, the first signal output ends of the flip-flops DFF 0-DFF 13 are all suspended, the output end of the Delay circuit Delay6 is further connected with the input end of the Buffer1, the output end of the Delay circuit Delay13 is further connected with the input end of the Buffer2, and the output end of the Buffer1 and the output end of the Buffer2 are respectively connected with the input end of the programmable charge pump.

In one embodiment of the present invention, each of the Delay circuits Delay 0-Delay 13 includes a transistor M0-transistor M13, wherein,

a gate of the transistor M1 is connected to the output terminal of the lock detector, a source of the transistor M1 is connected to a source of the transistor M0, a gate of the transistor M0, a gate of the transistor M4, a gate of the transistor M5, a gate of the transistor M6, a drain of the transistor M2 and a gate of the transistor M2, a drain of the transistor M1 is connected to a source of the transistor M2, a drain of the transistor M3 and a gate of the transistor M3, a drain of the transistor M0 is connected to a drain of the transistor M4, a source of the transistor M5 and a source of the transistor M6, a source of the transistor M3 is connected to a source of the transistor M11, a drain of the transistor M12 and a drain of the transistor M13, a source of the transistor M4 is connected to a drain of the transistor M11, a gate of the transistor M11, The gate of the transistor M12 and the gate of the transistor M13 are connected, the drain of the transistor M5 is connected to the source of the transistor M7, the drain of the transistor M6 is connected to the source of the transistor M8, the drain of the transistor M7 is connected to the gate of the transistor M8, the source of the transistor M9 and the gate of the transistor M10, the drain of the transistor M9 is connected to the source of the transistor M12, and the drain of the transistor M10 is connected to the source of the transistor M13.

In one embodiment of the present invention, the phase frequency detector includes a flip-flop DFF14, a flip-flop DFF15, a selector MUX, a third delay circuit, a fourth delay circuit, and a third logic circuit, wherein,

a clock input terminal of the flip-flop DFF14 is connected to the first signal input terminal, a clock input terminal of the flip-flop DFF15 is connected to the second signal input terminal, a signal input terminal of the flip-flop DFF14 and a signal input terminal of the flip-flop DFF15 are both connected to VB, a first signal output terminal of the flip-flop DFF14 and a first signal output terminal of the flip-flop DFF15 are both floating, a first signal output terminal of the flip-flop DFF14 is connected to a signal input terminal of the Delay circuit Delay0, clock input terminals of the flip-flops DFF0 to DFF6 and a first input terminal of the third Logic circuit, a first signal output terminal of the flip-flop DFF15 is connected to a signal input terminal of the Delay circuit Delay7, clock input terminals of the flip-flops DFF7 to DFF13, a second input terminal of the third Logic circuit, and an output terminal of the third Logic circuit 3 is connected to a signal input terminal of the third Delay circuit, The input end of the fourth delay circuit is connected, the output end of the third delay circuit is connected with the first signal input end of the selector MUX, the output end of the fourth delay circuit is connected with the second signal input end of the selector MUX, the enabling input end of the selector MUX is connected with the output end of the lock detector, and the output end of the selector MUX is respectively connected with the signal zero clearing end of the trigger DFF14 and the signal zero clearing end of the trigger DFF 15.

In an embodiment of the present invention, the delay time of the third delay circuit is T₁The delay time of the fourth delay circuit is T₂And T is₁＞T₂。

In one embodiment of the invention, the programmable charge pump comprises a plurality of programmable circuits, each programmable circuit comprises a pull-up circuit and a pull-down circuit, the pull-up circuit comprises a pull-up main current source, a first programmable current source group, a pull-up first switch, a pull-up second switch and a pull-up third switch, the pull-down circuit comprises a pull-down main current source, a second programmable current source group, a pull-down first switch, a pull-down second switch and a pull-down third switch, the first programmable current source group comprises a pull-up first auxiliary current source and a pull-up second auxiliary current source, the second programmable current source group comprises a pull-down first auxiliary current source and a pull-down second auxiliary current source, wherein,

the input end of the pull-up main current source, the input end of the pull-up first auxiliary current source, the input end of the pull-up second auxiliary current source are all connected with VDD, the output end of the pull-up second auxiliary current source is connected with one end of the pull-up third switch, the output end of the pull-up first auxiliary current source is connected with one end of the pull-up second switch, the output end of the pull-up main current source is connected with the output end of the Buffer1, one end of the pull-up first switch, the other end of the pull-up second switch, the other end of the pull-up third switch, the other end of the pull-up first switch is connected with one end of the pull-down first switch, the output end of the Buffer2 and the input end of the loop filter, the other end of the pull-down first switch is connected with the input end of the pull-down main current source and one end of the pull-down second switch, One end of the pull-down third switch is connected, the other end of the pull-down second switch is connected with the input end of the pull-down first auxiliary current source, the other end of the pull-down third switch is connected with the input end of the pull-down second auxiliary current source, and the output end of the pull-down main current source, the output end of the pull-down first auxiliary current source and the output end of the pull-down second auxiliary current source are all grounded.

In one embodiment of the present invention, the lock detector includes flip-flops DFF16 through DFF19, a fourth logic circuit, a fifth delay circuit, and a sixth delay circuit, wherein,

an input end of the fifth delay circuit is connected with an output end of the frequency divider and an output end of the first delay circuit, an output end of the fifth delay circuit is connected with a signal input end of the flip-flop DFF16 and a signal input end of the flip-flop DFF17, an input end of the sixth delay circuit is connected with an output end of the second delay circuit and a clock input end of the flip-flop DFF16, an output end of the sixth delay circuit is connected with a clock input end of the flip-flop DFF17, a first signal output end of the flip-flop DFF16 and a first signal output end of the flip-flop DFF17 are both floating, a first signal output end of the flip-flop DFF16 and a first signal output end of the flip-flop DFF17 are respectively connected with an input end of the fourth logic circuit, and an output end of the fourth logic circuit is connected with a signal input end of the flip-flop DFF18 and a signal clear end of the flip-flop DFF18, the clock input of the flip-flop DFF18 is connected to the clock input of the flip-flop DFF19, a first signal output of the flip-flop DFF18 is connected to a signal input of the flip-flop DFF19, to an input of the fifth logic circuit, the input of said fifth logic circuit is further connected to a first signal output of said flip-flop DFF19, a first signal output terminal of the flip-flop DFF19 and a first signal output terminal of the flip-flop DFF19 are both floating, the output end of the fifth logic circuit is connected with the enable input end of the selector MUX, the enable input ends of the Delay circuits Delay 0-Delay 13, the enable input end of the first logic circuit, the enable input end of the second logic circuit, the pull-up third switch in the programmable charge pump, the pull-down third switch in the programmable charge pump and the input end of the loop filter.

In one embodiment of the invention, the lock detector input clock signal is T_aThe clock signals input by the clock input end of the flip-flop DFF18 and the clock input end of the flip-flop DFF17 are T_b，T_aIs T_bN is an integer greater than 0.

In one embodiment of the present invention, the value of N is 32.

In one embodiment of the invention, the voltage controlled oscillator is a class C voltage controlled oscillator.

Compared with the prior art, the invention has the beneficial effects that:

the invention realizes the fast locking of the phase-locked loop and the calibration of the charge pump through the design of the dual-mode multiplexing phase detector, and greatly shortens the locking and calibration time of the phase-locked loop compared with the traditional method.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

Fig. 1 is a schematic circuit diagram of a phase-locked loop according to an embodiment of the present invention;

fig. 2 is a schematic circuit diagram of another phase-locked loop according to an embodiment of the present invention;

fig. 3 is a schematic circuit diagram of a dual-mode multiplexing phase detector in a phase-locked loop according to an embodiment of the present invention;

fig. 4 is a schematic diagram illustrating a signal operation principle of a dual-mode multiplexing phase detector in a phase-locked loop according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a circuit structure of a delay circuit in a dual-mode multiplexing phase detector according to an embodiment of the present invention;

fig. 6 is a schematic circuit diagram of a phase frequency detector in a phase locked loop according to an embodiment of the present invention;

fig. 7 is a schematic circuit diagram of a lock detector in a phase-locked loop according to an embodiment of the present invention;

fig. 8 is a schematic diagram illustrating a signal operation principle of a lock detector in a phase-locked loop according to an embodiment of the present invention;

fig. 9 is a schematic circuit structure diagram of a voltage controlled oscillator in a phase-locked loop according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.