阅读说明：本技术 一种提高mcu总线效率的方法、智能终端、存储介质及芯片 (Method for improving MCU bus efficiency, intelligent terminal, storage medium and chip ) 是由 杨力 王翔 刘吉平 于 2019-09-20 设计创作，主要内容包括：本发明所提供的一种提高MCU总线效率的方法、智能终端、存储介质及芯片,包括：系统寄存器获取预设指令,并根据所述预设指令执行操作如下：读取目标寄存器中的第一数值；将所述第一数值修改为第二数值；将所述第二数值写入所述目标寄存器。本发明通过设置预设指令,处理器获取预设指令,根据预设指令读取目标寄存器中的第一数值,并将所述第一数值载入系统寄存器中进行修改,修改成第二数值,再将修改之后的数值写回到目标寄存器中。本发明实现“读-修改-写”的过程只需要获取一次预设指令就可以实现,并不需要多次获取指令,因此,节省了多次获取指令所产生的时间间隔,提高了MCU总线的执行效率。(The invention provides a method for improving MCU bus efficiency, an intelligent terminal, a storage medium and a chip, comprising the following steps: the system register acquires a preset instruction, and executes the following operations according to the preset instruction: reading a first value in a target register; modifying the first value to a second value; writing the second value to the target register. According to the invention, the processor acquires the preset instruction by setting the preset instruction, reads a first numerical value in the target register according to the preset instruction, loads the first numerical value into the system register to be modified, modifies the first numerical value into a second numerical value, and writes the modified numerical value back into the target register. The method can realize the process of reading, modifying and writing only by acquiring the preset instruction once and does not need to acquire the instruction for multiple times, thereby saving the time interval generated by acquiring the instruction for multiple times and improving the execution efficiency of the MCU bus.)

1. A method for improving MCU bus efficiency, comprising:

the system register acquires a preset instruction, and executes the following operations according to the preset instruction:

reading a first value in a target register;

modifying the first value to a second value;

writing the second value to the target register.

2. The method for improving the efficiency of the MCU bus according to claim 1, further comprising:

when all values in the target register are modified, all values are modified in the target register and stored.

3. The method according to claim 1, wherein the obtaining of the preset instruction by the system register specifically comprises:

when partial values in the target register are modified, the system register acquires a preset instruction.

4. The method of claim 1, wherein the predetermined instruction is stored in a system register.

5. The method according to claim 1, wherein the preset command is a machine command.

6. The method of claim 1, wherein writing the second value to the destination register specifically comprises:

and the system register initiates a bus write request, and the target register receives the write request and writes the second numerical value into the target register.

7. The method of claim 1, wherein the target register is a peripheral register.

8. An intelligent terminal, comprising a processor and a memory connected to the processor, wherein the memory stores a program for improving the MCU bus efficiency, and when the program for improving the MCU bus efficiency is executed, the method for improving the MCU bus efficiency according to any one of claims 1 to 7 can be implemented.

9. A storage medium storing a program for improving MCU bus efficiency, wherein the program can be executed to implement the method for improving MCU bus efficiency according to any one of claims 1-7.

10. A chip, characterized in that it can be executed for implementing a method for improving MCU bus efficiency according to any of claims 1-7.

Technical Field

The invention relates to the technical field of MCU, in particular to a method for improving the efficiency of an MCU bus, an intelligent terminal, a storage medium and a chip.

Background

A Micro Control Unit (MCU), also called a Single Chip Microcomputer (Single Chip Microcomputer) or a Single Chip Microcomputer (MCU), is a Chip-level computer formed by appropriately reducing the frequency and specification of a Central Processing Unit (CPU) and integrating peripheral interfaces such as a memory, a counter (Timer), a USB, an a/D converter, a UART, a PLC, a DMA, etc., and even an LCD driving circuit on a Single Chip, and performing different combination control for different applications.

When the MCU runs, the target register is directly subjected to read-modify-write operation, and the read-modify-write operation needs to acquire instructions for execution for multiple times. Time intervals exist in the process of obtaining the instructions for multiple times, so that the problem that the efficiency of executing writing and reading operations by the MCU is low is caused.

Therefore, the prior art has defects and needs to be improved and developed.

Disclosure of Invention

The technical problem to be solved by the present invention is to provide a method, an intelligent terminal, a storage medium and a chip for improving the efficiency of an MCU bus, aiming at solving the problem that the MCU execution efficiency is low because the MCU bus needs to be acquired multiple times to execute the read-modify-write operation when the MCU bus is used in the prior art.

The technical scheme adopted by the invention for solving the technical problem is as follows:

a method of improving MCU bus efficiency, comprising:

the system register acquires a preset instruction, and executes the following operations according to the preset instruction:

reading a first value in a target register;

modifying the first value to a second value;

writing the second value to the target register.

Further, the method for improving the efficiency of the MCU bus further comprises:

when all values in the target register are modified, all values are modified in the target register and stored.

Further, the acquiring, by the processor, the preset instruction specifically includes:

and when part of numerical values in the target register are modified, acquiring a preset instruction, and calling a system register according to the preset instruction.

Further, the preset instruction is stored in a system register.

Further, the preset instruction is a machine instruction.

Further, writing the second value into the target register specifically includes:

and the system register initiates a bus write request, and the target register receives the write request and writes the second numerical value into the target register.

Further, the target register is a peripheral register.

The invention also provides an intelligent terminal, which comprises a processor and a memory connected with the processor, wherein the memory stores a program for improving the MCU bus efficiency, and the method for improving the MCU bus efficiency can be realized when the program for improving the MCU bus efficiency is executed.

The present invention also provides a storage medium, wherein the storage medium stores a program for improving the MCU bus efficiency, and the program for improving the MCU bus efficiency can be executed to implement the method for improving the MCU bus efficiency as described above.

The invention also provides a chip, wherein the chip can be executed to realize the method for improving the efficiency of the MCU bus.

The invention provides a method for improving MCU bus efficiency, an intelligent terminal, a storage medium and a chip, comprising the following steps: the system register acquires a preset instruction, and executes the following operations according to the preset instruction: reading a first value in a target register; modifying the first value to a second value; writing the second value to the target register. According to the invention, the processor acquires the preset instruction by setting the preset instruction, reads a first numerical value in the target register according to the preset instruction, loads the first numerical value into the system register to be modified, modifies the first numerical value into a second numerical value, and writes the modified numerical value back into the target register. The method can realize the process of reading, modifying and writing only by acquiring the preset instruction once and does not need to acquire the instruction for multiple times, thereby saving the time interval generated by acquiring the instruction for multiple times and improving the execution efficiency of the MCU bus.

Drawings

FIG. 1 is a flow chart of a preferred embodiment of a method for improving MCU bus efficiency according to the present invention;

FIG. 2 is a functional diagram of a preferred embodiment of the present invention for performing a write-through process in an MCU;

fig. 3 is a functional block diagram of a preferred embodiment of the intelligent terminal of the present invention.

Detailed Description

The invention provides a method for improving MCU bus efficiency, an intelligent terminal, a storage medium and a chip, and in order to make the purpose, technical scheme and effect of the invention clearer and clearer, the invention is further described in detail by referring to the attached drawings and taking examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Because the application range of the MCU is wider, the C language is taken as an example for illustration in the full text of the invention, and the scope of the invention is not limited to the application of the C language in the MCU.

During the use process of the existing MCU, the implemented operation is as follows:

after the data at an address in the target register is read, the read data is modified, and then the new data formed after modification is written into the address.

The C language code enumeration for reading and writing by MCU is as follows:

*(unsigned int*)0×40021004|＝0×03；

*(unsigned int*)0×40021004&＝0×fffffffc；

the process of reading and writing is illustrated here:

for example, the function of the C language code 0 × 40021004|, 0 × 03, is to set the register of the bus address 0 × 40021004 to 1 lower by 2, and the other bits of the address register (target register) are left unchanged.

The compiled assembler instructions on the ARM Cortex-M0 instruction set may be:

wherein:

the "LDR r0, [ r0, #4 ]" instruction reads the value of the target 0 x 40021004 address register to save to r 0;

the "MOVS r1, # 3" and "ORRS r0, r0, r 1" instructions complete the low 2 position bit 1 to r 0;

"LDR r1, [ pc, #4 ]; the [0 × 8000830] ═ 0 × 40021000 "instruction completes the fetch target address;

the "STR r0, [ r1, #4 ]" instruction writes the value of r0 to the 0 × 40021004 address completing the modification of the 0 × 40021004 address register.

The whole assembly process is shown in fig. 2, and it can be seen that a plurality of assembly instructions are needed to complete a C language operation of "read-modify-write", and thus, multiple instruction fetching operations are needed. For the same address (addr), the operation of fetching the instruction twice, the first reading, the second writing, and the existence of the instruction fetching twice have a certain time interval (delay), and the existence of the time interval affects the execution efficiency of the code. Similarly, when the AHB bus performs a write operation and a read operation, a delay phenomenon also occurs accordingly.

In order to solve the problem of low operating efficiency of the MCU bus, the present invention provides a method for improving the efficiency of the MCU bus, as shown in fig. 1:

and S1, the system register acquires a preset instruction and executes operation according to the preset instruction.

Machine code stored in system memory is executed in system registers while the CPU is running. The system register is an existing register, is a component in the central processing unit and is used for temporarily storing instructions, data and addresses. In the system register, the "read-modify-write" instruction is used to modify the value read from the target register.

The target register is a register of the system peripheral relative to the system register, when a program compiler compiles the target code, a function formed by the target code represents the number of bits to be modified in the register of the peripheral, the target code is compiled into machine code capable of executing a read-modify-write instruction and is stored in a system memory, and the system has a read-modify-write function. The "read-modify-write" function is automatically performed when the CPU reads the value in the target register.

And S2, reading the first numerical value in the target register.

And S3, modifying the first value into a second value.

When the CPU obtains a preset instruction, the preset instruction is used for controlling the CPU to execute a read-modify-write function. The CPU reads the first numerical value in the target register, writes the first numerical value into the system register for modification, and modifies the first numerical value into a second numerical value. The first numerical value and the second numerical value in the present invention are not specific numerical values and may be any data, and the present invention does not limit the first numerical value and the second numerical value, and any data that can be modified in the system register may be used as a modification of the first numerical value and the second numerical value in the present invention. The first and second values may be address data. And S4, writing the second numerical value into the target register.

Specifically, the system register initiates a bus write request, and the target register receives the write request and writes the second value into the target register.

Before the method for improving the efficiency of the MCU bus is realized, the technical developers need to carry out the early development work, and the specific process is as follows:

and A100, adding a preset instruction in a compiler to form a target compiler.

The compiler is an existing compiler and supports compiling code into machine instructions. A preset instruction is added in the existing compiler, and the preset instruction refers to a new type of instruction, and the instruction supports the read-modify-write operation, namely the instruction supported by the CPU. Here, this new class of instructions is embodied in the form of RMWxx, where xx is listed below:

xx may be: OR (logical OR operation), AND (logical AND operation), ADD (arithmetic addition), SUB (arithmetic subtraction operation), AND the like. The preset instruction is set by a developer according to the requirement in a self-defined manner, so the preset instruction is not limited to the examples, and any instruction form capable of realizing the operation process only by acquiring one instruction in the process of reading, modifying and writing can be used in the technical scheme of the invention.

A200, the target compiler acquires a target code, compiles the target code into a machine code, and loads the machine code into a system memory.

The object code may be a high-level language code, which is compiled in a compiler into corresponding instructions, data and addresses, which are represented by machine code. The machine code is binary instructions and can support the read-modify-write operation of the CPU; the system memory is used to store the machine code, and when the system runs, the system can automatically execute the 'read-modify-write' instruction represented by the machine code.

And then, forming the MCU, and when the MCU is in the operation process, executing the following operations:

firstly, the processor carries out pre-judgment, and when all the numerical values in the target register are modified, all the numerical values are modified and stored in the target register.

When a modification is made to a portion of the values in the target register, the following step a300 is performed.

And A300, the CPU reads a corresponding preset instruction in the machine code and executes the preset instruction.

Specifically, the CPU reads the machine code, acquires a "read-modify-write" instruction supported by the CPU in the register code, and executes the "read-modify-write" instruction, where the preset instruction is the "read-modify-write" instruction.

The step a300 performs the operations of: and reading the value in the target register, modifying the value, and writing the modified value back to the target register to complete the read-modify-write operation.

In order to make the technical solution of the present invention more intuitive, the description is made here. During the use of the MCU in the present invention, the following operations are implemented, which are still exemplified by C language code:

after the preset instruction is added, only by taking the example that the preset instruction includes RMWOR as an example, the assembly instruction of C language code (signaled int) 0 × 40021004| ═ 0 × 03 may become:

wherein:

"LDR r0, [ pc, #12 ]; the [0 × 8000830] ═ 0 × 40021000 "instruction stores the target address in r 0;

the "LDR r2, [ r0, #4 ]" instruction reads the value of the target register to r 2;

"MOVS r1, # 3" and "RMWOR r2, r2, r 1" complete assignment of the lower two bits of r2 to 1.

After the "RMWOR r2, r2 and r 1" instruction is executed, the CPU automatically initiates an AHB bus write operation request to write the value of r2 to a general register with the value of r0 as the target address. The r0, r1, r2, etc. are names of general purpose registers that are stored in the MAC and used when the CPU executes a program.

Compared with the prior art, the technical scheme of the invention reduces the execution operation of the two instructions, namely the operation of acquiring the instructions twice, saves the time interval between the two instruction acquisition times, and greatly improves the efficiency of the MCU bus.

The invention also provides an intelligent terminal, as shown in fig. 3, which includes a processor 10 and a memory 20 connected to the processor, where the memory 20 stores a program for improving the MCU bus efficiency, and when the program for improving the MCU bus efficiency is executed, the method for improving the MCU bus efficiency can be implemented.

The present invention also provides a storage medium, wherein the storage medium stores a program for improving the MCU bus efficiency, and the program for improving the MCU bus efficiency can be executed to implement the method for improving the MCU bus efficiency as described above.

The invention also provides a chip, wherein the chip can be executed to realize the method for improving the efficiency of the MCU bus.

In summary, the method, the intelligent terminal, the storage medium and the chip for improving the MCU bus efficiency disclosed in the present invention include: the method comprises the steps that a processor obtains a preset instruction, reads a first numerical value in a target register into a system register, and modifies the first numerical value into a second numerical value in the system register; writing the second value into the target register. And storing the machine code in a system memory, wherein when the system runs, a CPU (central processing unit) can automatically read a corresponding preset instruction in the machine code, and the preset instruction can execute read-write operation. When a CPU performs read-write operation, a first numerical value in a target register is read in sequence, the first numerical value is written into a system register, the first numerical value is modified into a second numerical value in the system register, and then the second numerical value is written back to the target register to replace the first numerical value, so that the read-write operation is realized. Compared with the existing read-write operation, the method avoids the problem that the operation of 'read-modify-write' is completed once only by acquiring the instruction for multiple times, reduces the execution process of the instruction, saves the time interval existing between the instructions acquired for multiple times, and achieves the purpose of improving the efficiency of the MCU bus.

It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.