阅读说明：本技术 基于同或异或电路反馈的全加器 (Full adder based on exclusive nor circuit feedback ) 是由 韩金亮 俞海珍 张跃军 于 2019-09-26 设计创作，主要内容包括：本发明公开了一种基于同或异或电路反馈的全加器,包括同或异或电路、求和电路、进位电路、第一反相器和第二反相器,同或异或电路包括第一MOS管、第二MOS管、第三MOS管、第四MOS管、第五MOS管、第六MOS管、第七MOS管、第八MOS管、第九MOS管、第十MOS管、第十一MOS管和第十二MOS管,求和电路包括第十三MOS管、第十四MOS管、第十五MOS管和第十六MOS管,进位电路包括第十七MOS管、第十八MOS管、第十九MOS管、第二十MOS管和第三反相器；优点是在具有全摆幅和较低的功耗的基础上,延时较小,运行速度较快。(The invention discloses a full adder based on the feedback of an exclusive-or circuit, which comprises an exclusive-or circuit, a summing circuit, a carry circuit, a first phase inverter and a second phase inverter, wherein the exclusive-or circuit comprises a first MOS (metal oxide semiconductor) transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor and a twelfth MOS transistor; the advantages are that the delay is small and the running speed is fast on the basis of having full swing and low power consumption.)

1. A full adder based on feedback of an exclusive OR circuit comprises an exclusive OR circuit, a summing circuit and a carry circuit, wherein the exclusive OR circuit is provided with a first input end, a second input end, a third input end, a first output end used for outputting an exclusive OR logic value and a second output end used for outputting an exclusive OR logic value, the summing circuit is provided with a first input end, a second input end, a third input end and an output end, the carry circuit is provided with a first input end, a second input end, a third input end, a fourth input end, an output end and an inverted output end, the first input end of the exclusive OR circuit is the first input end of the full adder and is used for connecting a first addend, the second input end of the exclusive OR circuit is the second input end of the full adder and is used for connecting a second addend, and the first output end of the exclusive OR circuit is respectively connected with the second input end of the summing circuit and the second output end of the carry circuit The carry circuit comprises a sum circuit, a carry circuit and a carry circuit, wherein the sum circuit comprises a first input end, a second input end, a third input end and a second input end, the first input end of the sum circuit is the carry signal input end of the full adder and is used for accessing a carry signal output at a low position, the output end of the sum circuit is the output end of the full adder and is used for outputting a sum signal, the output end of the carry circuit is the high-position carry signal output end of the full adder and is used for outputting a carry signal to a high position, the carry circuit is characterized in that the full adder also comprises a first inverter and a second inverter, the input end of the first inverter is connected with the first input end of the sum circuit, and the output end of the first inverter is respectively connected with the third input end of the sum circuit and the third input end of the carry circuit, the input end of the second inverter is connected with the first input end of the summation circuit, and the output end of the second inverter is connected with the fourth input end of the carry circuit;

the exclusive-nor circuit comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube and a twelfth MOS tube. The first PMOS transistor, the second MOS transistor, the fourth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, and the eleventh MOS transistor are all P-type MOS transistors, and the third MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, and the twelfth MOS transistor are all N-type MOS transistors; the source electrode of the first MOS transistor, the gate electrode of the second MOS transistor, the source electrode of the fifth MOS transistor, the gate electrode of the sixth MOS transistor, the gate electrode of the seventh MOS transistor and the gate electrode of the ninth MOS transistor are connected, and the connection end thereof is the first input end of the exclusive or circuit, the gate electrode of the first MOS transistor, the source electrode of the second MOS transistor, the source electrode of the third MOS transistor, the source electrode of the fourth MOS transistor, the gate electrode of the fifth MOS transistor, the source electrode of the sixth MOS transistor, the gate electrode of the eighth MOS transistor and the gate electrode of the tenth MOS transistor are connected, and the connection end thereof is the second input end of the exclusive or circuit, the drain electrode of the first MOS transistor, the drain electrode of the second MOS transistor, the drain electrode of the third MOS transistor, the drain electrode of the seventh MOS transistor, the gate electrode of the eleventh MOS transistor and the drain electrode of the twelfth MOS transistor are connected, and the connection end thereof is the second input end of the exclusive or circuit A gate of the third MOS transistor is connected to a gate of the fourth MOS transistor, a connection end of the third MOS transistor is a third input end of the exclusive nor circuit, a drain of the fourth MOS transistor, a drain of the fifth MOS transistor, a drain of the sixth MOS transistor, a drain of the tenth MOS transistor, a drain of the eleventh MOS transistor is connected to a gate of the twelfth MOS transistor, a connection end of the fifth MOS transistor is a second output end of the exclusive nor circuit, a source of the seventh MOS transistor is connected to a drain of the eighth MOS transistor, a source of the eighth MOS transistor is grounded, a source of the ninth MOS transistor and a source of the eleventh MOS transistor are both connected to a power supply, a drain of the ninth MOS transistor is connected to a source of the tenth MOS transistor, and a source of the twelfth MOS transistor is grounded;

the summing circuit comprises a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube and a sixteenth MOS tube; the thirteenth MOS tube and the sixteenth MOS tube are both P-type MOS tubes, and the fourteenth MOS tube and the fifteenth MOS tube are both N-type MOS tubes; a drain of the thirteenth MOS transistor, a drain of the fourteenth MOS transistor, a gate of the fifteenth MOS transistor and a gate of the sixteenth MOS transistor are connected, and connection ends thereof are first input ends of the summing circuit, a gate of the thirteenth MOS transistor and a drain of the sixteenth MOS transistor are connected, and connection ends thereof are second input ends of the summing circuit, a source of the thirteenth MOS transistor, a source of the fourteenth MOS transistor, a source of the fifteenth MOS transistor and a source of the sixteenth MOS transistor are connected, and connection ends thereof are output ends of the summing circuit, a gate of the fourteenth MOS transistor and a drain of the fifteenth MOS transistor are connected, and connection ends thereof are third input ends of the summing circuit;

the carry circuit comprises a seventeenth MOS tube, an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube and a third phase inverter, wherein the seventeenth MOS tube and the nineteenth MOS tube are both P-type MOS tubes, and the eighteenth MOS tube and the twentieth MOS tube are both N-type MOS tubes; the gate of the seventeenth MOS transistor is connected to the gate of the twentieth MOS transistor, and the connection end of the seventeenth MOS transistor is the first input end of the carry circuit, the source of the seventeenth MOS transistor, the source of the eighteenth MOS transistor, the source of the nineteenth MOS transistor, the source of the twentieth MOS transistor and the input end of the third inverter are connected, and the connection end of the twenty-first MOS transistor is the reverse output end of the carry circuit, the gate of the eighteenth MOS transistor and the gate of the nineteenth MOS transistor are connected, and the connection end of the nineteenth MOS transistor is the second input end of the carry circuit, the drain of the seventeenth MOS transistor and the drain of the eighteenth MOS transistor are connected, and the connection end of the seventeenth MOS transistor and the drain of the nineteenth MOS transistor is the third input end of the carry circuit, the drain of the nineteenth MOS transistor and the drain of the twentieth MOS transistor are connected, and the connection end of the nineteenth MOS, the output end of the third phase inverter is the output end of the carry circuit.

2. A full adder based on the feedback of an exclusive-OR gate circuit as claimed in claim 1, further comprising a summation self-checking circuit and a carry self-checking circuit, said summation self-checking circuit and said carry self-checking circuit having a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a fifth input terminal and an output terminal, respectively, said first input terminal of said summation self-checking circuit being connected to said first input terminal of said summation circuit, said second input terminal of said summation self-checking circuit being connected to said output terminal of said second inverter, said third input terminal of said summation self-checking circuit being connected to said second input terminal of said summation circuit, said fourth input terminal of said summation self-checking circuit being connected to said third input terminal of said summation circuit, said fifth input terminal of said summation self-checking circuit being connected to said output terminal of said summation circuit, the first input end of the carry self-checking circuit is connected with the output end of the carry circuit, the second input end of the carry self-checking circuit is connected with the inverted output end of the carry circuit, the third input end of the carry self-checking circuit is connected with the first input end of the summation circuit, the fourth input end of the carry self-checking circuit is connected with the first input end of the exclusive OR circuit, and the fifth input end of the carry self-checking circuit is connected with the second input end of the exclusive OR circuit;

the summation self-detection circuit comprises a twenty-first MOS tube, a twenty-second MOS tube, a twenty-third MOS tube, a twenty-fourth MOS tube, a twenty-fifth MOS tube, a twenty-sixth MOS tube, a twenty-seventh MOS tube and a twenty-eighth MOS tube, wherein the twenty-first MOS tube, the twenty-third MOS tube, the twenty-fifth MOS tube and the twenty-seventh MOS tube are P-type MOS tubes, the twenty-second twelve MOS tube, the twenty-fourth MOS tube, the twenty-sixth MOS tube and the twenty-eighth MOS tube are N-type MOS tubes, the source electrode of the twenty-first MOS tube is connected with the gate electrode of the twenty-second twelve MOS tube, the connecting end of the twenty-second MOS tube is the second input end of the summation self-detection circuit, the gate electrode of the twenty-first MOS tube, the gate electrode of the twenty-second MOS tube, the source electrode of the twenty-third MOS tube is connected with the source electrode of the twenty-fourth MOS tube, and the connecting end of the twenty-fifth input end of the summation self-detection circuit, the drain of the twenty-first MOS transistor, the drain of the twenty-second MOS transistor, the drain of the twenty-third MOS transistor, the drain of the twenty-fourth MOS transistor, the drain of the twenty-fifth MOS transistor, the drain of the twenty-sixth MOS transistor, the gate of the twenty-seventh MOS transistor and the gate of the twenty-eighteen MOS transistor are connected, the source of the twenty-second MOS transistor and the gate of the twenty-fourth MOS transistor are connected and the connection end thereof is the first input end of the summation self-test circuit, the gate of the twenty-fifth MOS transistor and the source of the twenty-seventh MOS transistor are connected and the connection end thereof is the third input end of the summation self-test circuit, the source of the twenty-fifth MOS transistor, the source of the twenty-sixth MOS transistor, the drain of the twenty-seventh MOS transistor and the drain of the twenty-eighteen MOS transistor are connected and the connection end thereof is the output end of the summation self-test circuit, the grid electrode of the twenty-sixth MOS tube is connected with the source electrode of the twenty-eighteen MOS tube, and the connecting end of the grid electrode of the twenty-sixth MOS tube is the fourth input end of the summation self-detection circuit;

the carry self-checking circuit comprises a twenty-ninth MOS tube, a thirty-fifth MOS tube, a thirty-first MOS tube, a thirty-second MOS tube, a thirty-third MOS tube, a thirty-fourth MOS tube, a thirty-fifth MOS tube, a thirty-sixth MOS tube, a thirty-seventeenth MOS tube, a thirty-eighth MOS tube, a thirty-ninth MOS tube, a forty-fourth MOS tube and an alternative selector, wherein the alternative selector is provided with a first input end, a second input end, a selection end and an output end, the twenty-ninth MOS tube, the thirty-fifth MOS tube, the thirty-second MOS tube, the thirty-fourth MOS tube, the thirty-seventeenth MOS tube and the thirty-ninth MOS tube are P-type MOS tubes, the thirty-first MOS tube, the thirty-third MOS tube, the fifteenth MOS tube, the sixteenth MOS tube, the thirty-eighth MOS tube and the forty MOS tube are all N-type MOS tubes, a source electrode of the twenty-ninth MOS transistor, a source electrode of the thirty-second MOS transistor, and a source electrode of the thirty-fourth MOS transistor are all connected to a power supply, a gate electrode of the twenty-ninth MOS transistor, a gate electrode of the thirty-second MOS transistor, a gate electrode of the thirty-third MOS transistor, and a gate electrode of the thirty-third MOS transistor are connected, and connection terminals thereof are a third input terminal of the carry self-test circuit, a drain electrode of the twenty-ninth MOS transistor is connected with a source electrode of the thirty-second MOS transistor, a gate electrode of the thirty-third MOS transistor, a gate electrode of the thirty-first MOS transistor, a gate electrode of the thirty-fourth MOS transistor, and a gate electrode of the thirty-fifth MOS transistor are connected, and a connection terminal thereof is a fifth input terminal of the carry self-test circuit, a drain electrode of the thirty second MOS transistor, a drain electrode of the thirty-third second MOS transistor, and a second input terminal of the two-one selector are connected, the source of the thirty-first MOS transistor, the source of the thirty-third MOS transistor and the source of the thirty-sixth MOS transistor are all grounded, the drain of the thirty-second MOS transistor, the drain of the thirty-fourth MOS transistor, the drain of the thirty-fifth MOS transistor and the first input terminal of the two-choice selector are connected, the source of the thirty-fifth MOS transistor and the drain of the thirty-sixth MOS transistor are connected, the selection terminal of the two-choice selector is the fourth input terminal of the carry self-test circuit, the output terminal of the two-choice selector, the drain of the thirty-seventh MOS transistor, the drain of the thirty-eighth MOS transistor, the gate of the thirty-ninth MOS transistor and the gate of the forty MOS transistor are connected, the gate of the thirty-seventh MOS transistor and the source of the thirty-ninth MOS transistor are connected, and the connection terminal thereof is the first input terminal of the carry self-test circuit, the source electrode of the seventeenth MOS tube, the source electrode of the eighteenth MOS tube, the drain electrode of the nineteenth MOS tube and the drain electrode of the forty MOS tube are connected, and the connecting end of the seventeenth MOS tube is the output end of the carry self-checking circuit, the grid electrode of the eighteenth MOS tube and the source electrode of the forty MOS tube are connected, and the connecting end of the grid electrode of the eighteenth MOS tube is the second input end of the carry self-checking circuit.

Technical Field

The invention relates to a full adder, in particular to a full adder based on the feedback of an exclusive-nor circuit.

Background

A full adder is one of the most basic arithmetic devices, and is applied to many VLSI systems, such as Digital Signal Processors (DSPs), multipliers, compressors, parity checkers, and microprocessors. In most VLSI systems, the full adder is located at the key position that determines the VLSI system performance and is the basic unit with the highest repetition rate. Therefore, designing a full adder with high energy efficiency is crucial to digital circuitry performance improvement.

The traditional full adder is realized by adopting a single topological structure in design, and comprises a classical complementary CMOS logic full adder, a transmission gate logic full adder, a double-channel transistor logic full adder, a transmission function full adder and the like. Goel et al in 2006 propose a hybrid transmission logic full adder implemented with hybrid transmission logic. Compared with the traditional full adder, the performance of the hybrid transmission logic full adder is greatly improved, and the design of the full adder is more possible due to the appearance of the hybrid transmission logic full adder. In 2018, Majid et al proposed an HFA-18T (HFA) full adder implemented by using hybrid transmission logic, which is structurally implemented by using three circuit modules, namely an exclusive or circuit, a summing circuit and a carry circuit, wherein the exclusive or circuit uses transmission pipe logic to complete basic signal transmission and is used as a feedback circuit to compensate threshold loss to generate a pair of complementary output signals for output; the summation circuit and the carry circuit are respectively realized by adopting transmission tube and transmission gate logic, and a pair of complementary output signals generated by an exclusive or circuit are used as driving signals. The full adder has the advantages that different transmission logics are adopted to realize the function of each circuit module, the exclusive OR circuit is used as a feedback circuit to make up for threshold loss, and finally the output of the full adder can reach full swing and lower power consumption. However, in the above full adder, when the two input addends AB are equal to 11, the XNOR output of the exclusive or circuit is equal to 1, the feedback circuit is turned on, and at this time, the NMOS transistor in the feedback circuit is turned on to pull down the output XOR to 1, and since the XOR signal is output after the XNOR signal is generated first and then pulled down through the feedback circuit, the delay of the XOR signal is too large; similarly, when the input AB is 00, the XNOR signal in the circuit is delayed too much, so the full adder is delayed too much and the operation speed is slow.

Disclosure of Invention

The invention aims to solve the technical problem of providing a full adder based on the feedback of an exclusive OR circuit, which has small time delay and high running speed on the basis of full swing and low power consumption.

The technical scheme adopted by the invention for solving the technical problems is as follows: a full adder based on feedback of an exclusive OR circuit comprises an exclusive OR circuit, a summing circuit and a carry circuit, wherein the exclusive OR circuit is provided with a first input end, a second input end, a third input end, a first output end used for outputting an exclusive OR logic value and a second output end used for outputting an exclusive OR logic value, the summing circuit is provided with a first input end, a second input end, a third input end and an output end, the carry circuit is provided with a first input end, a second input end, a third input end, a fourth input end, an output end and an inverted output end, the first input end of the exclusive OR circuit is the first input end of the full adder and is used for connecting a first addend, the second input end of the exclusive OR circuit is the second input end of the full adder and is used for connecting a second addend, and the first output end of the exclusive OR circuit is respectively connected with the second input end of the summing circuit and the first output end of the carry circuit The input end of the carry circuit is connected, the second output end of the exclusive nor circuit is respectively connected with the third input end of the summation circuit and the second input end of the carry circuit, the first input end of the summation circuit is the carry signal input end of the full adder and is used for accessing a carry signal output at a low position, the output end of the summation circuit is the output end of the full adder and is used for outputting a sum signal, the output end of the carry circuit is the high-position carry signal output end of the full adder and is used for outputting a carry signal at a high position, the full adder further comprises a first inverter and a second inverter, the input end of the first inverter is connected with the first input end of the exclusive nor circuit, and the output end of the first inverter is respectively connected with the third input end of the exclusive nor circuit and the third input end of the carry circuit, the input end of the second inverter is connected with the first input end of the summation circuit, and the output end of the second inverter is connected with the fourth input end of the carry circuit; the exclusive-nor circuit comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube and a twelfth MOS tube. The first PMOS transistor, the second MOS transistor, the fourth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, and the eleventh MOS transistor are all P-type MOS transistors, and the third MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, and the twelfth MOS transistor are all N-type MOS transistors; the source electrode of the first MOS transistor, the gate electrode of the second MOS transistor, the source electrode of the fifth MOS transistor, the gate electrode of the sixth MOS transistor, the gate electrode of the seventh MOS transistor and the gate electrode of the ninth MOS transistor are connected, and the connection end thereof is the first input end of the exclusive or circuit, the gate electrode of the first MOS transistor, the source electrode of the second MOS transistor, the source electrode of the third MOS transistor, the source electrode of the fourth MOS transistor, the gate electrode of the fifth MOS transistor, the source electrode of the sixth MOS transistor, the gate electrode of the eighth MOS transistor and the gate electrode of the tenth MOS transistor are connected, and the connection end thereof is the second input end of the exclusive or circuit, the drain electrode of the first MOS transistor, the drain electrode of the second MOS transistor, the drain electrode of the third MOS transistor, the drain electrode of the seventh MOS transistor, the gate electrode of the eleventh MOS transistor and the drain electrode of the twelfth MOS transistor are connected, and the connection end thereof is the second input end of the exclusive or circuit A gate of the third MOS transistor is connected to a gate of the fourth MOS transistor, a connection end of the third MOS transistor is a third input end of the exclusive nor circuit, a drain of the fourth MOS transistor, a drain of the fifth MOS transistor, a drain of the sixth MOS transistor, a drain of the tenth MOS transistor, a drain of the eleventh MOS transistor is connected to a gate of the twelfth MOS transistor, a connection end of the fifth MOS transistor is a second output end of the exclusive nor circuit, a source of the seventh MOS transistor is connected to a drain of the eighth MOS transistor, a source of the eighth MOS transistor is grounded, a source of the ninth MOS transistor and a source of the eleventh MOS transistor are both connected to a power supply, a drain of the ninth MOS transistor is connected to a source of the tenth MOS transistor, and a source of the twelfth MOS transistor is grounded; the summing circuit comprises a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube and a sixteenth MOS tube; the thirteenth MOS tube and the sixteenth MOS tube are both P-type MOS tubes, and the fourteenth MOS tube and the fifteenth MOS tube are both N-type MOS tubes; a drain of the thirteenth MOS transistor, a drain of the fourteenth MOS transistor, a gate of the fifteenth MOS transistor and a gate of the sixteenth MOS transistor are connected, and connection ends thereof are first input ends of the summing circuit, a gate of the thirteenth MOS transistor and a drain of the sixteenth MOS transistor are connected, and connection ends thereof are second input ends of the summing circuit, a source of the thirteenth MOS transistor, a source of the fourteenth MOS transistor, a source of the fifteenth MOS transistor and a source of the sixteenth MOS transistor are connected, and connection ends thereof are output ends of the summing circuit, a gate of the fourteenth MOS transistor and a drain of the fifteenth MOS transistor are connected, and connection ends thereof are third input ends of the summing circuit; the carry circuit comprises a seventeenth MOS tube, an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube and a third phase inverter, wherein the seventeenth MOS tube and the nineteenth MOS tube are both P-type MOS tubes, and the eighteenth MOS tube and the twentieth MOS tube are both N-type MOS tubes; the gate of the seventeenth MOS transistor is connected to the gate of the twentieth MOS transistor, and the connection end of the seventeenth MOS transistor is the first input end of the carry circuit, the source of the seventeenth MOS transistor, the source of the eighteenth MOS transistor, the source of the nineteenth MOS transistor, the source of the twentieth MOS transistor and the input end of the third inverter are connected, and the connection end of the twenty-first MOS transistor is the reverse output end of the carry circuit, the gate of the eighteenth MOS transistor and the gate of the nineteenth MOS transistor are connected, and the connection end of the nineteenth MOS transistor is the second input end of the carry circuit, the drain of the seventeenth MOS transistor and the drain of the eighteenth MOS transistor are connected, and the connection end of the seventeenth MOS transistor and the drain of the nineteenth MOS transistor is the third input end of the carry circuit, the drain of the nineteenth MOS transistor and the drain of the twentieth MOS transistor are connected, and the connection end of the nineteenth MOS, the output end of the third phase inverter is the output end of the carry circuit.

The full adder also comprises a summation self-checking circuit and a carry self-checking circuit, wherein the summation self-checking circuit and the carry self-checking circuit are respectively provided with a first input end, a second input end, a third input end, a fourth input end, a fifth input end and an output end, the first input end of the summation self-checking circuit is connected with the first input end of the summation circuit, the second input end of the summation self-checking circuit is connected with the output end of the second phase inverter, the third input end of the summation self-checking circuit is connected with the second input end of the summation circuit, the fourth input end of the summation self-checking circuit is connected with the third input end of the summation circuit, the fifth input end of the summation self-checking circuit is connected with the output end of the summation circuit, and the first input end of the carry self-checking circuit is connected with the output end of the carry circuit, the second input end of the carry self-checking circuit is connected with the inverted output end of the carry circuit, the third input end of the carry self-checking circuit is connected with the first input end of the summation circuit, the fourth input end of the carry self-checking circuit is connected with the first input end of the exclusive nor circuit, and the fifth input end of the carry self-checking circuit is connected with the second input end of the exclusive nor circuit; the summation self-detection circuit comprises a twenty-first MOS tube, a twenty-second MOS tube, a twenty-third MOS tube, a twenty-fourth MOS tube, a twenty-fifth MOS tube, a twenty-sixth MOS tube, a twenty-seventh MOS tube and a twenty-eighth MOS tube, wherein the twenty-first MOS tube, the twenty-third MOS tube, the twenty-fifth MOS tube and the twenty-seventh MOS tube are P-type MOS tubes, the twenty-second twelve MOS tube, the twenty-fourth MOS tube, the twenty-sixth MOS tube and the twenty-eighth MOS tube are N-type MOS tubes, the source electrode of the twenty-first MOS tube is connected with the gate electrode of the twenty-second twelve MOS tube, the connecting end of the twenty-second MOS tube is the second input end of the summation self-detection circuit, the gate electrode of the twenty-first MOS tube, the gate electrode of the twenty-second MOS tube, the source electrode of the twenty-third MOS tube is connected with the source electrode of the twenty-fourth MOS tube, and the connecting end of the twenty-fifth input end of the summation self-detection circuit, the drain of the twenty-first MOS transistor, the drain of the twenty-second MOS transistor, the drain of the twenty-third MOS transistor, the drain of the twenty-fourth MOS transistor, the drain of the twenty-fifth MOS transistor, the drain of the twenty-sixth MOS transistor, the gate of the twenty-seventh MOS transistor and the gate of the twenty-eighteen MOS transistor are connected, the source of the twenty-second MOS transistor and the gate of the twenty-fourth MOS transistor are connected and the connection end thereof is the first input end of the summation self-test circuit, the gate of the twenty-fifth MOS transistor and the source of the twenty-seventh MOS transistor are connected and the connection end thereof is the third input end of the summation self-test circuit, the source of the twenty-fifth MOS transistor, the source of the twenty-sixth MOS transistor, the drain of the twenty-seventh MOS transistor and the drain of the twenty-eighteen MOS transistor are connected and the connection end thereof is the output end of the summation self-test circuit, the grid electrode of the twenty-sixth MOS tube is connected with the source electrode of the twenty-eighteen MOS tube, and the connecting end of the grid electrode of the twenty-sixth MOS tube is the fourth input end of the summation self-detection circuit; the carry self-checking circuit comprises a twenty-ninth MOS tube, a thirty-fifth MOS tube, a thirty-first MOS tube, a thirty-second MOS tube, a thirty-third MOS tube, a thirty-fourth MOS tube, a thirty-fifth MOS tube, a thirty-sixth MOS tube, a thirty-seventeenth MOS tube, a thirty-eighth MOS tube, a thirty-ninth MOS tube, a forty-fourth MOS tube and an alternative selector, wherein the alternative selector is provided with a first input end, a second input end, a selection end and an output end, the twenty-ninth MOS tube, the thirty-fifth MOS tube, the thirty-second MOS tube, the thirty-fourth MOS tube, the thirty-seventeenth MOS tube and the thirty-ninth MOS tube are P-type MOS tubes, the thirty-first MOS tube, the thirty-third MOS tube, the fifteenth MOS tube, the sixteenth MOS tube, the thirty-eighth MOS tube and the forty MOS tube are all N-type MOS tubes, a source electrode of the twenty-ninth MOS transistor, a source electrode of the thirty-second MOS transistor, and a source electrode of the thirty-fourth MOS transistor are all connected to a power supply, a gate electrode of the twenty-ninth MOS transistor, a gate electrode of the thirty-second MOS transistor, a gate electrode of the thirty-third MOS transistor, and a gate electrode of the thirty-third MOS transistor are connected, and connection terminals thereof are a third input terminal of the carry self-test circuit, a drain electrode of the twenty-ninth MOS transistor is connected with a source electrode of the thirty-second MOS transistor, a gate electrode of the thirty-third MOS transistor, a gate electrode of the thirty-first MOS transistor, a gate electrode of the thirty-fourth MOS transistor, and a gate electrode of the thirty-fifth MOS transistor are connected, and a connection terminal thereof is a fifth input terminal of the carry self-test circuit, a drain electrode of the thirty second MOS transistor, a drain electrode of the thirty-third second MOS transistor, and a second input terminal of the two-one selector are connected, the source of the thirty-first MOS transistor, the source of the thirty-third MOS transistor and the source of the thirty-sixth MOS transistor are all grounded, the drain of the thirty-second MOS transistor, the drain of the thirty-fourth MOS transistor, the drain of the thirty-fifth MOS transistor and the first input terminal of the two-choice selector are connected, the source of the thirty-fifth MOS transistor and the drain of the thirty-sixth MOS transistor are connected, the selection terminal of the two-choice selector is the fourth input terminal of the carry self-test circuit, the output terminal of the two-choice selector, the drain of the thirty-seventh MOS transistor, the drain of the thirty-eighth MOS transistor, the gate of the thirty-ninth MOS transistor and the gate of the forty MOS transistor are connected, the gate of the thirty-seventh MOS transistor and the source of the thirty-ninth MOS transistor are connected, and the connection terminal thereof is the first input terminal of the carry self-test circuit, the source electrode of the seventeenth MOS tube, the source electrode of the eighteenth MOS tube, the drain electrode of the nineteenth MOS tube and the drain electrode of the forty MOS tube are connected, and the connecting end of the seventeenth MOS tube is the output end of the carry self-checking circuit, the grid electrode of the eighteenth MOS tube and the source electrode of the forty MOS tube are connected, and the connecting end of the grid electrode of the eighteenth MOS tube is the second input end of the carry self-checking circuit. In the circuit, the summation self-checking circuit and the carry self-checking circuit are connected behind the summation circuit and the carry circuit, when an error occurs in the operation of the circuit, the error can be timely found through self-checking signals output by the summation self-checking circuit and the carry self-checking circuit, and the reliability of the full adder is ensured.

Compared with the prior art, the invention has the advantages that the exclusive-nor circuit is used as a main module of the full adder circuit, has great influence on the speed and the power consumption of the full adder circuit, the exclusive-nor circuit is formed by the first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, the tenth MOS tube, the eleventh MOS tube and the twelfth MOS tube, the exclusive-nor circuit adopts feedback logic, three logics of transmission tube logic and static CMOS logic are realized, two addend signals input into the full adder are marked as A and B, when AB 00 or 11 is input, the third MOS tube and the fourth MOS tube complement as strong '0' and strong '1', so that the output of the full adder circuit is full, and simultaneously, the ninth MOS tube and the tenth MOS tube are connected in series to assist the pull-up network conduction to pull the XNOR signal to '1', the eleventh MOS tube to pull up the XNOR signal, or the seventh MOS tube and the eighth MOS tube are connected in series to pull down the network to conduct and pull down the XOR signal to '0', the twelfth MOS tube assists in pulling down the XOR signal, the summing circuit adopts the combined logic design of a transmission gate and a transmission tube, when the transmission signals of the fifteenth MOS tube and the sixteenth MOS tube in the summing circuit have threshold loss, the transmission gate formed by the thirteenth MOS tube and the fourteenth MOS tube in the summing circuit conducts and compensates the threshold loss, the carry circuit is composed of two transmission gates and an inverter, the first transmission gate is composed of a seventeenth MOS tube and an eighteenth MOS tube, the second transmission gate is composed of a nineteenth MOS tube and a twentieth MOS tube and has the functions equivalent to a data selector, the XOR signal and the XNOR signal are used as selection signals, the inverted signal of the addition signal A and the inverted signal of the input carry CI signal are used as the input of the data selector, and the complementary output fed back by the same or exclusive or circuit is used as the driving signals of the summing circuit and the carry circuit, the invention has greatly simplified the circuit structure of the summation circuit and carry circuit, in the invention, the same or exclusive OR circuit adopts feedback circuit and tandem MOS tube to pull up or pull down and output together, have faster response speed, there is very big speed advantage while the circuit works, meanwhile, compensate the threshold loss existing in the circuit through third MOS tube and fourth MOS tube, in the course of circuit work, each MOS tube has definite division of labor, there is no direct current route, therefore the power consumption of the circuit is smaller, adopt the transmission gate to complement with the transmission tube logic when summing circuit and carry circuit are designed, fully utilize the complementary output of the same or exclusive OR circuit, simplify the summing and carry circuit, therefore the invention has on the basis of full swing and lower power consumption, the time delay is smaller, the running speed is faster.

Drawings

Fig. 1 is a block diagram of a full adder based on exclusive nor circuit feedback according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram of an exclusive OR circuit of the full adder based on exclusive OR feedback of the present invention;

FIG. 3 is a circuit diagram of a summing circuit of a full adder based on the feedback of an exclusive-nor circuit of the present invention;

FIG. 4 is a circuit diagram of a carry circuit of a full adder based on the feedback of an exclusive-nor circuit according to the present invention;

FIG. 5 is a block diagram of a full adder based on the feedback of the exclusive-nor circuit according to a second embodiment of the present invention;

FIG. 6 is a circuit diagram of a summing self-test circuit of a full adder based on the feedback of an exclusive-nor circuit according to the present invention;

FIG. 7 is a circuit diagram of a carry self-checking circuit of a full adder based on the feedback of an exclusive-nor circuit according to the present invention;

FIG. 8 is a simulation diagram of a full adder based on the feedback of the exclusive-nor circuit according to a first embodiment of the present invention;

FIG. 9 is a simulation diagram of a full adder based on the feedback of the exclusive-nor circuit according to the second embodiment of the present invention;

Detailed Description

The invention is described in further detail below with reference to the accompanying examples.