阅读说明：本技术 用于相关电子开关（ces）器件操作的方法、系统和设备 (Methods, systems, and apparatus for Correlated Electron Switch (CES) device operation ) 是由 姆迪特·巴尔加瓦 格伦·阿诺德·罗森代尔 于 2018-05-10 设计创作，主要内容包括：本技术总体涉及用于操作相关电子开关(CES)器件的方法、系统和设备。在一个实施例中,通过控制施加到非易失性存储器器件的端子的电流和电压,能够在写入操作中将CES器件置于多个阻抗状态中的任一阻抗状态中。在一个实施方式中,CES器件可以被置于高阻抗或绝缘状态中或者两个或更多个可区分的低阻抗或导电状态中。(The present technology relates generally to methods, systems, and devices for operating Correlated Electron Switching (CES) devices. In one embodiment, a CES device can be placed in any one of a plurality of impedance states in a write operation by controlling current and voltage applied to terminals of the non-volatile memory device. In one embodiment, a CES device may be placed in a high impedance or insulating state or in two or more distinguishable low impedance or conductive states.)

1. A method, comprising:

applying a first programming signal to a terminal of an associated electronic switching (CES) element to place the CES element in a first particular low impedance or conductive state of two or more low impedance or conductive states, the CES element capable of being placed in a high impedance or insulating state and the two or more low impedance or conductive states;

measuring or detecting a first current in the CES element in response to a read signal being applied to a terminal of the CES element; and is

Determining that the CES element is in the first particular low impedance or conductive state among the two or more low impedance or conductive states based at least in part on a measured or detected current in the CES element.

2. The method of claim 1, wherein the CES element comprises a Correlated Electron Material (CEM) formed between terminals of the CES element, and wherein the two or more low impedance or conductive states are discernable based at least in part on a density or concentration of electrons in the CEM.

3. The method of claim 1 or claim 2, further comprising: applying a second programming signal to a terminal of the CES element to place the CES element in a second particular low impedance or conductive state, wherein applying the first programming signal to the terminal of the CES element provides a second current in the CES element and applying the second programming signal to the terminal of the CES element provides a third current in the CES element, the third current having a magnitude that is greater than a magnitude of the second current.

4. The method of claim 3, further comprising: measuring or detecting a fourth current in the CES element in response to the read signal being applied to a terminal of the CES element when the CES element is in the second particular low impedance or conductive state, wherein a magnitude of the first current is greater than a magnitude of the fourth current.

5. The method of claim 3, further comprising: measuring or detecting a fourth current in the CES element in response to the read signal being applied to a terminal of the CES element when the CES element is in the second particular low impedance or conductive state, wherein a magnitude of the first current is less than a magnitude of the fourth current.

6. The method of any preceding claim, further comprising: the determined particular low impedance or conduction state is mapped to one of three or more symbols or values.

7. The method of any preceding claim, further comprising: the determined low impedance or conductive state is mapped with a binary value.

8. An apparatus, comprising:

an associated electronic switching (CES) element; and

a write circuit configured to place the CES element in a particular state from among a plurality of detectable states, including a high impedance or insulating state and two or more low impedance or conductive states.

9. The apparatus of claim 8, further comprising: a sensing circuit to detect between or among the two or more low impedance or conductive states of the CES element.

10. The device of claim 9, wherein the sensing circuit is configured to detect between or among the two or more low impedance or conductive states of a CES element based at least in part on a current in the CES element sensed in response to a controlled voltage being applied across terminals of the CES element.

11. The apparatus of claim 9 or claim 10, further comprising: circuitry for mapping a detected impedance state of the CES element to one of three or more symbols or values.

12. The apparatus of any of claims 9 to 11, further comprising: circuitry for mapping a detected impedance state of the CES element to a binary value.

13. The apparatus of any of claims 8 to 12, wherein the write circuitry is configured to:

applying a first voltage between a first terminal of the CES element and a second terminal of the CES element while maintaining a first current between the first terminal and the second terminal to place the CES element in the high impedance or insulating state;

applying a second voltage between the first terminal and the second terminal of the CES element to place the CES element in a particular state from the two or more low impedance or conductive states while maintaining a particular second current from a plurality of second currents between the first terminal and the second terminal,

wherein a magnitude of the second voltage is greater than a magnitude of the first voltage, and wherein a magnitude of the first current is greater than a magnitude of the plurality of second currents.

14. The apparatus of claim 13, wherein the plurality of second currents correspond to the two or more low impedance or conductive states.

15. The apparatus of claim 13 or 14, further comprising: a read circuit to detect between or among the two or more low impedance or conductive states of the CES element, the read circuit configured to:

applying a programming signal to a terminal of the CES element to provide a current in the CES element having a magnitude that is less than a magnitude of at least one of the plurality of second currents; and is

Sensing a current in the CES element after applying the programming signal to determine whether the CES element is placed in the high impedance or insulation state.

16. The device of any of claims 8 to 15, wherein the CES comprises a Correlated Electron Material (CEM) formed between terminals of the CES, and wherein the two or more low impedance or conductive states are discernable based at least in part on a density or concentration of electrons in the CEM.

Technical Field

The present technology relates generally to utilizing memory devices.

Background

Non-volatile memory is a type of memory that: wherein a memory cell or element does not lose its state after power to the device is removed. For example, computer memory, which was originally made of a ring of ferrite magnetizable in two directions, is non-volatile. As semiconductor technology advances to higher levels of miniaturization, ferrite devices are being replaced by more familiar volatile memories, such as DRAM (dynamic random access memory) and SRAM (static RAM).

One type of non-volatile memory is an Electrically Erasable Programmable Read Only Memory (EEPROM) device, which has a large cell area and may require a strong voltage (e.g., from 12.0 to 21.0 volts) applied across the transistor gate to be written to or erased. Further, the erase or write time is typically on the order of tens of microseconds. One limiting factor in using an EEPROM is that the number of erase/write cycles must not exceed about 600,000, or on the order of 10⁵-10⁶. Memory arrays are sectorized by erasing "pages" (e.g., sub-arrays) in EEPROMs known as flash memory devices at once, thereby eliminating the need for pass-gate switching transistors between the EEPROM and the non-volatile transistors in the semiconductor industry. In flash memory devices, the ability to maintain random access (erase/write single bits) is sacrificed in exchange for speed and higher bit density.

Recently, FeRAM (ferroelectric RAM) offers low power, relatively high write/read speed, and endurance of over 100 hundred million read/write cycles. Similarly, magnetic memories (MRAMs) offer higher write/read speeds and endurance, but have higher cost spills and greater power consumption. None of these techniques can achieve the density of flash memory devices, for example. Therefore, flash memory is still the preferred choice for non-volatile memory. However, it is generally recognized that flash memory technology can be difficult to scale down to below 65 nanometers (nm). Therefore, new nonvolatile memory devices that can be reduced to smaller sizes are being actively sought.

Technologies considered to replace flash memory devices include memories based on certain such materials: exhibit a change in resistance associated with a phase change of the material (determined at least in part by the atoms of long range order in the crystal structure). In one type of variable resistance memory, known as a phase change memory (PCM/PCRAM) device, the resistance changes as the memory element briefly melts and then cools to a conductive crystalline state or a non-conductive amorphous state. Representative materials vary from one another but may include GeSbTe, where Sb and Te may be interchanged with other elements of the periodic table having the same or similar properties. However, these resistance-based memories have not proven commercially useful because their transition between the conductive and insulating states depends on physical structural phenomena (e.g., melting at temperatures up to 600 degrees celsius) and because the return to the solid state cannot be adequately controlled for use in useful memories in many applications.

Another variable resistance memory class includes materials that respond to an initial high "forming" voltage and current to activate a variable resistance function. These materials may include, for example: pr (Pr) of_xCa_yMn_zO_εWherein the stoichiometry of x, y, z and epsilon varies; transition metal oxides, e.g. CuO, CoO, Vo_x、NiO、TiO₂、Ta₂O₅(ii) a And some perovskites, such as Cr; SrTiO₃. Several of these memory types exist and belong to the resistive ram (reram) or conductive bridge rams (cbram) categories to distinguish them from chalcogenide type memories. It is assumed that the resistive switches in these RAMs are due, at least in part, to the formation of narrow conductive paths or filaments connecting the top and bottom conductive terminals by an electroforming (electroforming) process (although the presence of such conductive filaments is still a controversial problem). Since the operation of the ReRAM/CBRAM may be strongly temperature dependent, the resistive switching mechanism in the ReRAM/CBRAM may also be highly temperature dependent. In addition, these systems are likely to operate randomly because the formation and movement of the filaments is random. Other types of ReRAM/CBRAM may also exhibit instability in quality. In addition, the resistive switches in ReRAM/CBRAM tend to fatigue over many memory cycles. Namely, it isAfter changing the memory state multiple times, the resistance difference between the conductive and insulating states may change significantly. In commercial memory devices, such changes may cause the memory to be out of specification, thereby rendering it unusable.

In view of the inherent difficulties in forming thin film resistive switching materials that are stable over time and temperature, a practical resistive switching memory remains challenging. Furthermore, all resistive switching mechanisms developed to date are not inherently suitable for memories due to high currents, electroforming, no measurable memory read or write window over reasonable temperature and voltage ranges, and many other problems such as random behavior. Thus, there remains a need in the art for non-volatile memory for certainty with respect to: have low power, high speed, high density and stability, and in particular, such memories can be scaled to feature sizes well below 65 nanometers (nm).

Disclosure of Invention

Briefly, certain embodiments are directed to a method comprising: applying a first programming signal to a terminal of an associated electronic switch (CES) to place the CES in a first particular low impedance or conductive state of two or more low impedance or conductive states, the CES capable of being placed in a high impedance or insulating state and two or more low impedance state impedance or conductive states; measuring or detecting a first current in the CES in response to a read signal being applied to a terminal of the CES; and determining that the CES is in a first particular low impedance or conducting state of the two or more low impedance or conducting states based at least in part on the measured or detected current in the CES.

Another particular embodiment is directed to an apparatus comprising: an associated electronic switching (CES) element; a write circuit configured to place the CES element in a particular state from among a plurality of detectable states, including a high impedance or insulating state and two or more low impedance or conductive states.

Drawings

It should be understood that the above-described embodiments are merely example embodiments, and claimed subject matter is not necessarily limited in any particular respect to these example embodiments.

The claimed subject matter is particularly pointed out and distinctly claimed in the concluding portion of the specification. However, both as to organization and/or method of operation, together with objects, features, and/or advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which:

figure 1A shows a current density versus voltage graph for a CES device according to an embodiment;

fig. 1B is a schematic diagram of an equivalent circuit of a CES device according to an embodiment;

FIG. 2 is a schematic diagram of a memory circuit according to an embodiment;

FIGS. 3A and 3B are schematic diagrams of alternative architectures of bitcells, consistent with certain embodiments;

figure 4 is a graph of current density versus voltage for a CES device capable of being in three or more impedance states, in accordance with an embodiment; and

fig. 5 is a flow diagram depicting a procedure for operations that may be applicable to a CES device capable of being placed in any of two or more low impedance or conductive states, in accordance with an embodiment.

Detailed Description

In the following detailed description, reference is made to the accompanying drawings that form a part hereof wherein like numerals may designate like, similar, and/or analogous components throughout the detailed description. It will be appreciated that for simplicity and/or clarity of illustration, for example, the figures have not necessarily been drawn to scale. For example, the dimensions of some of the aspects may be exaggerated relative to other aspects. Further, it is to be understood that other embodiments may be utilized. In addition, structural and/or other changes may be made without departing from claimed subject matter. Reference in this specification to "claimed subject matter" means subject matter that is intended to be encompassed by one or more claims or any portion thereof, and is not necessarily intended to refer to a complete claim set, to a particular combination of claim sets (e.g., method claims, product claims, etc.), or to a particular claim item. It should also be noted that directions and/or references, such as up, down, top, bottom, and the like, may be used, for example, to facilitate discussion of the figures and are not intended to limit application of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the claimed subject matter and/or equivalents are not to be taken.

Certain embodiments of the present disclosure incorporate Correlated Electron Materials (CEMs) to form Correlated Electron Switches (CES). In this context, CES may exhibit a burst conductor/insulator transition induced by electron correlation (electron correlation) rather than solid state structural phase change (e.g., crystalline/amorphous in Phase Change Memory (PCM) devices, or filament formation and conduction in resistive RAM devices, as discussed above). Unlike melting/solidification or filament formation, the abrupt conductor/insulator transition in CES may be a response to quantum mechanical phenomena. In any of several embodiments, such quantum mechanical transitions between conductive and insulating states in a CEM memory device can be understood.

The quantum-mechanical transition of CES between the insulating and conducting states can be understood in terms of the mott transition. In a mott transition, the material may switch from an insulating state to a conducting state if a mott transition condition occurs. The criterion may be passed through the condition (n)_c)^1/3a ≈ 0.26, where n_cIs the concentration of electrons and "a" is the Bohr radius. If the critical carrier concentration is reached such that the Mott criterion is met, a Mott transition may occur and the state may change from a high resistance/capacitance to a low resistance/capacitance.

Motter transitions can be controlled by electronic localization. When carriers are localized, the strong coulombic interaction between electrons can split the energy bands of the material, forming an insulator. If the electrons are no longer localized, weak coulombic interactions may dominate band splitting, leaving behind metallic (conductive) bands. Sometimes this is interpreted as a "crowded elevator" phenomenon. Although there are only a few people in the elevator, these people can easily walk, which is similar to the conductive state. On the other hand, when a certain concentration of people is reached in the elevator, the passengers are not able to move, which is similar to an insulated state. However, it is to be understood that this classical interpretation, as with all classical interpretations of quantum phenomena, is merely an incomplete analogy, and claimed subject matter is not limited in this respect.

The resistive switching integrated circuit memory may include: a resistive switching memory cell comprising a CES device; a write circuit to place the resistive-switching memory cell in a first resistive state or a second resistive state depending on a signal provided to the memory cell, wherein a resistance of the CES is higher in the second resistive state than in the first resistive state; and a read circuit for sensing a state of the memory cell and providing an electrical signal corresponding to the sensed state of the memory cell. In particular embodiments, a CES device may switch resistance states in response to a mott transition in a majority of a volume of the CES device. In an embodiment, the CES device may contain a material selected from the group consisting of: aluminum, cadmium, chromium, cobalt, copper, gold, iron, manganese, mercury, molybdenum, nickel, palladium, rhodium, ruthenium, silver, tantalum, tin, titanium, vanadium, and zinc (all of which may be bonded to a cation such as oxygen or other type of ligand), or combinations thereof.

In particular embodiments, the CES device may be formed as a "CEM random access memory (CeRAM)" device. In this context, a CeRAM device includes such materials: the material may be enabled to transition between or among a plurality of predetermined, detectable memory states based at least in part on a transition of at least a portion of the material between a conductive state and an insulating state utilizing a mott transition of quantum mechanics. In this context, "memory state" means a detectable state of a memory device, a detectable state indicating a value, sign, parameter, or condition, to provide just a few examples. In one particular implementation, as described below, a memory state of a memory device may be detected based at least in part on a signal detected on a terminal of the memory device in a read operation. In another particular embodiment, as described below, a memory device may be placed into a particular memory state representing or storing a particular value, symbol, or parameter by applying one or more signals across terminals of the memory device in a "write operation.

In particular embodiments, the CES element may include a material sandwiched between conductive terminals. The material can be transformed between the aforementioned conductive and insulating memory states by applying a specific voltage and current between the terminals. As discussed below in certain example embodiments, the voltage V may be applied across the conductive terminals by a voltage applied across the conductive terminals_resetAnd current I_resetBy placing the material of the CES element sandwiched between the terminals in an insulating or high impedance memory state, or by applying a voltage V across the terminals_setAnd current I_setTo be placed in a conductive or low impedance memory state. In this context, it should be understood that terms such as "conductive or low impedance" memory state and "insulating or high impedance" memory state are relative terms and are not specific to any particular amount or value of impedance or conductivity. For example, in one embodiment, when a memory device is in a first memory state, referred to as an insulative or high impedance memory state, the memory device is less conductive (or more insulative) than the memory device in a second memory state, referred to as a conductive or low impedance memory state. Furthermore, as discussed below with respect to particular embodiments, a CES may be placed in any of two or more low impedance or conductive states that are distinct and distinguishable.

In particular embodiments, a CeRAM memory cell may include a metal/CEM/metal (M/CEM/M) stack formed on a semiconductor. Such that the M/CEM/M stack may be formed on a diode, for example. In an example, such a diode may be selected from the group consisting of: junction diodes and schottky diodes. In this context, it is understood that "metal" means a conductor, i.e. any material that functions as a metal, including for example polysilicon or a doped semiconductor.

Fig. 1A shows a current density versus voltage across terminals (not shown) of a CES device or CES element according to an embodiment. The CES may be placed in a conductive state or an insulating state based, at least in part, on a voltage applied to terminals of the CES device (e.g., in a write operation). For example, applying a voltage V_setAnd current density J_setThe CES device may be placed in a conductive memory state and a voltage V applied_resetAnd current density J_resetThe CES device may be placed in an insulated memory state. After CES is placed in the insulating or conducting state, it may be possible to apply a voltage V_readA particular state of the CES device is detected (e.g., in a read operation) and by detecting a current or current density at a terminal of the CeRAM device.

According to an embodiment, the CES device of fig. 1A may include any Transition Metal Oxide (TMO) (e.g., perovskite), mott insulator, charge exchange insulator, and anderson disordered insulator. In particular embodiments, the CEM device may be formed of switching materials such as: nickel oxide, cobalt oxide, iron oxide, yttrium titanium oxide, and perovskites (e.g., chromium doped strontium titanate, lanthanum titanate), and the manganate families (including praseodymium calcium manganate and lanthanum manganate), just to provide a few examples. In particular, oxides doped with elements having incomplete "d" and "f" orbital shells may exhibit sufficient resistive switching characteristics for use in CEM devices. In an embodiment, a CES device may be fabricated without electroforming. Other embodiments may employ other transition metal compounds without departing from claimed subject matter. For example, { M (chxn)₂Br}Br₂Where M may comprise Pt, Pd, or Ni, and chxn comprises 1R, 2R-cyclohexanediamine, and other such metal complexes may be used without departing from claimed subject matter.

The CES device of fig. 1A may include a material that is a variable resistance material of a TMO metal oxide, although it should be understood that these are merely exemplary and are not intended to be limitingThe claimed subject matter. Other variable resistance materials may also be used in certain embodiments. Nickel oxide NiO is disclosed as one particular TMO. The NiO materials discussed herein can be doped with extrinsic ligands that can stabilize variable resistance properties. In particular, the NiO variable resistance materials disclosed herein may include carbon-containing ligands, which may be composed of NiO (C)_x) To indicate. Here, one skilled in the art can determine the x value for any particular carbon-containing ligand and any particular combination of carbon-containing ligand and NiO simply by balancing the valences. In another particular example, NiO doped with an extrinsic ligand may be represented as NiO (L)_x) Wherein L is_xThe ligand elements or compounds may be indicated, and x may indicate the number of units of ligand for one unit of NiO. One skilled in the art can determine the x value for any particular ligand and any particular combination of ligand with NiO or any other transition metal simply by balancing the valences.

A CES device may rapidly switch from a conductive state to an insulating state via a mott transition if a sufficient bias voltage is applied (e.g., exceeding the band splitting potential) and the mott condition described above is satisfied (injected electron holes — electrons in the switching region). This may occur at point 108 in the relationship diagram of FIG. 1A. At this point, the electrons are no longer shielded and become localized. This correlation can result in a strong electron-electron interaction potential that causes the energy bands to split, thereby forming an insulator. While the CES device is still in an insulating state, current may be generated due to the transport of electron holes. Electrons may be injected into a metal-insulator-metal (MIM) diode beyond the barrier of the MIM device if a sufficient bias voltage is applied across the terminals of the CES. If enough electrons are injected and a sufficient potential is applied across the terminals to place the CES device in a particular low impedance or conducting state, the increase in electrons may shield the electrons and delocalize the electrons, which may collapse the potential of the split energy bands forming the metal.

According to an embodiment, a "compliance" condition applied externally (based at least in part on a write operation period)Determined by an external current that is limited) to control current in the CES device to place the CES device in a conductive or low impedance state. This externally applied compliance current may also condition the current density for a subsequent reset operation to place the CES in a high impedance or insulating state. As shown in the particular embodiment of FIG. 1A, a current density J applied during a write operation at point 116 to place the CES device in a conductive or low impedance state_compA compliance condition may be determined to place the CES device in an insulating or high impedance state in a subsequent write operation. As shown, this may then be accomplished by a voltage V at point 108_resetLower applied current density J_reset≥J_compTo place the CES device in an insulating state, wherein J_compIs externally applied.

Thus, compliance may set the number of electrons in the CES device that will be used for "trapping" by holes of the mott transition. In other words, the current applied in a write operation to place the CES device in a conductive memory state may determine the number of holes to be injected into the CEM device for subsequently transitioning the CEM device to an insulating memory state.

As noted above, the reset condition may occur in response to a mott transition at point 108. As noted above, such mott transitions may occur under the following conditions in CES devices: the electron concentration n is equal to the electron hole concentration p. This condition can be modeled according to the following expression (1):

wherein: lambda [ alpha ]_TFIs the Thomas Fermi (Thomas Fermi) shield length, and C is a constant.

According to an embodiment, the current or current density in the region 104 of the graph shown in FIG. 1A may be responsive to holes due to a voltage signal applied across terminals of the CEM deviceThe implant is present. Here, the injection of holes may satisfy a critical voltage V applied across terminals of the CEM device_MIAt a current I_MIThe mott transition criterion for the resulting conductive state to insulating state transition. This can be modeled according to the following expression (2):

Q(V_MI)＝qn(V_MI) (2)

() Wherein Q (V)_MI) Is the injected charge (hole or electron) and is a function of the applied voltage.

Injecting electron-hole to enable a mott transition to occur between energy bands and to a critical voltage V_MIAnd critical current I_MIA response is made. According to the expression (1), by equating the electron concentration n with the charge concentration, the charge concentration is represented by I in the expression (2)_MIThe injected holes cause a Mott transition, and such a threshold voltage V can be determined according to the following expression (3)_MILength lambda of shielding from Thomas Fermi_TFThe dependency of (c) is modeled:

wherein:

A_CeRamis the cross-sectional area of the CES element; and is

J_reset(V_MI) Is to be at the critical voltage V_MIA current density through the CES element applied to the CES element to place the CES element in an insulating state.

According to an embodiment, a CES element may be placed in a conductive memory state (e.g., by transitioning from an insulating memory state) by injecting a sufficient number of electrons to satisfy the mott transition criterion.

Upon transitioning a CES to a conductive memory state, a critical switching potential (e.g., V) is overcome due to sufficient electrons having been injected and the potential across the terminals of the CES device_set) The injected electrons begin to shield and delocalize the double-occupied electrons to reverse the disproportionation reaction and close the band gap. The critical voltage V for effecting a transition to a conductive memory state may be expressed according to the following expression (4)_IMCurrent density J for lower CES transition to conductive memory state_set(V_IM)：

Q(V_IM)＝qn(V_IM)

Wherein the content of the first and second substances,

a_Bis the Bohr radius.

According to an embodiment, a "read window" 102 for detecting a memory state of a CES device in a read operation may be set to a portion 106 in the graph of fig. 1A when the CES device is in an insulating state versus when the CES device is at a read voltage V_readThe difference between the portions 104 in the relationship diagram of fig. 1A when in the conductive state. In particular embodiments, read window 102 may be used to determine a thomas fermi shield length λ of a material comprising a CES device_TF. For example, at a voltage V according to the following expression (5)_resetLower, current density J_resetAnd J_setIt can be related:

in another embodiment, can be used forA "write window" 110 for placing a CES device in an insulating or conductive memory state during a write operation is set to V_reset(at J)_resetLower) and V_set(at J)_setLower) is calculated. Establishing | V_set|>|V_resetI achieve switching between a conducting state and an insulating state. V_resetCan be approximately at the band splitting potential caused by the correlation, and V_setMay be about twice the band splitting potential. In particular embodiments, the size of the write window 110 may be determined based at least in part on the doping and the material of the CES device.

The transition from high resistance/capacitance to low resistance/capacitance in a CES device may be represented by the singular impedance of the CES device. Fig. 1B depicts a schematic diagram of an equivalent circuit of an example variable resistance device (such as a CES device), such as variable impedance device 124. As mentioned, the variable impedance device 124 may include characteristics of both a variable resistance and a variable capacitance. For example, in an embodiment, the equivalent circuit of the variable resistance device may include a variable resistor (such as variable resistor 126) in parallel with a variable capacitor (such as variable capacitor 128). Of course, although variable resistor 126 and variable capacitor 128 are depicted in fig. 1B as comprising discrete components, a variable impedance device, such as variable impedance device 124, may comprise a substantially homogeneous CES, wherein the CES element comprises characteristics of a variable capacitance and a variable resistance. Table 1 below depicts an example truth table for an example variable impedance device (e.g., variable impedance device 100).

Resistance (RC)	Capacitor with a capacitor element	Impedance (L)
			RHeight of(VApplication of)	CHeight of(VApplication of)	ZHeight of(VApplication of)
RIs low in(VApplication of)	CIs low in(VApplication of)～0	ZIs low in(VApplication of)

TABLE 1

In a particular embodiment of the CES of fig. 1A, the CES may be placed in either of two different impedance states: a low impedance or conductive state in response to a set operation and a high impedance or insulating state in response to a reset operation. According to an embodiment, a CES may be placed in two or more distinguishable low impedance or conductive states in addition to a high impedance or insulating state. Likewise, the CES may be programmed in a write operation to be in any of three or more distinguishable impedance states. This may extend the use of CES to represent not only binary states.

FIG. 2 is a schematic diagram of a memory circuit according to an embodiment. The bit cell circuit 200 may include a memory element (e.g., a non-volatile memory element) including one or more of the CES devices. In this context, a "bit cell" or "bit cell circuitry" referred to herein includes a circuit or a portion of a circuit capable of representing a value, symbol, or parameter as a state. For example, a bit cell may include one or more memory devices capable of representing a value, symbol, or parameter as a memory state of the memory device. In particular embodiments, a bit cell may represent a value, symbol, or parameter as a single bit or as multiple bits.

According to an embodiment, the bit cell circuit 200 may include a memory element having behavior similar to that of the CES device discussed above in connection with fig. 1A. For example, the memory elements in the bit cell 200 can be placed into a particular memory state (e.g., two or more distinguishable conductive or low impedance memory states, or insulative or high impedance memory states) by independently controlling the voltage and current applied across the terminals of the memory cell in a "write operation. As discussed below in particular embodiments, such a write operation may be performed by applying a signal controlled to provide a critical current and voltage across terminals of the memory device to place the memory device in a particular memory state. In another embodiment, the memory state of the memory element in the bit cell 200 may be detected or sensed in a "read operation" by closing transistor M0 in response to the voltage drop of signal PRN to precharge the bit line BL to connect the bit line BL with a voltage RVDD of 0.4V. The transistor M0 may then be turned off in response to the voltage increase of the signal PRN, and then the transistor M3 may be turned on in response to the voltage increase of the signal RD _ Col _ Sel to connect the bit line BL to the sensing circuit 203. In this context, "bit line" includes such conductors: at least one terminal connectable to a memory element may be capable of sending a signal to change a memory state of the memory element during a write operation or to send a signal indicative of a current memory state of the memory element during a read operation. The sense circuit 203 may detect the memory state of the memory element in the bitcell 200 based on the magnitude of the current or voltage from the bitline BL through the transistor M3 in a read operation. The output signal may have a voltage (e.g., as a "1", "0", or other symbol) that indicates the current memory state of the bitcell 200. In one embodiment of a read operation, to detect the current memory state of a memory element, the voltage of the signal applied across the terminals of the memory element in bitcell 200 may be controlled so that the current memory state of the memory element is not changed by the detection.

Fig. 3A and 3B are directed to particular embodiments of a bitcell circuit including a CES device or element storing a particular memory state as an impedance state. While the following description provides a CeRAM device or non-volatile memory element as a specific example of a device in a bitcell capable of maintaining a memory state, it should be understood that these are merely example implementations. For example, it should be appreciated that CES suitable for purposes other than a non-volatile memory device or a CeRAM device may be used to store a particular memory state (e.g., two or more conductive or low impedance memory states, or an insulative or high impedance memory state) in a write operation that can be detected in a subsequent read operation, and claimed subject matter is not limited to implementations of CeRAM or non-volatile memory devices. Thus, the bit cell implementation of CES shown in fig. 3A and 3B may be viewed merely as an example implementation of CES, and various aspects of the present disclosure may be variously applied without departing from the claimed subject matter.

As noted above in fig. 1A, the memory state of a CES device in the bit-cell 200 may be changed or determined based on the particular voltage and current applied to the bit-line BL. For example, bit line BL is supplied with a voltage V_resetAnd a sufficient current I_resetMay place the CES device of the bit cell 200 in an insulating or high impedance memory state. Similarly, a bit line BL is supplied with a voltage V_setAnd a sufficient current I_setMay place the CES device of the bit cell 200 in a conductive or low impedance memory state. As can be seen from FIG. 1A, although the voltage V_setIs greater than the voltage V_resetBut the current I_setIs less than the current I_resetThe size of (2).

The write operation performed in conjunction with the write circuit 202 is described herein as a particular process of placing a memory device, such as a CES element, in a particular memory state of a plurality of predetermined memory states by applying a "program signal" to terminals of the memory device. A particular one of the predetermined memory states may correspond to a particular voltage level (e.g., V) to be applied to the memory device_setAnd V_reset). Similarly, a particular one of the predetermined memory states may correspond to a particular current level (e.g., I) to be applied to the memory device_setAnd I_reset). Therefore, in a particular implementationIn an example, a programming signal used to place a CES device in a particular memory state in a write operation may be controlled to have a particular voltage level and current level corresponding to the particular memory state.

As described in particular embodiments below, a voltage signal having a voltage level for a programming signal may be selected at a signal selection circuit based at least in part on a data signal to place a memory device in a predetermined memory state. The conductive element connected to the signal selection circuit may selectively connect or disconnect the voltage signal to or from the memory device at a current level corresponding to a predetermined memory state based at least in part on the data signal. In this context, a "conductive element" includes a circuit element that is capable of allowing current to pass between two nodes. In particular embodiments, the conductive element may alter the current allowed to pass between the nodes based at least in part on a particular condition. Certain embodiments described below employ FETs as conductive elements to allow current to pass between a source terminal and a drain terminal based at least in part on a voltage applied to a gate terminal. However, it should be understood that other types of devices, such as bipolar transistors, diodes, variable resistors, and the like, may also be used as conductive elements, and claimed subject matter is not limited in this respect. In this context, a conductive element having first and second terminals may "connect" the first and second terminals by providing a conductive path between the first and second terminals that has very little or negligible impedance for a particular signal. In one particular example embodiment, the conductive element may change an impedance between the first terminal and the second terminal based at least in part on a signal provided to a third terminal of the conductive element (e.g., based on a voltage or current applied to the third terminal). In one embodiment, the conductive element may "close" in response to a signal provided on the third terminal, thereby connecting the first terminal and the second terminal. Likewise, the conductive element may "open" in response to a different signal provided on the third terminal, thereby disconnecting the first terminal from the second terminal. In one embodiment, the conductive element in the open state may isolate the first portion of the circuit from the second portion of the circuit by removing or breaking a conductive path between the first portion and the second portion of the circuit. In another embodiment, the conductive element may change an impedance between the first terminal and the second terminal between an open state and a closed state based on a signal provided to the third terminal.

The specific example embodiments of fig. 3A and 3B, in conjunction with the example embodiment of fig. 2, are capable of providing a read voltage signal to a terminal of a non-volatile memory element or CES during a read operation. Here, the signal Wrt _ Col _ SeIN may be lowered during a read operation to close the FET M4 and connect the read voltage signal to the bit line BL (except for being lowered during a write operation to connect the program signal to the bit line BL). In an alternative embodiment (described below), a read voltage may be generated locally at bit cell 200 to be provided to a terminal of a memory element during a read operation. In this case, signal Wrt _ Col _ SeIN may be raised during the read operation to turn off the FET M4 signal and disconnect the write circuit from the bit line BL.

FIGS. 3A and 3B are schematic diagrams of alternative architectures for bitcells, consistent with certain embodiments. In a particular implementation of a read operation, a bit line may be connected to a terminal of a non-volatile memory (NVM) element through a first conductive element in response to a voltage signal on the word line. As noted above, "non-volatile memory" includes integrated circuit devices in which a memory cell or element retains its memory state (e.g., a conductive or low impedance memory state, or an insulative or high impedance memory state) after power to the device is removed. In this context, a "word line" includes a conductor used to transmit a signal to select a particular bit cell or group of bit cells to be accessed in a read operation or a write operation. In certain example embodiments, the voltage of a signal on a word line may be raised or lowered during a read or write operation to select or deselect a particular bit cell or group of bit cells to be connected to a corresponding bit line or group of bit cells. However, it should be understood that this is merely an example of a word line and claimed subject matter is not limited in this respect. Likewise, in this context, a "reference node" includes such nodes in a circuit: maintained at a particular voltage level or at a particular voltage difference with another node in the circuit. In one example, the reference node may include or be connected to a ground node. In other particular embodiments, the reference node may be maintained at a particular voltage relative to the voltage of the ground node.

According to an embodiment, in a first write operation to place an NVM element in a first memory state, a bit line may be connected to a first terminal of the NVM element through a conductive element in response to a voltage signal on the word line. In a first write operation, a programming signal having a first write voltage and a first write current may be applied across terminals of the NVM element to place the NVM element in a first memory state (e.g., an insulating or high impedance memory state). In a second write operation to place the NVM element in a second memory state, the bit line can be reconnected to the first terminal of the NVM element through the first conductive element in response to the voltage signal on the word line. The second write operation may apply a programming signal having a second write voltage and a second write current between terminals of the NVM element to place the NVM element in a second memory state (e.g., a particular conductive or low impedance memory state from among a plurality of distinguishable low impedance or conductive states). In particular embodiments, the NVM elements can include materials having one or more of the properties discussed above with reference to fig. 1A (where I is_reset|>|I_setWhen |, V |_reset|<|V_set|) CES element or CeRAM element. Accordingly, in the specific example shown in fig. 3A and 3B, the magnitude of the first write voltage may be greater than the magnitude of the second write voltage, and the magnitude of the first write current may be less than the magnitude of the second write current. After placing the NVM element in the second memory state, a third voltage (e.g., V) may be applied across the terminals of the NVM element in a read operation_read) To detect the current memory state of the NVM elements. When the third voltage is applied during the read operation, the current between the first terminal and the second terminal may be limited to be smaller than the magnitude of the first current(s) ((For example, | I_read|<|I_reset|) to maintain a second memory state (e.g., a conductive or low impedance memory state) of the NVM elements.

In one embodiment, NVM element 52 includes a CES element connected at a first terminal to FET M1 and at a second terminal to bit line BL 2. In response to a word line voltage WLB applied to the gate terminal of FET M1, M1 may connect the first terminal of NVM element 52 to bit line BL1 during a read or write operation. In one particular embodiment, the bit line BL2 may be connected to a reference node, such as a ground node (not shown). In other embodiments, the bit lines BL1 and BL2 may comprise complementary bit lines to apply an appropriate voltage (e.g., V) across the first and second terminals of NVM 52 during a write operation_setOr V_reset) And current (e.g. I)_setOr I_reset) To place NVM 52 in a desired memory state or to apply an appropriate voltage (e.g., V) in a read operation_read). In this particular example implementation, BL2 may be connected to the write circuit through additional conductive elements (not shown) in response to the word line signal voltage.

As noted above, the write circuitry can independently control the voltage and current of signals applied to NVM element 52 in a write operation based at least in part on whether the write operation placed NVM element 52 in a conductive or low impedance memory state or an insulative or high impedance memory state. For example, for a write operation that places NVM element 52 in a conductive or low impedance memory state, a voltage V may be applied_setAnd current I_setOf the signal of (1). Likewise, for a write operation that places NVM element 52 in an insulating or high impedance memory state, a voltage V may be applied_resetAnd current I_resetOf the signal of (1). As shown in fig. 1A, voltage V_setMay be greater than the voltage V_resetAnd current I_setMay be smaller than the current I_reset. As discussed above in particular embodiments, write circuit 202 may independently control voltage and current to provide bit line supply to place the non-volatile memory device in a conductive or low impedance memory stateA state or an isolated or high impedance state.

To detect the current memory state of the NVM element 52, M1 may connect the bit line BL1 to node 2 to apply a read voltage V across the first and second terminals of the NVM 52 in a read operation_read. When a read voltage V is applied_readThen, the current flowing through bit line BL1 may be sensed (e.g., at sensing circuitry 203) to detect the current state of NVM element 52. According to an embodiment, the magnitude of the current flowing through the terminals of NVM element 52 during a read operation may be limited to be less than I_resetThe size of (2). This may be to prevent the current state of NVM element 52 in a conductive or low impedance memory state from accidentally transitioning to an insulating or high impedance memory state during a read operation. The current flowing through the terminals of NVM element 52 during a read operation can be controlled, for example, by controlling the voltage applied to the gate of FET M1 during a read operation. In the particular embodiment of fig. 3B, FET M1 is configured as an NFET. Here, the increased word line voltage signal WL may be applied during a write operation to allow sufficient current to flow through the NVM element 52 to place the NVM element 52 in a particular memory state. The voltage of the word line voltage signal WL may then be reduced during a read operation to limit the current flowing through the NVM element 52. Alternatively, a voltage source (e.g., write circuit 202) that applies a read voltage to bit lines BL1 and/or BL2 may limit the current flowing to bit lines BL1 and/or BL2 during a read operation.

Fig. 4 is a relationship diagram illustrating operation of a CES according to an embodiment. In a particular embodiment, fig. 4 can characterize the operation of NVM element 52 under the control of write circuitry 202 and sense circuitry 203. As shown in the particular illustrated embodiment, the CES may be placed in any one of four different impedance states, one in a high impedance or insulating state and three in a different low impedance or conducting state. The CES of fig. 4 may be placed in a low impedance or conducting state by applying a programming signal having a voltage in region 414 in a set operation, or the CES of fig. 4 may be placed in a high impedance or insulating state by applying a programming signal having a voltage in region 412. In addition, as discussed below in particular embodiments, the CES of fig. 4 may also be placed in any of three different, distinguishable conductive or low impedance states.

As discussed above, the CES signal may be generated by applying a voltage V across the terminals of the CES_resetAnd current I_resetTo place the CES of fig. 4 in a high impedance or isolation state in a write operation. As noted above, to successfully place the CES of fig. 4 in a high impedance or insulating state in a reset operation, a programming signal applied to the CES may include a voltage V at the reset window 412_resetAnd a current I that exceeds a current previously programmed to place the CES of FIG. 4 in a low impedance or insulating state in a set operation_reset(e.g., current I)_resetBeyond Icomp1, Icomp2, and Icomp 3). The behavior of the CES of fig. 4 after such a reset operation that places the CES in a high impedance or insulating state may be modeled according to the relationship graph 422.

In addition, the set operation may place the CES of fig. 4 in either of two distinguishable low impedance or conductive states. Although fig. 4 illustrates that the CES may be placed in three different, distinguishable low impedance or conductive states, it should be understood that in other embodiments, the CES may be placed in two distinguishable low impedance or conductive states, or four or more distinguishable low impedance or conductive states, without departing from the claimed subject matter. In the presently illustrated embodiment, the CES of fig. 4 may be placed in any one of the three low impedance or conductive states in a set operation by applying a corresponding programming signal to exhibit the behavior depicted by curves 416, 418, or 420.

As noted above, CES may include a Correlated Electron Material (CEM) formed between terminals. In one embodiment, the different low impedance or conductive states of the CES may be distinguished, at least in part, by a density or concentration of electrons in the CEM formed between terminals of the CES after the set operation. Here, a higher electron density or electron concentration in the CEM formed in CES may impart a lower impedance or a higher conductivity. For example, a first low impedance or conductive state of a CES (e.g., after a first set operation) may have a first density or concentration of localized electrons in the CEM, while a second low impedance or conductive state of the CES (e.g., after a second set operation) may have a second density or concentration of electrons in the CEM. If the first density or concentration of electrons is higher than the second density or concentration of electrons, the first low impedance or conductive state may exhibit a higher conductivity/lower impedance than the second low impedance or conductive state. As discussed herein, the impedance difference of the first and second low impedance or conductive states may enable detection between different memory states (e.g., representing different values, parameters, conditions, or symbols).

According to an embodiment, a programming signal applied to a terminal of the CES of fig. 4 in a set operation may have a voltage V in a set window 414_set. To place the CES of fig. 4 in a particular, distinguishable, low impedance or conducting state (e.g., characterized by curves 416, 418, or 420), a programming signal in a set operation may apply a current Icomp1, Icomp2, or Icomp3 between terminals of the CES. For example, applying a current Icomp3 having a voltage V while maintaining a current Icomp3 between terminals of the CES of FIG. 4_setMay place the CES in an impedance state modeled by curve 420. Likewise, the current Icomp2 between the terminals of the CES of fig. 4 is maintained while applying a voltage V_setMay place the CES in an impedance state modeled by curve 418. Finally, a current Icomp1 is applied with a voltage V while maintaining the current Icomp1 between the terminals of the CES of fig. 4_setMay place the CES in an impedance state modeled by curve 416.

According to an embodiment, any of the four impedance states modeled by curves 416, 418, 420, or 422 may be modeled by applying a read voltage V at read window 402_readTo detect. According to an embodiment, a bit line having a voltage V may be applied in a read operation by connecting the precharged bit line (e.g., precharged by precharge circuit 201) to a terminal of the CES of fig. 4_readThe read signal of (1). A sensing circuit (e.g., sensing circuit 203) may detect or measure a current through the CES of fig. 4 in response to applying a read signal as current Ird1 at point 410, current Ird2 at point 408, current Ird3 at point 406, or Ird4 at point 404. Here, if responding to V_readIs detected or measured as Ird4 in the CES, it can be concluded that the CES of fig. 4 is in a high impedance or conductive state. Likewise, if the detected or measured current is at the corresponding current level, Ird1, Ird2 or Ird3, respectively, then the CES of fig. 4 may be inferred to be in a particular low impedance or conductive state modeled by curves 416, 418 or 420.

According to an embodiment, the different impedance states of the CES of fig. 4 modeled or depicted by the curves 416, 418, 420 or 422 may represent or map to four different symbols or values as shown in table 2 below. As shown in Table 2, the CES modeled or depicted by curves 416, 418, 420, or 422 in FIG. 4 may be responsive to application of V at Ron1/Ird1, Ron2/Ird2, Ron3/Ird3, or Ron4/Ird4, respectively, in a read operation_readBut with a detectable impedance/current. In one embodiment, depending on the particular symbol or value to be represented by the low impedance or conductive state, the write operation may apply a programming signal having a particular current Icomp1 (e.g., for CES to represent a symbol or value of "00"), a particular current Icomp2 (e.g., for CES to represent a symbol or value of "01"), or a particular current Icomp3 (e.g., for CES to represent a symbol or value of "10").

Detectable impedance/current	Symbol or value
		Ron1/Ird1	00
Ron2/Ird2	01
		Ron3/Ird3	10
Roff/Ird4	11

TABLE 2

Fig. 5 is a flow diagram of a process of applying operations to a CES having the behavior shown in fig. 4, according to an embodiment. Block 502 may include applying a programming signal to a terminal of a CES. Such programming signals may be generated by write circuitry, such as write circuitry 202. Here, the programming signal applied in block 502 may apply a voltage between terminals of the CES in the setup window 414 while maintaining a current between terminals of the CES at Icomp1, Icomp2, or Icomp3 (depending on the particular low impedance state the CES is to be placed in). In the particular embodiment of table 2, for example, the programming signal may maintain a current Icomp1, Icomp2, or Icomp3, depending on whether the CES represents a symbol or value of "00", "01", or "10".

Block 504 may include responding to the voltage V_readA read signal is applied on the CES terminal to detect or measure a current in the CES (e.g., at the sensing circuit 203). For example, a read signal may be applied by connecting a terminal of a CES to a precharged bit line (e.g., precharged by precharge circuit 201). Block 506 may then associate the current detected or measured at block 504 (e.g., Ird1, Ird2 or Ird3) with the associated low impedance or conductive state. As noted above, the associated low impedance or conductive state may also represent a particular symbol or value (e.g., "00," "01," or "10").

Reference throughout the specification to one embodiment, an example, an embodiment, etc., means that a particular feature, structure, and/or characteristic described in connection with the particular embodiment and/or example is included in at least one embodiment and/or example of claimed subject matter. Thus, for example, the appearances of such phrases in various places throughout this specification are not necessarily intended to refer to the same embodiment or any one particular embodiment described. Furthermore, it is to be understood that the particular features, structures, and/or characteristics described are capable of being combined in various ways in one or more embodiments and, thus, for example, are within the intended scope of the claims. Of course, these and other problems typically vary from context to context. Thus, the particular context of description and/or usage provides helpful guidance regarding inferences to be drawn.

While there has been shown and described what are presently considered to be example features, it will be understood by those skilled in the art that various other modifications may be made, and equivalents may be substituted, without departing from claimed subject matter. In addition, many modifications may be made to adapt a particular situation to the teachings of claimed subject matter without departing from the central concept described herein. Therefore, it is intended that claimed subject matter not be limited to the particular examples disclosed, but that such claimed subject matter may also include all aspects falling within the scope of the appended claims, and equivalents thereof.