阅读说明：本技术 检测半导体装置的故障的方法 (Method for detecting failure of semiconductor device ) 是由 崔芝影 詹瞻 金敏燮 金洲铉 姜成建 李化成 于 2019-03-14 设计创作，主要内容包括：提供了一种检测半导体装置的故障的方法,所述方法包括：在基底的有源区上形成有源鳍,所述有源鳍在第一方向上延伸；在有源鳍上形成栅极结构,所述栅极结构在与第一方向交叉的第二方向上延伸；在栅极结构的相对侧处的有源鳍的对应部分上形成源极/漏极层；形成电连接到源极/漏极层的布线；以及施加电压以测量源极/漏极层之间的漏电流。可以在有源区上形成仅一个或两个有源鳍。可以在有源鳍上形成仅一个或两个栅极结构。(There is provided a method of detecting a failure of a semiconductor device, the method including: forming an active fin on an active region of a substrate, the active fin extending in a first direction; forming a gate structure on the active fin, the gate structure extending in a second direction crossing the first direction; forming source/drain layers on corresponding portions of the active fin at opposite sides of the gate structure; forming a wiring electrically connected to the source/drain layer; and applying a voltage to measure a leakage current between the source/drain layers. Only one or two active fins may be formed on the active region. Only one or two gate structures may be formed on the active fin.)

1. A method of detecting a failure of a semiconductor device, the method comprising:

forming a first active fin and a second active fin on a first region and a second region of a substrate, respectively;

forming a first gate structure and a second gate structure on the first active fin and the second active fin, respectively;

forming a first source/drain layer on a corresponding portion of the first active fin at an opposite side of the first gate structure, and forming a second source/drain layer on a corresponding portion of the second active fin at an opposite side of the second gate structure;

forming a first wiring and a second wiring electrically connected to the first source/drain layer and the second source/drain layer, respectively; and

a leak current between the second source/drain layers is detected by applying a voltage to the second wiring,

wherein the first active fin is formed on the first active region in a first region of the substrate, the second active fin is formed on the second active region in a second region of the substrate, the first active region and the second active region have upper surfaces higher than upper surfaces of other portions located in the first region and the second region of the substrate, respectively, and

wherein only one or two second active fins are formed on the second active region.

2. The method of claim 1, wherein only one or two second gate structures are formed on the second active fin.

3. The method of claim 2, wherein one or more first active fins are formed on the first active region.

4. The method of claim 1, wherein one or more first active fins are formed on the first active region.

5. The method of claim 1, wherein each of the first and second active fins extends in a first direction and each of the first and second gate structures extends in a second direction that intersects the first direction.

6. The method of claim 5, wherein:

a plurality of second active regions are formed in the first direction, and

a distance between adjacent ones of the plurality of second active regions is equal to or greater than 30 times a width of the second active fin in the second direction.

7. The method of claim 5, wherein an extended length of the second active fin in the first direction is equal to or less than 30 times a width of the second active fin in the second direction.

8. The method of claim 1, wherein the first region is a chip region and the second region is a scribe line region separated from the first region in a separating operation.

9. The method of claim 1, wherein forming the first and second active fins comprises:

forming a first active fin and a second active fin by removing an upper portion of the substrate to form a first recess;

forming a second recess deeper than the first recess by removing portions of the first and second active fins and a portion of the substrate underlying the removed portions of the first and second active fins; and

an isolation pattern is formed on the substrate to fill a lower portion of the first recess and the second recess,

wherein the first active region and the second active region are defined by a second recess.

10. The method of claim 1, wherein forming a first gate structure and a second gate structure on the first active fin and the second active fin, respectively, comprises:

forming a first dummy gate structure and a second dummy gate structure on the first active fin and the second active fin, respectively;

forming an insulating interlayer on the substrate to cover the sidewalls of the first dummy gate structure and the second dummy gate structure;

removing the first dummy gate structure and the second dummy gate structure to form a first opening and a second opening, respectively; and

a first gate structure and a second gate structure are formed in the first opening and the second opening, respectively.

11. The method of claim 1, wherein forming the first and second source/drain layers comprises:

partially removing the first and second active fins to form third and fourth recesses, respectively; and

a selective epitaxial growth process is performed to form a first source/drain layer filling the third recess and a second source/drain layer filling the fourth recess, respectively.

12. The method of claim 2, further comprising the steps of:

forming a first contact plug and a second contact plug on the first source/drain layer and the second source/drain layer, respectively;

forming a first via and a second via on the first contact plug and the second contact plug, respectively;

forming third and fourth wirings on the first and second vias, respectively; and

a third via and a fourth via are formed on the third wiring and the fourth wiring respectively,

wherein the first wiring and the second wiring are formed on the third via and the fourth via, respectively.

13. A method of detecting a failure of a semiconductor device, the method comprising:

forming an active fin on an active region of a substrate, the active fin extending in a first direction;

forming a gate structure on the active fin, the gate structure extending in a second direction crossing the first direction;

forming source/drain layers on corresponding portions of the active fin at opposite sides of the gate structure;

forming a wiring electrically connected to the source/drain layer; and

a voltage is applied to measure the leakage current between the source/drain layers,

wherein only one or two active fins are formed on the active region, and

wherein only one or two gate structures are formed on the active fin.

14. The method of claim 13, wherein the plurality of active regions are formed to be spaced apart from each other in the first direction or the second direction.

15. The method of claim 14, wherein a distance between adjacent ones of the plurality of active regions is equal to or greater than 30 times a width of the active fin in the second direction.

16. The method of claim 13, wherein an extended length of the active fin in the first direction is equal to or less than 30 times a width of the active fin in the second direction.

17. The method of claim 13, wherein the active region of the substrate is formed in a scribe line region of the substrate.

18. The method of claim 13, wherein the active region of the substrate has an upper surface that is higher than an upper surface of other portions of the substrate.

19. A method of detecting a failure of a semiconductor device, the method comprising:

removing upper portions of the substrate spaced apart from each other in a second direction to form active fins extending in a first direction crossing the second direction;

removing a portion of the substrate and one or more of the active fins to form active regions spaced apart from each other in the first direction or the second direction, each of the active regions including ones of the active fins located thereon, at least one first one of the active regions including only one or two of the active fins located thereon;

forming a gate structure on the active fin, the gate structure extending in a second direction;

forming source/drain layers on corresponding portions of the active fin at opposite sides of the gate structure;

forming wirings electrically connected to the source/drain layers, respectively; and

applying a voltage to one or more of the wires electrically connected to the source/drain layers on the active fins located on the at least one first active area to measure a leakage current between the source/drain layers.

20. The method of claim 19, wherein only one or two gate structures are formed on the active fin on the at least one first active region.

Technical Field

Background

The malfunction of the semiconductor chip may be detected by chip Electrical characteristic Sorting (EDS). However, such processes may involve extended feedback times during product development.

Disclosure of Invention

Drawings

Features will become apparent to those skilled in the art by describing in detail example embodiments with reference to the accompanying drawings.

Fig. 1 to 27 show plan and cross-sectional views of stages in a method of manufacturing a semiconductor device and a method of detecting a failure according to example embodiments.

Fig. 28 shows a graph of the length of active fins and the number of active fins included in an active region versus the leakage current of a source/drain layer formed on the active fins.

Fig. 29 is a graph showing a relationship between a distance between active regions including active fins and a leakage current of a source/drain layer formed on the active fins.

Fig. 30 to 32 show plan views of semiconductor devices according to example embodiments.

Embodiments relate to a method of detecting a malfunction of a semiconductor apparatus.