阅读说明：本技术 三态门电路 (Three-state gate circuit ) 是由 胡曙敏 于 2019-10-21 设计创作，主要内容包括：本发明公开了一种三态门电路。三态门电路包括第一反相器、第一与非门、第二反相器、第一NMOS管和第一NMOS管。利用本发明提供的三态门电路可以得到三个稳定的电路状态,同时电路结构简单。(The invention discloses a tri-state gate circuit. The tri-state gate circuit comprises a first phase inverter, a first NAND gate, a second phase inverter, a first NMOS transistor and a first NMOS transistor. The three-state gate circuit provided by the invention can obtain three stable circuit states, and the circuit structure is simple.)

1. A tri-state gate circuit, characterized by: comprises a first inverter, a first NAND gate, a second inverter, and a first NMOS

The transistor and the first NMOS transistor;

the input end of the first phase inverter is connected with the input end A, and the output end of the first phase inverter is connected with the grid electrode of the first NMOS tube; one input end of the first NAND gate is connected with the input end A, the other input end of the first NAND gate is connected with the input end B, and the output end of the first NAND gate is connected with the input end of the second inverter; the input end of the second inverter is connected with the output end of the first NAND gate, and the output end of the second inverter is connected with the grid electrode of the second NMOS tube; the grid electrode of the first NMOS tube is connected with the output end of the first phase inverter, the drain electrode of the first NMOS tube is connected with a power supply voltage VCC, and the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube and serves as the output end OUT of the tri-state gate; the grid electrode of the second NMOS tube is connected with the output end of the second phase inverter, the drain electrode of the second NMOS tube is connected with the source electrode of the first NMOS tube and serves as the output end OUT of the tri-state gate, and the source electrode of the second NMOS tube is grounded.

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a tri-state gate circuit.

Background

In order to obtain three stable circuit states, a tri-state gate circuit with stable performance needs to be designed, and the circuit structure is simple.

Disclosure of Invention

The invention aims to solve the defects of the prior art and provides a tri-state gate circuit.

The tri-state gate circuit comprises a first phase inverter, a first NAND gate, a second phase inverter, a first NMOS transistor and a first NMOS transistor:

the input end of the first phase inverter is connected with the input end A, and the output end of the first phase inverter is connected with the grid electrode of the first NMOS tube; one input end of the first NAND gate is connected with the input end A, the other input end of the first NAND gate is connected with the input end B, and the output end of the first NAND gate is connected with the input end of the second inverter; the input end of the second inverter is connected with the output end of the first NAND gate, and the output end of the second inverter is connected with the grid electrode of the second NMOS tube; the grid electrode of the first NMOS tube is connected with the output end of the first phase inverter, the drain electrode of the first NMOS tube is connected with a power supply voltage VCC, and the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube and serves as the output end OUT of the tri-state gate circuit; the grid electrode of the second NMOS tube is connected with the output end of the second phase inverter, the drain electrode of the second NMOS tube is connected with the source electrode of the first NMOS tube and serves as the output end OUT of the tri-state gate circuit, and the source electrode of the second NMOS tube is grounded.

When the input end A of the tri-state gate circuit is at a low level and the input end B is at a low level, the grid of the first NMOS tube is at a high level, the grid of the second NMOS tube is at a low level, and the output end OUT of the tri-state gate circuit is at a high level; when the input end A of the tri-state gate circuit is at a low level and the input end B is at a high level, the grid of the first NMOS tube is at a high level, the grid of the second NMOS tube is at a low level, and the output end OUT of the tri-state gate circuit is at a high level; when the input end A of the tri-state gate circuit is at a high level and the input end B is at a low level, the grid of the first NMOS tube is at a low level, the grid of the second NMOS tube is at a low level, and the output end OUT of the tri-state gate circuit is at a high-impedance state; when the input end A of the tri-state gate circuit is at a high level and the input end B is at a high level, the grid of the first NMOS tube is at a low level, the grid of the second NMOS tube is at a high level, and the output end OUT of the tri-state gate circuit is at a low level. As an embodiment of the tri-state gate, three circuit output states may be implemented.

Drawings

FIG. 1 is a circuit diagram of a tri-state gate circuit of the present invention.

Detailed Description

The present invention will be further explained with reference to the accompanying drawings.

The tri-state gate circuit, as shown in fig. 1, includes a first inverter 10, a first nand gate 20, a second inverter 30, a first NMOS transistor 40, and a first NMOS transistor 50:

the input end of the first inverter 10 is connected with the input end A, and the output end is connected with the grid electrode of the first NMOS tube 40; one input end of the first nand gate 20 is connected to the input end a, the other input end is connected to the input end B, and the output end is connected to the input end of the second inverter 30; the input end of the second inverter 30 is connected with the output end of the first nand gate 20, and the output end is connected with the gate of the second NMOS transistor 50; the grid electrode of the first NMOS tube 40 is connected with the output end of the first phase inverter 10, the drain electrode is connected with a power supply voltage VCC, and the source electrode is connected with the drain electrode of the second NMOS tube 50 and serves as the output end OUT of the tri-state gate circuit; the gate of the second NMOS transistor 50 is connected to the output terminal of the second inverter 30, the drain is connected to the source of the first NMOS transistor 40 and serves as the output terminal OUT of the tri-state gate, and the source is grounded.

When the input end a of the tri-state gate circuit is at a low level and the input end B is at a low level, the gate of the first NMOS transistor 40 is at a high level, the gate of the second NMOS transistor 50 is at a low level, and the output end OUT of the tri-state gate circuit is at a high level; when the input end a of the tri-state gate circuit is at a low level and the input end B is at a high level, the gate of the first NMOS transistor 40 is at a high level, the gate of the second NMOS transistor 50 is at a low level, and the output end OUT of the tri-state gate circuit is at a high level; when the input end a of the tri-state gate circuit is at a high level and the input end B is at a low level, the gate of the first NMOS transistor 40 is at a low level, the gate of the second NMOS transistor 50 is at a low level, and the output end OUT of the tri-state gate circuit is at a high impedance state; when the input end a of the tri-state gate circuit is at a high level and the input end B is at a high level, the gate of the first NMOS transistor 40 is at a low level, the gate of the second NMOS transistor 50 is at a high level, and the output end OUT of the tri-state gate circuit is at a low level. As an embodiment of the tri-state gate, three circuit output states may be implemented.

The description of the embodiments provided above is merely illustrative of preferred embodiments of the present invention, and it will be apparent to those skilled in the art that the present invention can be implemented or used in light of the above description. It should be noted that, for those skilled in the art, it is possible to make several modifications and variations without departing from the technical principle of the present invention, and any invention that does not depart from the scope of the essential spirit of the present invention should be construed as the scope of the present invention.