阅读说明：本技术 一种三态门电路 (Three-state gate circuit ) 是由 孟庆生 于 2019-11-11 设计创作，主要内容包括：本发明公开了一种三态门电路。一种三态门电路包括第一反相器、第一或非门、第二反相器、第三反相器、第一与非门、第四反相器、第一PMOS管和第一NMOS管。利用本发明提供的三态门电路可以降低电路的复杂性,提高稳定性。(The invention discloses a tri-state gate circuit. A tri-state gate circuit comprises a first phase inverter, a first NOR gate, a second phase inverter, a third phase inverter, a first NAND gate, a fourth phase inverter, a first PMOS tube and a first NMOS tube. The tri-state gate circuit provided by the invention can reduce the complexity of the circuit and improve the stability.)

1. A tri-state gate circuit, comprising: comprises a first inverter, a first NOR gate, a second inverter, and a third inverter

The phase device comprises a phase device, a first NAND gate, a fourth phase inverter, a first PMOS tube and a first NMOS tube;

the input end of the first inverter is connected with the input end A, and the output end of the first inverter is connected with one input end of the first NOR gate and one input end of the first NAND gate; one input end of the first NOR gate is connected with the output end of the first inverter and one input end of the first NAND gate, the other input end of the first NOR gate is connected with the input end B, and the output end of the first NOR gate is connected with the input end of the second inverter; the input end of the second inverter is connected with the output end of the first NOR gate, and the output end of the second inverter is connected with the grid electrode of the first PMOS tube; the input end of the third inverter is connected with the input end B, and the output end of the third inverter is connected with one input end of the first NAND gate; one input end of the first NAND gate is connected with the output end of the first inverter and one input end of the first NOR gate, the other input end of the first NAND gate is connected with the input end of the third inverter, and the output end of the first NAND gate is connected with the input end of the fourth inverter; the input end of the fourth inverter is connected with the output end of the first NAND gate, and the output end of the fourth inverter is connected with the grid electrode of the first NMOS tube; the grid electrode of the first PMOS tube is connected with the output end of the second phase inverter, the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and serves as the output end OUT of the tri-state gate circuit, and the source electrode of the first PMOS tube is connected with a power supply voltage VCC; the grid electrode of the first NMOS tube is connected with the output end of the fourth inverter, the drain electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube and serves as the output end OUT of the tri-state gate circuit, and the source electrode of the first NMOS tube is grounded.

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a tri-state gate circuit.

Background

Tri-state gates are often encountered in integrated circuit design processes, and the complexity and stability of the circuits directly affect the performance and area of the chip.

Disclosure of Invention

The invention aims to solve the defects of the prior art and provides a tri-state gate circuit.

A tristate gate circuit comprises a first phase inverter, a first NOR gate, a second phase inverter, a third phase inverter, a first NAND gate, a fourth phase inverter, a first PMOS tube and a first NMOS tube:

the input end of the first inverter is connected with the input end A, and the output end of the first inverter is connected with one input end of the first NOR gate and one input end of the first NAND gate; one input end of the first NOR gate is connected with the output end of the first inverter and one input end of the first NAND gate, the other input end of the first NOR gate is connected with the input end B, and the output end of the first NOR gate is connected with the input end of the second inverter; the input end of the second inverter is connected with the output end of the first NOR gate, and the output end of the second inverter is connected with the grid electrode of the first PMOS tube; the input end of the third inverter is connected with the input end B, and the output end of the third inverter is connected with one input end of the first NAND gate; one input end of the first NAND gate is connected with the output end of the first inverter and one input end of the first NOR gate, the other input end of the first NAND gate is connected with the input end of the third inverter, and the output end of the first NAND gate is connected with the input end of the fourth inverter; the input end of the fourth inverter is connected with the output end of the first NAND gate, and the output end of the fourth inverter is connected with the grid electrode of the first NMOS tube; the grid electrode of the first PMOS tube is connected with the output end of the second phase inverter, the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and serves as the output end OUT of the tri-state gate circuit, and the source electrode of the first PMOS tube is connected with a power supply voltage VCC; the grid electrode of the first NMOS tube is connected with the output end of the fourth inverter, the drain electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube and serves as the output end OUT of the tri-state gate circuit, and the source electrode of the first NMOS tube is grounded.

When the input end A of the tri-state gate circuit is at a low level and the input end B is at a low level, the grid of the first PMOS tube is at a high level, the grid of the first NMOS tube is at a high level, and the output end OUT of the tri-state gate circuit is at a low level; when the input end A of the tri-state gate circuit is at a low level and the input end B is at a high level, the grid of the first PMOS tube is at a high level, the grid of the first NMOS tube is at a low level, and the output end OUT of the tri-state gate circuit is at a high-impedance state; when the input end A of the tri-state gate circuit is at a high level and the input end B is at a low level, the grid of the first PMOS tube is at a low level, the grid of the first NMOS tube is at a low level, and the output end OUT of the tri-state gate circuit is at a high level; when the input end A of the tri-state gate circuit is at a high level and the input end B is at a high level, the grid of the first PMOS tube is at a high level, the grid of the first NMOS tube is at a low level, and the output end OUT of the tri-state gate circuit is at a high-resistance state.

Drawings

FIG. 1 is a circuit diagram of a tri-state gate circuit of the present invention.

Detailed Description

The present invention will be further explained with reference to the accompanying drawings.

A tristate gate circuit, as shown in FIG. 1, comprises a first inverter 10, a first NOR gate 20, a second inverter 30, a third inverter 40, a first NAND gate 50, a fourth inverter 60, a first PMOS transistor 70 and a first NMOS transistor 80:

the input end of the first inverter 10 is connected to the input end a, and the output end is connected to an input end of the first nor gate 20 and an input end of the first nand gate 50; one input end of the first nor gate 20 is connected to the output end of the first inverter 10 and one input end of the first nand gate 50, the other input end is connected to the input end B, and the output end is connected to the input end of the second inverter 30; the input end of the second inverter 30 is connected with the output end of the first nor gate 20, and the output end is connected with the gate of the first PMOS transistor 70; the input end of the third inverter 40 is connected to the input end B, and the output end is connected to one input end of the first nand gate 50; one input of the first nand gate 50 is connected to the output of the first inverter 10 and one input of the first nor gate 20, the other input is connected to the input of the third inverter 40, and the output is connected to the input of the fourth inverter 60; the input end of the fourth inverter 60 is connected with the output end of the first nand gate 50, and the output end is connected with the gate of the first NMOS transistor 80; the grid electrode of the first PMOS tube 70 is connected with the output end of the second inverter 30, the drain electrode is connected with the drain electrode of the first NMOS tube 80 and serves as the output end OUT of the tri-state gate circuit, and the source electrode is connected with a power supply voltage VCC; the gate of the first NMOS transistor 80 is connected to the output terminal of the fourth inverter 60, the drain is connected to the drain of the first PMOS transistor 70 and serves as the output terminal OUT of the tri-state gate, and the source is grounded.

When the input end a of the tri-state gate circuit is at a low level and the input end B is at a low level, the gate of the first PMOS transistor 70 is at a high level, the gate of the first NMOS transistor 80 is at a high level, and the output end OUT of the tri-state gate circuit is at a low level; when the input end a of the tri-state gate circuit is at a low level and the input end B is at a high level, the gate of the first PMOS transistor 70 is at a high level, the gate of the first NMOS transistor 80 is at a low level, and the output end OUT of the tri-state gate circuit is at a high impedance state; when the input end a of the tri-state gate circuit is at a high level and the input end B is at a low level, the gate of the first PMOS transistor 70 is at a low level, the gate of the first NMOS transistor 80 is at a low level, and the output end OUT of the tri-state gate circuit is at a high level; when the input end a of the tri-state gate circuit is at a high level and the input end B is at a high level, the gate of the first PMOS transistor 70 is at a high level, the gate of the first NMOS transistor 80 is at a low level, and the output end OUT of the tri-state gate circuit is at a high impedance state.

The description of the embodiments provided above is merely illustrative of preferred embodiments of the present invention, and it will be apparent to those skilled in the art that the present invention can be implemented or used in light of the above description. It should be noted that, for those skilled in the art, it is possible to make several modifications and variations without departing from the technical principle of the present invention, and any invention that does not depart from the scope of the essential spirit of the present invention should be construed as the scope of the present invention.