阅读说明：本技术 非周期四相z互补序列对信号的生成方法及装置 (Method and device for generating aperiodic four-phase Z complementary sequence pair signal ) 是由 李国军 曾悦 曾凡鑫 张力生 叶昌荣 于 2019-10-10 设计创作，主要内容包括：本发明属于通信系统技术领域,具体涉及通信系统中非周期四相Z互补序列对信号的生成方法及装置；所述方法包括将一组零相关区宽度为Z的非周期二元Z互补序列对(<U>a</U>,<U>b</U>)输入至串并转换器；将串并转换后的每个序列元素对应输出至一个符号转换器中；符号转换器对输入的序列元素进行处理后,输出至相乘电路中；相乘电路产生三路输出；加法器将序列<U>a</U>中每个序列元素的三路输出数据与序列<U>b</U>中每个序列元素的三路输出数据进行交错叠加,产生非周期四相Z互补序列对的各个序列元素；采用并串转换器将非周期四相Z互补序列对的各个序列元素进行并串转换,从而输出非周期四相Z互补序列对；本发明可应用于信号处理、通信系统和大规模集成电路测试等。(The invention belongs to the technical field of communication systems, and particularly relates to a method and a device for generating a non-periodic four-phase Z complementary sequence pair signal in a communication system; the method comprises the following steps of (1) enabling a group of non-periodic binary Z complementary sequence pairs with zero correlation zone width of Z a ， b ) Inputting the data to a serial-to-parallel converter; correspondingly outputting each serial element after serial-parallel conversion to a symbol converter; the symbol converter processes the input sequence elements and outputs the processed sequence elements to the multiplying circuit; the multiplication circuit generates three paths of outputs; the adder will sequence a Three-way output data and sequence of each sequence element b The three paths of output data of each sequence element are staggered and superposed to generate each sequence element of the non-periodic four-phase Z complementary sequence pair; adopting a parallel-serial converter to carry out parallel-serial conversion on each sequence element of the non-periodic four-phase Z complementary sequence pair, thereby outputting the non-periodic four-phase Z complementary sequence pair; the invention can be applied to signal processing,Communication systems and large scale integrated circuit testing, etc.)

1. A method for generating an aperiodic four-phase Z-complement pair signal in a communication system, the method comprising the steps of:

s1, a group of non-periodic binary Z complementary sequence pairs with zero correlation zone width Z (a,b) Input to a serial-to-parallel converter for serial-to-parallel conversion, thereby converting the sequence into (A), (B), (C)a,b) The respective sequence elements of (a) are arranged in sequence;

s2, correspondingly outputting each serial element after serial-parallel conversion to a symbol converter;

s3, the symbol converter processes the input sequence elements and outputs the processed sequence elements to the multiplication circuit; the multiplication circuit generates three paths of outputs;

s4, adder will sequenceaThree-way output data and sequence of each sequence elementbThe three paths of output data of each sequence element are staggered and superposed to generate each sequence element of the non-periodic four-phase Z complementary sequence pair;

s5, adopting a parallel-serial converter to carry out parallel-serial conversion on each sequence element of the non-periodic four-phase Z complementary sequence pair, thereby outputting a non-periodic four-phase Z complementary sequence pair (u,v)。

2. The method of claim 1, wherein the symbol converter comprises an output of 1 when the input sequence element is "0", and an output of-1 when the input sequence element is "1".

3. The method of claim 1, wherein the multiplying circuit comprises three outputs formed by multiplying circuits corresponding to the first multiplying coefficient, the second multiplying coefficient and the third multiplying coefficient respectively; the sum of the first multiplication coefficient and the second multiplication coefficient is 1, and the first multiplication coefficient and the second multiplication coefficient are conjugate complex numbers; the input corresponding to the third multiplication coefficient is the output corresponding to the third multiplication coefficient, and the third multiplication coefficient is-1.

4. The method of claim 3, wherein the first multiplication factor isThe second multiplication coefficient is

5. The method as claimed in claim 1, wherein the step S4 includes generating the sequence of the non-periodic four-phase Z complementary sequence pair signalaThe first way output and sequence of the ith sequence element ofbThe second output of the N-i-1 th sequence element is superposed to form a sequence four-phase non-periodic four-phase Z complementary sequenceuThe 2 i-th sequence element of (1); will be sequencedaThe third path of the (N-i-1) th sequence element of (A) and the sequencebThe first output of the ith sequence element is superposed to form a sequence four-phase non-periodic four-phase Z complementary sequenceuThe 2i +1 th sequence element of (1); will be sequencedaThe first way output and sequence of the ith sequence element ofbThe third path outputs of the (N-i-1) th sequence elements are superposed to form a sequence four-phase non-periodic four-phase Z complementary sequencevThe 2 i-th sequence element of (1); will be sequencedaSecond output and sequence of the N-i-1 th sequence elementbThe first output of the ith sequence element is superposed to form a sequence four-phase non-periodic four-phase Z complementary sequencevThe 2i +1 th sequence element of (1); i ═ N-1 (0,1, · N); n represents the length of the aperiodic binary Z complementary sequence pair and is a positive integer.

6. An apparatus for generating aperiodic four-phase Z complementary sequence pair signal in communication system, which is characterized in that the apparatus comprises a time sequence control circuit and an aperiodic binary Z complementary sequence pair database, 2N output serial-parallel converters, 2N symbol converters, 2N groups of multiplication circuits, 4N adders, 4N input parallel-serial converters and an aperiodic four-phase Z complementary sequence pair database which are controlled by the time sequence control circuit and connected in sequence;

the time sequence control circuit is used for controlling the serial-parallel converter and the parallel-serial converter to be reset and controlling the other units to operate in sequence;

the aperiodic binary Z complementary sequence pair database is used for generating an aperiodic binary Z complementary sequence pair with the length of N;

the 2N output serial-parallel converters split 2N sequence elements of the non-periodic binary Z complementary sequence pair according to the sequence element arrangement order;

the symbol converter is used for converting the symbols output by the serial-parallel converter;

the multiplication circuit is used for generating 6N sequence elements;

the adder is used for performing staggered superposition on 6N sequence elements of the aperiodic four-phase Z complementary sequence pair to form 4N sequence elements of the aperiodic four-phase Z complementary sequence pair;

the 4N input parallel-serial converters perform parallel-serial conversion on 4N sequence elements of the aperiodic four-phase Z complementary sequence pair to form an aperiodic four-phase Z complementary sequence pair with the length of 2N;

the aperiodic four-phase Z-complement sequence pair database is used for storing aperiodic four-phase Z-complement sequence pairs with the length of 2N.

7. The apparatus of claim 6, wherein said sign converter comprises a multiplier and an adder connected in series.

8. The apparatus according to claim 6, wherein the multiplying circuit comprises three multipliers, and the three multipliers correspond to one output in sequence to form three outputs; the sum of a first multiplication coefficient of the first multiplier and a second multiplication coefficient of the second multiplier is 1, and the two multiplication coefficients are conjugate complex numbers; the input of the third multiplier is the output of the second multiplier and the third multiplication coefficient of the third multiplier is-1.

9. The apparatus of claim 6, wherein the 2 i-th adder adds a first output of an i-th multiplying circuit of the first N multiplying circuits to a second output of an N-i-1-th multiplying circuit of the last N multiplying circuits to form a 2 i-th sequence element of the first 2N elements of the aperiodic four-phase Z-complementary sequence pair, and the 2i + 1-th adder adds a third output of an N-i-1-th multiplying circuit of the first N multiplying circuits to a first output of an i-th multiplying circuit of the last N multiplying circuits to form a 2i + 1-th element of the first 2N elements of the aperiodic four-phase Z-complementary sequence pair; in the last 2N adders, the 2 i-th adder superposes the first output of the i-th multiplying circuit in the first N multiplying circuits and the third output of the N-i-1-th multiplying circuit in the last N multiplying circuits to form the 2 i-th sequence element in the last 2N elements of the non-periodic four-phase Z complementary sequence pair, and the 2i + 1-th adder superposes the second output of the N-i-1-th multiplying circuit in the first N multiplying circuits and the first output of the i-th multiplying circuit in the last N multiplying circuits to form the 2i + 1-th sequence element in the last 2N elements of the non-periodic four-phase Z complementary sequence pair; i ═ N-1 (0,1, · N); n represents the length of the aperiodic binary Z complementary sequence pair and is a positive integer.

Technical Field

The invention belongs to the technical field of communication systems, and relates to the field of generation of aperiodic four-phase Z complementary sequence pairs; in particular to a method and a device for generating a non-periodic four-phase Z complementary sequence pair signal in a communication system.

Background

The aperiodic Z complementary sequence pair is composed of two sequences with the same length, and is characterized in that the sum of the aperiodic autocorrelation functions of the two sequences has a zero correlation zone (abbreviated as ZCZ) near the time shift origin, is in the ZCZ zone, and has the characteristics like an impulse function. In particular, when the ZCZ region contains all of the out-of-phase correlation functions, the aperiodic Z-complementary sequence pair degenerates into a conventional aperiodic Z-complementary sequence pair, also known as golay complementary sequence pair. The number of aperiodic Z-complementary sequence pairs is much larger than golay complementary sequence pairs. The non-periodic complementary sequence pair is widely applied to the synchronization of communication, can also be used as a radar signal, and the like. In 2007, the concept of aperiodic binary Z-complementary sequence pairs was proposed (p.z.fan, w.n.yuan, and y.f.tu, "Z-complementary binding sequences," IEEE Signal process.lett., vol.14, No.8, pp.509-512, aug.2007). In 2010, the concept of aperiodic four-phase Z-Complementary sequence pairs was defined (x.d. Li, p.z. fan, x.h. tang, and l.hao, "quadraphase Z-Complementary Sequences", iecetrans.on Fundamentals, vol.e. 93-a, No.11, pp.2251-2257, nov.2010).

In recent years, aperiodic binary Z complementary sequence pairs are intensively studied, and the theory of richer aperiodic binary Z complementary sequence pairs is established. In 2011, the presence of aperiodic binary Z-complement pairs was discussed (x.li, p.fan, x.tang, and y.tu, "Existence of binding Z-complementarypair," IEEE signaling process.lett., vol.18, No.1, pp.63-66, jan.2011.). In 2014, characteristics and construction methods of non-periodic binary Z complementary sequence pairs of odd and even lengths were studied (z.liu, u.parampalli, and y.l.guan, "Optimal odd-length binary Z-complementary pairs", IEEE trans.inf.theory, vol.60, No.9, pp.5768-5781, sep.2014.) (z.liu, u.parampalli, and y.l.guan, "On even-periodic binary Z-complementary pairs with large zcs", IEEE signalprocess.lett., vol.21, No. 3, pp.284-287, mar.2014.). In 2017, Based on the Generalized Boolean function, a new method for constructing non-periodic Z Complementary sequences was proposed (C.Y. Chen, "A Novel Construction of Z-Complementary Pairs Based on Generalized Boolean Functions", IEEE SignalProcess.Lett., vol.24, No.7, pp.987-990, Jul.2017.). In 2018, aperiodic Binary Z Complementary sequence Pairs With large ZCZ regions were constructed (A.R. Adhikary, S.Maji, Z.L.Liu, Y.L.Guan, "New Sets of Even-Length Binary Z-Complementary Pair With asymmetric ZCZ Ratio of 3/4", IEEESignal Process. letter., vol.25, nno.7, pp.970-973, May 2018.).

In contrast, the aperiodic four-phase Z-complement pair is very weak to study. In 2010, the fundamental transformation of aperiodic four-phase Z-complement pairs was studied (x.d. li, p.z. fan, x.h. tang, and l.hao, "quadraphase Z-Complementary Sequences", ieee trans. on fundamental, vol.e93-a, No.11, pp.2251-2257, nov.2010). In 2016, a new aperiodic four-phase Z-complement pair was constructed by linear weighted combination of two aperiodic binary or four-phase Z-complement pairs (X.D.Li, W.H.Mow, and X.H.Niu, "New constraint of Z-complements," Electronics Letters, vol.52, No.8, pp.609-611, Apr.2016).

In short, the prior art has the defects of few construction methods for the aperiodic four-phase Z complementary sequence pair, incapability of generating all required lengths, complex construction process, difficult realization process and the like.

Disclosure of Invention

Based on the problems in the prior art, the invention aims to provide a method and a device for generating an aperiodic four-phase Z complementary sequence pair, which have simple structure and easy realization.

The invention provides a method for generating a non-periodic four-phase Z complementary sequence pair, which can convert the known non-periodic binary Z complementary sequence pair into the non-periodic four-phase Z complementary sequence pair, the length of the obtained sequence and the width of a ZCZ region are respectively increased by one time, the non-periodic autocorrelation function is twice of the binary sequence pair in even time shift and is all zero in odd time shift.

The invention relates to a method for generating a non-periodic four-phase Z complementary sequence pair signal in a communication system, which comprises the following steps:

s1, mixingA set of aperiodic binary Z complementary sequence pairs with zero correlation zone width of Z (a,b) Input to a serial-to-parallel converter for serial-to-parallel conversion, thereby converting the sequence into (A), (B), (C)a,b) The respective sequence elements of (a) are arranged in sequence;

s2, correspondingly outputting each serial element after serial-parallel conversion to a symbol converter;

s3, the symbol converter processes the input sequence elements and outputs the processed sequence elements to the multiplication circuit; the multiplication circuit generates three paths of outputs;

s4, adder will sequenceaThree-way output data and sequence of each sequence elementbThe three paths of output data of each sequence element are staggered and superposed to generate each sequence element of the non-periodic four-phase Z complementary sequence pair;

s5, adopting a parallel-serial converter to carry out parallel-serial conversion on each sequence element of the non-periodic four-phase Z complementary sequence pair, thereby outputting a non-periodic four-phase Z complementary sequence pair (u,v)。

In addition, based on the method of the invention, the invention also provides a device for generating the non-periodic four-phase Z complementary sequence pair signal in the communication system,

the device comprises a time sequence control circuit, a non-periodic binary Z complementary sequence pair database, 2N output serial-parallel converters, 2N symbol converters, 2N groups of multiplication circuits, 4N adders, 4N input parallel-serial converters and a non-periodic four-phase Z complementary sequence pair database, wherein the non-periodic binary Z complementary sequence pair database, the 2N output serial-parallel converters, the 2N symbol converters, the 2N groups of multiplication circuits, the 4N adders, the 4N input parallel-serial converters and the non-periodic four-phase Z complementary;

the time sequence control circuit is used for controlling the serial-parallel converter and the parallel-serial converter to be reset and controlling the other units to operate in sequence;

the aperiodic binary Z complementary sequence pair database is used for generating an aperiodic binary Z complementary sequence pair with the length of N;

the 2N output serial-parallel converters split 2N sequence elements of the non-periodic binary Z complementary sequence pair according to the sequence element arrangement order;

the symbol converter is used for converting the symbols output by the serial-parallel converter;

the multiplication circuit is used for generating 6N sequence elements;

the adder is used for performing staggered superposition on 6N sequence elements of the aperiodic four-phase Z complementary sequence pair to form 4N sequence elements of the aperiodic four-phase Z complementary sequence pair;

the 4N input parallel-serial converters perform parallel-serial conversion on 4N sequence elements of the aperiodic four-phase Z complementary sequence pair to form an aperiodic four-phase Z complementary sequence pair with the length of 2N;

the aperiodic four-phase Z-complement sequence pair database is used for storing aperiodic four-phase Z-complement sequence pairs with the length of 2N.

The invention has the beneficial effects that:

the invention arbitrarily selects the aperiodic binary Z complementary sequence pair with the length of N and the width of a zero correlation zone of Z as the seed pair of the invention, the sum of the aperiodic autocorrelation functions of the obtained aperiodic four-phase Z complementary sequence pair is twice of that of the seed pair in even time shift, and is all zero in odd time shift, and the zero correlation zone is 2Z. The invention can be applied to signal processing, communication system and large scale integrated circuit test, etc.

Drawings

FIG. 1 is a schematic block diagram of a method for generating a signal using an aperiodic four-phase Z-complement sequence according to the invention;

FIG. 2 is a schematic block diagram of a symbol converter in the method for generating a non-periodic four-phase Z complementary sequence pair signal according to the present invention;

fig. 3 is a schematic diagram of a circuit configuration of an apparatus for generating a non-periodic four-phase Z complementary sequence pair signal in a communication system according to the present invention;

FIG. 4 is another preferred circuit configuration diagram of the apparatus for generating a non-periodic four-phase Z complementary sequence pair signal in a communication system of the present invention;

FIG. 5 is a circuit flow diagram of an apparatus for generating a non-periodic four-phase Z complementary sequence pair signal in a communication system according to the present invention;

FIG. 6 is a block diagram of a symbol converter of an apparatus for generating a non-periodic four-phase Z-complement pair signal in a communication system of the present invention;

fig. 7 is a schematic diagram showing the structure of a multiplying circuit of the device for generating a non-periodic four-phase Z complementary sequence pair signal in the communication system of the present invention;

in the figure, 1, a time sequence control circuit, 2, an aperiodic binary Z complementary sequence pair database, 3, a serial-parallel converter, 4, a four-phase symbol generation circuit, 5, a parallel-serial converter and 6, an aperiodic four-phase Z complementary sequence pair database.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly and completely apparent, the technical solutions in the embodiments of the present invention are described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.

As shown in fig. 1, in an implementation manner, a method for generating an aperiodic four-phase Z complementary sequence pair signal in a communication system of the present invention includes the following steps:

s1, a group of non-periodic binary Z complementary sequence pairs with zero correlation zone width Z (a,b) Input to a serial-to-parallel converter for serial-to-parallel conversion, thereby converting the sequence into (A), (B), (C)a,b) The respective sequence elements of (a) are arranged in sequence;

s2, correspondingly outputting each serial element after serial-parallel conversion to a symbol converter;

s3, the symbol converter processes the input sequence elements and outputs the processed sequence elements to the multiplication circuit; the multiplication circuit generates three paths of outputs;

s4, adder will sequenceaThree-way output data and sequence of each sequence elementbThe three paths of output data of each sequence element are staggered and superposed to generate each sequence element of the non-periodic four-phase Z complementary sequence pair;

s5, adopting a parallel-serial converter to carry out parallel-serial conversion on each sequence element of the non-periodic four-phase Z complementary sequence pair, thereby outputting a non-periodic four-phase Z complementary sequence pair (u,v)。

In step S1, the aperiodic binary Z complementary sequence pair with length N and zero correlation zone width Z may be arbitrarily selected as the original data according to the user' S indexClear seed pairs, non-periodic binary Z complement pairs selected in this example (a,b) Ina＝(a₀,a₁,a₂,…,a_N-1)，b＝(b₀,b₁,b₂,…,b_N-1) (ii) a The total length of the aperiodic binary Z complementary sequence pair is 2N, and N is a positive integer.

Further, the symbol converter includes an output of the symbol converter being 1 when the input sequence element is "0", and an output of the symbol converter being-1 when the input sequence element is "1".

As an alternative, the sign converter employs a switching circuit.

As an alternative, the multiplying circuit includes three outputs formed by multiplying circuits corresponding to the first multiplying coefficient, the second multiplying coefficient and the third multiplying coefficient respectively; the sum of the first multiplication coefficient and the second multiplication coefficient is 1, and the first multiplication coefficient and the second multiplication coefficient are conjugate complex numbers; the input corresponding to the third multiplication coefficient is the output corresponding to the third multiplication coefficient, and the third multiplication coefficient is-1.

As a preferred embodiment, the first multiplication coefficient isThe second multiplication coefficient is j²＝-1。

As a preferred embodiment, the preferred process of interleaving the stacks in step S4 includes concatenating the sequencesaThe first way output and sequence of the ith sequence element ofbThe second output of the N-i-1 sequence element is superposed to form a sequence four-phase non-periodic four-phase Z complementary sequenceuThe 2 i-th sequence element of (1); will be sequencedaThe third path of the (N-i-1) th sequence element of (A) and the sequencebThe first output of the ith sequence element is superposed to form a sequence four-phase non-periodic four-phase Z complementary sequenceuThe 2i +1 th sequence element of (1); will be sequencedaTo (1) aFirst output and sequence of i sequence elementsbThe third path outputs of the (N-i-1) th sequence elements are superposed to form a sequence four-phase non-periodic four-phase Z complementary sequencevThe 2 i-th sequence element of (1); will be sequencedaSecond output and sequence of the N-i-1 th sequence elementbThe first output of the ith sequence element is superposed to form a sequence four-phase non-periodic four-phase Z complementary sequencevThe 2i +1 th sequence element of (1); i ═ N-1 (0, 1.,).

As an implementable manner, the present embodiment provides a generation apparatus of a non-periodic four-phase Z complementary sequence pair signal in a communication system, which, as shown in fig. 3, includes a timing control circuit 1, a non-periodic binary Z complementary sequence pair database 2, a serial-to-parallel converter 3, a four-phase symbol generation circuit 4, a parallel-to-serial converter 5, and a non-periodic four-phase Z complementary sequence pair database 6.

In the device, a time sequence control circuit 1 clears a serial-parallel converter 3 and a parallel-serial converter 5, and then controls circuit units 2, 3, 4, 5 and 6 to orderly finish the work of the unit from left to right.

The timing control circuit 1 controls the seed pair (a,b) Input to a serial-to-parallel converter 3, the storage circuit of the serial-to-parallel converter 3 storing the sequence elements or symbols a sequentially from top to bottom₀,a₁,a₂,…,a_N-1,b₀,b₁,b₂,…,b_N-1The serial-to-parallel converter 3 has 2N outputs in total.

As a preferred embodiment, this embodiment provides a preferred generation apparatus of aperiodic four-phase Z complementary sequence pair signal in a communication system, as shown in fig. 4, the apparatus includes a timing control circuit, and an aperiodic binary Z complementary sequence pair database, 2N output serial-to-parallel converters, 2N symbol converters, 2N groups of multiplication circuits, 4N adders, 4N input parallel-to-serial converters, and an aperiodic four-phase Z complementary sequence pair database, which are controlled by the timing control circuit and connected in sequence.

The time sequence control circuit is used for controlling the serial-parallel converter and the parallel-serial converter to be reset and controlling the other units to operate in sequence;

the aperiodic binary Z complementary sequence pair database is used for generating an aperiodic binary Z complementary sequence pair with the length of N;

the 2N output serial-parallel converters split 2N sequence elements of the non-periodic binary Z complementary sequence pair according to the sequence element arrangement order;

the symbol converter is used for converting the symbols output by the serial-parallel converter;

the multiplication circuit is used for generating 6N sequence elements;

the adder is used for performing staggered superposition on 6N sequence elements of the aperiodic four-phase Z complementary sequence pair to form 4N sequence elements of the aperiodic four-phase Z complementary sequence pair;

the 4N input parallel-serial converters perform parallel-serial conversion on 4N sequence elements of the aperiodic four-phase Z complementary sequence pair to form an aperiodic four-phase Z complementary sequence pair with the length of 2N;

the aperiodic four-phase Z-complement sequence pair database is used for storing aperiodic four-phase Z-complement sequence pairs with the length of 2N.

As an implementation manner, as shown in fig. 5, in the first 2N adders, the 2 i-th adder adds a first output of the i-th multiplying circuit in the first N multiplying circuits and a second output of the N-i-1-th multiplying circuit in the last N multiplying circuits to form a 2 i-th sequence element in the first 2N elements of the aperiodic four-phase Z complementary sequence pair, and the 2i + 1-th adder adds a third output of the N-i-1-th multiplying circuit in the first N multiplying circuits and a first output of the i-th multiplying circuit in the last N multiplying circuits to form a 2i + 1-th element in the first 2N elements of the aperiodic four-phase Z complementary sequence pair; in the last 2N adders, the 2 i-th adder superposes the first output of the i-th multiplying circuit in the first N multiplying circuits and the third output of the N-i-1-th multiplying circuit in the last N multiplying circuits to form the 2 i-th sequence element in the last 2N elements of the aperiodic four-phase Z complementary sequence pair, and the 2i + 1-th adder superposes the second output of the N-i-1-th multiplying circuit in the first N multiplying circuits and the first output of the i-th multiplying circuit in the last N multiplying circuits to form the 2i + 1-th sequence element in the last 2N elements of the aperiodic four-phase Z complementary sequence pair; i ═ N-1 (0,1, · N); n represents the length of the aperiodic binary Z complementary sequence pair and is a positive integer.

Optional, input u of parallel-to-serial converter_2i＝c_i0+d_N-1-i,1，u_2i+1＝d_i0+c_N-1-i,2，v_2i＝c_i0+d_N-1-i,2， v_2i+1＝d_i0+c_N-1-i,1(i＝0,1,2,…,N-1)；

As an implementation, the sign converter includes a multiplier and an adder connected in series as shown in fig. 5.

As an implementation manner, as shown in fig. 6, the multiplication circuit includes three multipliers, and the three multipliers correspond to one output in sequence, so as to form three outputs; the sum of a first multiplication coefficient of the first multiplier and a second multiplication coefficient of the second multiplier is 1, and the two multiplication coefficients are conjugate complex numbers; the input of the third multiplier is the output of the second multiplier and the third multiplication coefficient of the third multiplier is-1.

Code element a_iThe first output of the multiplication circuit corresponding to (i ═ 0,1,2, …, N-1) is denoted as c_i,0The second output is denoted c_i,1And the third output is denoted as c_i,2Code element b_iThe first output of the multiplication circuit corresponding to (i ═ 0,1,2, …, N-1) is denoted as d_i,0The second output is denoted as d_i,1And the third output is denoted as d_i,2That is to say that,

wherein j is²＝-1；

In addition, the symbols are interleaved and superimposed by an adder to generate u_2i＝c_i0+d_N-1-i,1， u_2i+1＝d_i0+c_N-1-i,2，v_2i＝c_i0+d_N-1-i,2，v_2i+1＝d_i0+c_N-1-i,1(i＝0,1,2,…,N-1) Are respectively used as the input of the parallel-serial converter 5 and are stored in the corresponding u_k(k ═ 0,1,2 …,2N-1) and v_k(k＝0,1,2…,2N-1)。

Further, under the control of the timing control circuit 1, the sequence output by the first 2N parallel-to-serial converters 5 is taken as the sequence u, and the sequence output by the second 2N parallel-to-serial converters is taken as the sequence v, so as to form a sequence pair (b) ((c))u,v) Namely, the invention uses a seed pair (a,b) (ii) the resulting aperiodic four-phase Z complementary sequence pairu,v) The sequence pairs may be fed into the aperiodic four-phase Z-complement sequence pair database 6 for storage.

In a preferred embodiment, under the control of the timing control circuit 1, the circuit operation of the generating device is finished, or returns to the process of generating the aperiodic binary Z complementary sequence pair by the aperiodic binary Z complementary sequence pair database 2, and the required aperiodic four-phase Z complementary sequence pair is continuously generated and stored according to the control circuit units, i.e. the process of generating the aperiodic binary Z complementary sequence pair database 2, the serial-parallel converter 3, the four-phase symbol generating circuit 4, the parallel-serial converter 5 and the aperiodic four-phase Z complementary sequence pair database 6.

To illustrate the effectiveness of the aperiodic four-phase Z-complement sequence generated by the present invention, the present invention provides the following derivation process, including:

the outputs of the multiplication circuits corresponding to the respective symbols are calculated as follows:

thus, further obtained is:

note the booka'＝(a_N-1,a_N-2,…,a₁,a₀)，b'＝(b_N-1,b_N-2,…,b₁,b₀)；

Thus, there is an aperiodic correlation function:

thus, the sequence pair (u,v) The aperiodic autocorrelation function of (a) is:

C_u,u(2τ₀)＝C_a,a(τ₀)+C_b,b(τ₀)(τ₀＝0,1,2,…,N-1)

C_u,u(2τ₀+1)＝0(τ₀＝0,1,2,…,N-1)

C_v,v(2τ₀)＝C_a,a(τ₀)+C_b,b(τ₀)(τ₀＝0,1,2,…,N-1)

C_v,v(2τ₀+1)＝0(τ₀＝0,1,2,…,N-1)

finally, obtain

Obviously, when the seed is paired with (a,b) Is a sequence pair (N, ZCZ) generated by the invention when the non-periodic binary Z complementary sequence pair with the length of N, ZCZ and the width of Z isu,v) That is, an aperiodic four-phase Z-complementary sequence pair of length 2N, ZCZ and width 2Z.

For ease of understanding, the present embodiment gives a specific example for illustration.

Taking an aperiodic binary Z complementary sequence pair (18 in length and 13 in ZCZ zone width Z)a,b) As a seed pair.

a＝[1，0，0，0，1，0，0，1，0，1，0，1，1，1，0，0，0，1]；

b＝[0，0，0，0，1，1，1，0，1，1，0，1，1，0，1，1，1，1]；

(a,b) The sum of the aperiodic autocorrelation function is:

C_a,a(τ)+C_b,b(τ)＝(36，0，0，0，0，0，0，0，0，0，0，0，0，4，-4，-4，-4，0)

according to the inventive method, a four-phase Z complementary sequence pair (N-36) of non-periodic length is generatedu,v) Is composed ofu＝[-1，1，j，j，j，j，j，j，-j，-j，j，-j，j，-j，-j，j，j，-j，-1，-1，1，1， -1，-1，-1，-1，-1，1，1，-1，1，-1，1，-1，-j，-j]

v＝[-j，j，1，1，1，1，1，1，-1，-1，1，-1，1，-1，-1，1，1，-1，-j，-j， j，j，-j，-j，-j，-j，-j，j，j，-j，j，-j，j，-j，-1，-1]

The sum of the aperiodic autocorrelation functions is:

C_u,u(τ)+C_v,v(τ)＝(72，0，0，0，0，0，0，0，0，0，0，0，0，0，0，0，0，0，0，0，0，0，0，0，0，0，8，0，-8，0，-8，0，-8，0，0，0)。

has a ZCZ zone width of 26.

It is understood that, in the present invention, some features of the sequence-to-signal generation method and the generation apparatus can be mutually cited, and the present invention is not exemplified for the sake of space saving.

Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer readable storage medium, and the storage medium may include: ROM, RAM, magnetic or optical disks, and the like.

The above-mentioned embodiments, which further illustrate the objects, technical solutions and advantages of the present invention, should be understood that the above-mentioned embodiments are only preferred embodiments of the present invention, and should not be construed as limiting the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.