阅读说明：本技术 一种基于fpga的零中频二次雷达直流偏置补偿算法 (Zero intermediate frequency secondary radar direct current offset compensation algorithm based on FPGA ) 是由 杨见 杨珍 蒋鑫 刘永刚 于 2019-09-16 设计创作，主要内容包括：本发明涉及信号处理领域,公开了一种基于FPGA的零中频二次雷达直流偏置补偿算法,本发明根据二次雷达系统中噪声、信号的特性,建立相应的数据模型,并设计一种数据甄别滑窗,对输入的基带数据类型(噪声或者信号)进行识别,准确提取出基带数据中I/Q路携带的直流偏置并实时消除。本发明在ADC输出的数据未饱和的前提下,实时、高效、准确的还原基带数据中信号的幅相特性；在确保不会对系统带来其他不利影响的同时,解决由直流偏置带来的系统识别概率下降、虚警率高、探测精度降低等问题,提升二次雷达设备的可靠性。(The invention relates to the field of signal processing, and discloses a zero intermediate frequency secondary radar direct current offset compensation algorithm based on an FPGA (field programmable gate array). according to the characteristics of noise and signals in a secondary radar system, a corresponding data model is established, a data discrimination sliding window is designed, the type (noise or signal) of input baseband data is identified, and direct current offset carried by an I/Q (input/output) path in the baseband data is accurately extracted and eliminated in real time. The invention can effectively and accurately restore the amplitude-phase characteristics of signals in baseband data in real time on the premise that data output by the ADC is not saturated; the problems of system identification probability reduction, high false alarm rate, detection precision reduction and the like caused by direct current bias are solved while other adverse effects on the system are avoided, and the reliability of secondary radar equipment is improved.)

1. The utility model provides a zero intermediate frequency secondary radar DC offset compensation algorithm based on FPGA which characterized in that includes:

step 1: establishing a corresponding noise data model and a corresponding signal data model according to the characteristics of noise data and signal data in a secondary radar system;

step 2: designing a data type discrimination sliding window model according to the noise data model and the signal data model, wherein a data cache space is arranged in the data type discrimination sliding window model, and a bias attribute is defined for each group of data input into the data cache space;

and step 3: sequentially inputting N groups of zero intermediate frequency secondary radar baseband data into a data type discrimination sliding window model, transferring N groups of data into an original cache library for caching, and then identifying and judging the types of the N groups of input data according to the offset attribute of the input data; n is a natural number more than or equal to 1;

and 4, step 4: if the noise data exist in the N groups of input data judged in the sliding window, the noise data are moved into a noise cache library from an original cache library for caching;

if signal data exist in the N groups of input data judged in the sliding window, the signal data are removed from an original cache library; after the signal data are eliminated, noise mean value of the noise data in the noise buffer library at the previous moment is calculated to be used as substitute data of the signal data, and the substitute data is transferred into the noise buffer library for buffering;

and 5: calculating the mean value of all noise data in the current noise cache library, and defining the mean value as a direct current offset value carried in current secondary radar baseband data;

step 6: and subtracting the quantization values of the N groups of secondary radar baseband data before being input into the sliding window model from the extracted direct current offset value to eliminate the direct current offset and output data.

2. The FPGA-based zero intermediate frequency secondary radar DC offset compensation algorithm according to claim 1, wherein in the step 1, the noise data model and the signal data model comprise: and the secondary radar system receives a noise model, a secondary radar response signal model and a noise model carrying direct current offset in channel baseband data.

3. The FPGA-based zero intermediate frequency secondary radar DC offset compensation algorithm according to claim 1, wherein in the step 2, the detailed process of defining the offset attribute is as follows:

when the input data is larger than the noise maximum positive offset value, indicating that the input data is positive offset;

when the input data is smaller than the maximum negative bias value of the noise, the input data is represented as negative bias;

when the input data is greater than the noise maximum negative bias value and less than the noise maximum positive bias value, the input data is neither positively nor negatively biased.

4. The FPGA-based zero intermediate frequency secondary radar DC offset compensation algorithm of claim 3, wherein the process of calculating the maximum positive offset value and the maximum negative offset value of the noise is divided into two cases:

if the noise data does not exist in the current noise cache library, the initial noise data group is input in a user-defined mode and the average value of the initial noise data group is obtained to serve as the initial noise average value; extracting maximum noise data in the custom noise data group as an initial noise maximum value; extracting minimum noise data in the custom noise data group as an initial noise minimum value;

the expression of the initial noise maximum positive offset value is:

NMPO_init＝MAX_noise+AVA_noise；

the expression for the maximum negative bias value of the initial noise is:

NMNO_init＝MIN_noise-AVA_noise；

wherein, NMPO_initRepresenting the maximum positive offset value of the initial noise, NMNO_initRepresenting the maximum negative offset, AVA, of the initial noise_noiseRepresenting the initial noise mean, MAX_noiseRepresenting the initial noise maximum, MIN_noiseRepresents the initial noise minimum;

if the noise data exists in the current noise cache library, averaging the noise data in the current noise cache library to be used as a real-time noise average value;

the expression of the maximum positive offset value of the real-time noise is as follows:

x_MPO(n)＝m_N(n)+NMPO_init；

the expression of the maximum negative offset value of the real-time noise is as follows:

x_MNO(n)＝m_N(n)-NMNO_init；

wherein x is_MPO(n) represents the maximum positive offset value of real-time noise, x_MNO(n) represents the maximum negative bias value of real-time noise, m_N(n) means real time noise mean, NMPO_initRepresenting the maximum positive offset value of the initial noise, NMNO_initRepresenting the initial noise maximum negative bias value.

5. The FPGA-based zero intermediate frequency secondary radar DC offset compensation algorithm according to claim 1, wherein in the step 3, the detailed process for identifying and determining the data type is as follows:

if the N groups of input data are all represented as positive bias or negative bias in the sliding window, the N groups of input data are all noise data carrying direct current bias;

if the N groups of input data are not represented as positive offset or negative offset in the sliding window, the N groups of input data are all noise data which do not carry direct current offset;

if the N groups of input data are partially presented as positive bias and partially presented as negative bias in the sliding window, and the rest of the input data are not presented as positive bias or negative bias, the signal data in the N groups of input data are present.

6. The FPGA-based zero intermediate frequency secondary radar DC offset compensation algorithm as claimed in claim 5, wherein in the detailed data determination process, if the data is identified to carry the DC offset, a cancellation flag is set on the data to indicate the state of the DC cancellation process.

7. The FPGA-based zero intermediate frequency secondary radar DC offset compensation algorithm as recited in claim 1, wherein the data type discrimination sliding window model has a sliding window width larger than an effective pulse width of a secondary radar response signal.

8. The FPGA-based zero intermediate frequency secondary radar DC offset compensation algorithm as claimed in claim 1, wherein the algorithm is described by Verilog language and configured into FPGA for implementation.

Technical Field

The invention relates to the field of signal processing, in particular to a zero intermediate frequency secondary radar direct current offset compensation algorithm based on an FPGA.

Background

Zero Intermediate Frequency (ZIF) architectures have emerged since the inception of the radio, which have the advantages of lowest cost, lowest power consumption, and smallest size. With the development of scientific technology, a plurality of common defects existing in the early stage of a zero intermediate frequency architecture can be solved through the combination of process, design, partition and algorithm, so that a new product brought by the method achieves breakthrough in performance, the novel application of the traditional technology which is expected to be dusty can be realized, and inevitably, some problems also exist in the zero intermediate frequency architecture, including flicker noise (1/f), direct current offset (DC-offset), I/Q imbalance, even harmonic and the like. Only the problem and solution of dc biasing is described herein.

The zero intermediate frequency receiver converts the radio frequency signal to zero intermediate frequency, a large amount of bias voltage can deteriorate the signal, and more seriously, the direct current bias signal can cause the saturation of the mixing rear stage, signal distortion and the like.

Local oscillator leakage appears as an increased dc offset in the I or Q signal path. The reason for this is that the LO is coupled directly into the radio frequency signal path and is down-converted to the output in a coherent manner. The result is a mixer product, which appears as a dc offset, added to any residual dc offset present in the signal chain, as shown in fig. 1.

The isolation between the local oscillator port, the mixer port and the LNA is poor, local oscillator signals, environmental electromagnetic interference signals and the like can directly pass through the LNA and the mixer, and the phenomenon that local oscillator leakage occurs is that the coupled local oscillator signals and interference signals reach the mixer through the LNA due to coupling of a capacitor and a substrate in a chip and are mixed (self-mixing) with the input local oscillator signals, so that direct current components are generated behind the low-pass filter; in the approximate case of fig. 1(b), the signal from the LNA, the jammer signal, is coupled to the local oscillator input of the mixer, thereby producing a dc component.

The method for eliminating the direct current offset comprises a mode of compensating data by using an algorithm calibration and a demodulation chip calibration compensation interface, a mode of combining the algorithm calibration and the demodulation chip calibration compensation interface, and the like.

The blind calibration method of representative TI company is briefly described.

Direct current accumulation:

updating the direct current bias:

ΔOffset＝2^-shift·Offset_ACC

updating and counting direct current offset:

Offset_(n+1)＝Offset_(n)+ΔOffset

DC offset compensation:

y(i)＝x(i)-Offset(n)

the way in which the demodulation chip self-calibration interface is used for compensation is shown in fig. 2.

The existing scheme for solving the problem of direct current offset is basically based on direct statistics of baseband data, channel direct current offset extraction and one-time or cyclic compensation.

The defect of a one-off compensation mode is very obvious, and fixed parameter compensation can only solve the direct current bias caused by local oscillator leakage to a certain extent, but cannot solve the direct current bias caused by factors such as equipment electromagnetic environment change and the like.

The cyclic compensation method needs to extract the dc offset accurately, and needs to count a large amount of data to implement the cyclic compensation method, so that the dc cancellation process is slow, and the influence of the signal on the dc offset extraction cannot be avoided, which causes an error between the actually obtained dc offset value and the true value, which is shown in the dc cancellation effect that a small offset may still exist after the cancellation is completed, that is, the cancellation is not thorough.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: aiming at the existing problems, the zero intermediate frequency secondary radar direct current offset compensation algorithm based on the FPGA is provided, a corresponding model is established according to the characteristics of noise and signals in a secondary radar system, a data discrimination sliding window is designed, the type (noise and signals) of input data is identified, direct current offset carried by an I/Q path in baseband data is accurately extracted and eliminated in real time, and the reliability and the stability of equipment are improved.

The technical scheme adopted by the invention is as follows: the utility model provides a zero intermediate frequency secondary radar DC offset compensation algorithm based on FPGA which characterized in that includes:

step 1: establishing a corresponding noise data model and a corresponding signal data model according to the characteristics of noise data and signal data in a secondary radar system;

step 2: designing a data type discrimination sliding window model according to the noise data model and the signal data model, wherein a data cache space is arranged in the data type discrimination sliding window model, and a bias attribute is defined for each group of data input into the data cache space;

and step 3: sequentially inputting N groups of zero intermediate frequency secondary radar baseband data into a data type discrimination sliding window model, transferring N groups of data into an original cache library for caching, and then identifying and judging the types of the N groups of input data according to the offset attribute of the input data; n is a natural number more than or equal to 1;

and 4, step 4: if the noise data exist in the N groups of input data judged in the sliding window, the noise data are moved into a noise cache library from an original cache library for caching;

if signal data exist in the N groups of input data judged in the sliding window, the signal data are removed from an original cache library; after the signal data are eliminated, noise mean value of the noise data in the noise buffer library at the previous moment is calculated to be used as substitute data of the signal data, and the substitute data is transferred into the noise buffer library for buffering;

and 5: calculating the mean value of all noise data in the current noise cache library, and defining the mean value as a direct current offset value carried in current secondary radar baseband data;

step 6: and subtracting the quantization values of the N groups of secondary radar baseband data before being input into the sliding window model from the extracted direct current offset value to eliminate the direct current offset and output data.

Further, in step 1, the noise data model and the signal data model include: and the secondary radar system receives a noise model, a secondary radar response signal model and a noise model carrying direct current offset in channel baseband data.

Further, in step 2, the detailed process of defining the bias attribute is as follows:

when the input data is larger than the noise maximum positive offset value, indicating that the input data is positive offset;

when the input data is smaller than the maximum negative bias value of the noise, the input data is represented as negative bias;

when the input data is greater than the noise maximum negative bias value and less than the noise maximum positive bias value, the input data is neither positively nor negatively biased.

Further, the process of calculating the maximum positive offset and the maximum negative offset of the noise is divided into two cases:

if the noise data does not exist in the current noise cache library, the initial noise data group is input in a user-defined mode and the average value of the initial noise data group is obtained to serve as the initial noise average value; extracting maximum noise data in the custom noise data group as a noise maximum value; extracting minimum noise data in the custom noise data group as a noise minimum value;

the expression of the maximum noise positive offset value is as follows:

NMPO_init＝MAX_noise+AVA_noise；

the expression of the maximum negative offset value of the noise is as follows:

NMNO_init＝MIN_noise-AVA_noise；

wherein, NMPO_initRepresenting the maximum positive offset value of the initial noise, NMNO_initRepresenting the maximum negative offset, AVA, of the initial noise_noiseRepresenting the mean value of the noise, MAX_noiseRepresenting the initial noise maximum, MIN_noiseRepresents the initial noise minimum;

if the noise data exists in the current noise cache library, averaging the noise data in the current noise cache library to be used as a real-time noise average value;

the expression of the maximum positive offset value of the real-time noise is as follows:

x_MPO(n)＝m_N(n)+NMPO_init；

the expression of the maximum negative offset value of the real-time noise is as follows:

x_MNO(n)＝m_N(n)-NMNO_init；

wherein x is_MPO(n) represents the maximum positive offset value of real-time noise, x_MNO(n) represents the maximum negative bias value of real-time noise, m_N(n) means real time noise mean, NMPO_initRepresenting the maximum positive offset value of the initial noise, NMNO_initRepresenting the initial noise maximum negative bias value.

Further, in step 3, the detailed process of data determination is as follows:

if the N groups of input data are all represented as positive bias or negative bias in the sliding window, the N groups of input data are all noise data carrying direct current bias;

if the N groups of input data are not represented as positive offset or negative offset in the sliding window, the N groups of input data are all noise data which do not carry direct current offset;

if the N groups of input data are partially presented as positive bias and partially presented as negative bias in the sliding window, and the rest of the input data are not presented as positive bias or negative bias, the signal data in the N groups of input data are present.

Further, in the detailed process of the data determination, if it is identified that the data carries the dc offset, a cancellation flag is set on the data to indicate a state of the dc cancellation process.

Further, the width of a sliding window of the data type discrimination sliding window model is larger than the effective pulse width of the secondary radar response signal.

Furthermore, the algorithm is described by a Verilog language and is configured into an FPGA for implementation.

Compared with the prior art, the beneficial effects of adopting the technical scheme are as follows: aiming at the defects of the existing direct current bias processing scheme, the invention provides a direct current bias accurate compensation algorithm based on an FPGA (field programmable gate array), which can be used for efficiently and accurately restoring the amplitude-phase characteristics of signals in baseband data in real time on the premise that data output by an ADC (analog to digital converter) is not saturated, ensuring that other adverse effects on a system are not brought, solving the problems of reduced system identification probability, high false alarm rate, reduced detection accuracy and the like caused by direct current bias and improving the reliability of secondary radar equipment.

Drawings

Fig. 1(a) and 1(b) are schematic diagrams of dc offset generation for zero-if architecture;

FIG. 2 is a schematic diagram of a demodulation chip self-calibration interface compensation mode;

FIG. 3 is a DC compensation algorithm architecture based on FPGA of the present invention;

FIG. 4 is a secondary radar response signal format;

FIG. 5 is a simulation diagram of the process of eliminating DC offset by the present algorithm.

Detailed Description

The invention is further described below with reference to the accompanying drawings.