阅读说明：本技术 时钟信号产生电路及其操作方法 (Clock signal generating circuit and operating method thereof ) 是由 张全仁 李文明 于 2018-10-31 设计创作，主要内容包括：本发明公开了一种时钟信号产生电路及其操作方法,时钟信号产生电路的操作方法包含以下步骤：由电压侦测器传送时钟信号至时钟树电路；以及依据时钟树电路的电压调整时钟信号的频率以维持电压于电压范围内。本发明的时钟信号产生电路及其操作方法,可稳定时钟树电路的操作电压,并稳定数据输出时间。(The invention discloses a clock signal generating circuit and an operation method thereof, wherein the operation method of the clock signal generating circuit comprises the following steps: transmitting a clock signal from the voltage detector to the clock tree circuit; and adjusting the frequency of the clock signal according to the voltage of the clock tree circuit to maintain the voltage within the voltage range. The clock signal generating circuit and the operation method thereof can stabilize the operation voltage of the clock tree circuit and stabilize the data output time.)

1. A method of operating a clock signal generation circuit, comprising:

transmitting a clock signal from the voltage detector to the clock tree circuit; and

adjusting the frequency of the clock signal according to the voltage of the clock tree circuit to maintain the voltage within a voltage range.

2. The method of operation of claim 1, further comprising:

increasing the frequency of the clock signal when the voltage is above an upper voltage threshold; and

reducing the frequency of the clock signal when the voltage is below a voltage lower threshold.

3. The method of operation of claim 1, wherein the voltage is an operating voltage of the clock tree circuit.

4. The method of operation of claim 1, further comprising:

the clock signal is generated by a signal generation circuit.

5. The method of operation of claim 1, further comprising:

the voltage of the clock tree circuit is detected by the voltage detector.

6. A clock signal generation circuit, comprising:

a clock tree circuit; and

a voltage detector coupled to the clock tree circuit, wherein the voltage detector is used for transmitting a clock signal to the clock tree circuit;

wherein the voltage detector adjusts the frequency of the clock signal according to the voltage of the clock tree circuit to maintain the voltage within a voltage range.

7. The clock signal generation circuit of claim 6, wherein the voltage detector is further configured to increase the frequency of the clock signal when the voltage is above an upper voltage threshold and to decrease the frequency of the clock signal when the voltage is below a lower voltage threshold.

8. The clock signal generation circuit of claim 6, wherein the voltage is an operating voltage of the clock tree circuit.

9. The clock signal generation circuit of claim 6, wherein the voltage detector comprises:

the signal generating circuit is used for generating the clock signal.

10. The clock signal generation circuit of claim 6, wherein the voltage detector is further configured to detect the voltage of the clock tree circuit.

Technical Field

The present invention relates to a clock signal generating circuit and an operating method thereof, and more particularly, to a clock signal generating circuit of a Delay Locked Loop (DLL) and an operating method thereof.

Background

When the operating frequency of the clock signal generating circuit (e.g., DRAM) is high, the data output time (tAC) becomes less stable. Stabilizing the voltage of the clock tree is a common method of stabilizing the output time. Therefore, how to stabilize the voltage of the clock tree is one of the problems to be solved in the art.

Disclosure of Invention

The present invention provides a method for stabilizing the operating voltage of a clock tree circuit and stabilizing the operation of a data output clock signal generation circuit.

An aspect of the present invention is to provide a method of operating a clock signal generating circuit. The operation method comprises the following steps: transmitting a clock signal from the voltage detector to the clock tree circuit; and adjusting the frequency of the clock signal according to the voltage of the clock tree circuit to maintain the voltage within a voltage range.

In some embodiments, the method for operating the clock signal generating circuit further includes: when the voltage is higher than the upper voltage limit threshold value, increasing the frequency of the clock signal; and reducing the frequency of the clock signal when the voltage is below the voltage lower threshold.

In some embodiments, the voltage is an operating voltage of the clock tree circuit.

In some embodiments, the method for operating the clock signal generating circuit further includes: the clock signal is generated by a signal generating circuit.

In some embodiments, the method for operating the clock signal generating circuit further includes: the voltage of the clock tree circuit is detected by a voltage detector.

Another aspect of the present invention is to provide a clock signal generating circuit. The clock signal generating circuit includes a clock tree circuit and a voltage detector. The voltage detector is coupled to the clock tree circuit, wherein the voltage detector is used for transmitting the clock signal to the clock tree circuit. The voltage detector adjusts the frequency of the clock signal according to the voltage of the clock tree circuit to maintain the voltage within a voltage range.

In some embodiments, the voltage detector is further configured to increase the frequency of the clock signal when the voltage is higher than the upper voltage threshold, and to decrease the frequency of the clock signal when the voltage is lower than the lower voltage threshold.

In some embodiments, the voltage is an operating voltage of the clock tree circuit.

In some embodiments, the voltage detector comprises: the signal generating circuit is used for generating a clock signal.

In some embodiments, the voltage detector is further configured to detect a voltage of the clock tree circuit.

Therefore, in some embodiments, a clock signal generating circuit and an operating method thereof are provided to stabilize an operating voltage of a clock tree circuit and stabilize a data output time (tAC).

Drawings

The above and other objects, features, and advantages of the present invention will become more apparent from the following description of the embodiments taken in conjunction with the accompanying drawings in which:

FIG. 1 is a schematic diagram of a clock signal generation circuit according to some embodiments of the invention; and

FIG. 2 is a graph of experimental data according to some embodiments of the present invention; and

fig. 3 is a flow chart of a method of operating a clock signal generation circuit according to some embodiments of the invention.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. The elements and configurations of the specific examples are used in the following discussion to simplify the present invention. Any examples discussed are intended for illustrative purposes only and do not limit the scope or meaning of the invention or its illustrations in any way. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, which are included for simplicity and clarity and do not in themselves dictate a relationship between the various embodiments and/or configurations discussed below.

The term (terms) used throughout the specification and claims has the ordinary meaning as commonly understood in each term used in the art, in the disclosure herein, and in the specific context, unless otherwise indicated. Certain terms used to describe the invention are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing the invention.

As used herein, to "couple" or "connect" may mean that two or more elements are in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, and to "couple" or "connect" may also mean that two or more elements are in step or action with each other.

It will be understood that the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections. These elements, components, regions, layers and/or regions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. As used herein, the word "and/or" includes any combination of one or more of the associated listed items. Reference to "and/or" in this document refers to any combination of any, all, or at least one of the elements of the list.

Please refer to fig. 1. Fig. 1 is a schematic diagram of a clock signal generating circuit 100 according to some embodiments of the invention. The clock signal generating circuit 100 includes a clock tree circuit 110 and a voltage detector 130. In some embodiments of the present invention, the voltage detector 130 is coupled to the clock tree circuit 110.

In operational relation, the voltage detector 130 is used to detect the voltage of the clock tree circuit 110 and transmit the clock signal CLK to the clock tree circuit 110. The voltage detector 130 adjusts the frequency of the clock signal CLK according to the voltage to maintain the voltage within a voltage range.

In some embodiments of the present invention, the voltage detected by the voltage detector 130 is the operating voltage VDD of the clock tree circuit 110. In some embodiments of the present invention, the voltage detector 130 is further configured to increase the frequency of the clock signal CLK when the detected voltage is higher than the upper voltage threshold, and decrease the frequency of the clock signal CLK when the voltage is lower than the lower voltage threshold.

Please refer to fig. 2. Fig. 2 is a graph 200 of experimental data according to some embodiments of the present invention. The curve V1 represents the voltage detected by the voltage detector 130. The curve CLK represents the clock signal output by the voltage detector 130. In some embodiments of the present invention, the curve V1 represents the operating voltage VDD of the clock tree circuit 110 as shown in FIG. 1.

As shown in fig. 2, since at the time point t₁When the voltage V1 is lower than the lower threshold VLT, the voltage detector 130 decreases the frequency of the clock signal CLK. When the frequency of the clock signal CLK is decreased, the current flowing through the clock tree circuit 110 is decreased and the power consumption of the clock tree circuit 110 is also decreased. After the power consumption of the clock tree circuit 110 is reduced, the voltage VDD (as shown in fig. 1) is increased, and the voltage V1 detected by the voltage detector 130 is also increased.

On the other hand, since at the time point t₂When the voltage V1 is higher than the upper voltage threshold VUT, the voltage detector 130 increases the frequency of the clock signal CLK. When the frequency of the clock signal CLK increases, the current flowing through the clock tree circuit 110 increases and the power consumption of the clock tree circuit 110 also increases. After the power consumption of the clock tree circuit 110 increases, the voltage VDD (as shown in fig. 1) also decreases, and the voltage V1 detected by the voltage detector 130 also decreases.

Therefore, in some embodiments of the present invention, the voltage VDD can be maintained within a voltage range, that is, the voltage VDD can be maintained between the upper voltage threshold VUT and the lower voltage threshold VLT.

In some embodiments of the invention, the upper voltage threshold VUT is 2V and the lower voltage threshold VLT is 1V. In some embodiments of the present invention, the frequency of the clock signal CLK is between 800MHz and 3200 MHz. The values of the upper voltage threshold VUT, the lower voltage threshold VLT and the frequency of the clock signal CLK are merely used for illustration, and the embodiments of the present invention are not limited thereto.

Please refer to fig. 1 again. In some embodiments of the present invention, the voltage detector 130 comprises a signal generating circuit 135. The signal generating circuit 135 is used for generating a clock signal CLK.

In some embodiments of the present invention, the clock signal generation circuit 100 further comprises a receiver 150, a DLL (delay locked loop) circuit 170, and an output circuit 190. The receiver 150 is coupled to the DLL circuit 170, the DLL circuit 170 is coupled to the clock tree circuit 110, and the clock tree circuit 110 is coupled to the output circuit 190.

In operational relationship, the receiver 150 receives the clock source signal CSS and transmits a receiver signal to the DLL circuit 170 according to the clock source signal CSS. The DLL circuit 170 receives the receiver signal and transmits the DLL signal to the clock tree circuit 110 according to the receiver signal. The clock tree circuit 110 receives the DLL signal and the clock signal CLK, and the clock tree circuit 110 transmits the clock tree signal to the output circuit 190. The output circuit 190 outputs the output clock signal according to the clock tree signal.

It should be noted that the clock signal generating circuit 100 may be included in a storage device, such as DDR (double data rate), SDRAM (synchronous dynamic random access memory), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM or any other device including a clock signal generating circuit.

Please refer to fig. 3. Fig. 3 is a flow chart of a method 300 of operating the clock signal generation circuit 100 according to some embodiments of the invention. The method of operation 300 includes the steps of:

s310: transmitting a clock signal to the clock tree circuit; and

s330: the frequency of the clock signal is adjusted according to the voltage of the clock tree circuit to maintain the voltage within the voltage range.

For convenience of illustration and understanding, please refer to fig. 1 and fig. 3 together. The above steps are for illustration purposes. Additional steps are also within the contemplated scope of embodiments of the present invention.

In step S310, a clock signal is transmitted to the clock tree circuit. In some embodiments of the present invention, step S310 may be performed by the voltage detector 130. For example, the voltage detector 130 detects an operating voltage VDD of the clock tree circuit 110 as illustrated in fig. 1, and the voltage detector 130 transmits the clock signal CLK to the clock tree circuit 110 according to the detected voltage.

In step S330, the frequency of the clock signal is adjusted according to the voltage of the clock tree circuit to maintain the voltage within the voltage range. In some embodiments of the present invention, the step S330 may be performed by the voltage detector 130. For example, when the voltage is detected to be higher than the upper voltage threshold, the voltage detector 130 increases the frequency of the clock signal CLK, and when the voltage is lower than the lower voltage threshold, the voltage detector 130 decreases the frequency of the clock signal CLK.

Please refer to fig. 2 and fig. 3. Due to the fact that at the time point t₁When the voltage V1 is lower than the lower threshold VLT, the voltage detector 130 decreases the frequency of the clock signal CLK. When the frequency of the clock signal CLK is decreased, the current flowing through the clock tree circuit 110 is decreased and the power consumption of the clock tree circuit 110 is also decreased. After the power consumption of the clock tree circuit 110 is reduced, the voltage VDD (as shown in fig. 1) is increased, and the voltage V1 detected by the voltage detector 130 is increased.

On the other hand, since at the time point t₂When the voltage V1 is higher than the upper voltage threshold VUT, the voltage detector 130 increases the frequency of the clock signal CLK. When the frequency of the clock signal CLK increases, the current flowing through the clock tree circuit 110 increases, and the power consumption of the clock tree circuit 110 increases. After the power consumption of the clock tree circuit 110 increases, the voltage VDD (as shown in fig. 1) decreases, and the voltage V1 detected by the voltage detector 130 also decreases.

Therefore, in some embodiments of the present invention, the voltage VDD can be maintained within a voltage range, that is, the voltage VDD can be maintained between the upper voltage threshold VUT and the lower voltage threshold VLT. In addition, since the operating voltage VDD of the clock tree circuit 110 is stable, the data output time (tAC) of the clock signal generating circuit 100 is also stable.

Additionally, the above illustration includes exemplary steps in sequential order, but the steps need not be performed in the order shown. It is within the contemplation of the invention to perform these steps in a different order. Steps may be added, substituted, changed in order, and/or omitted as appropriate within the spirit and scope of embodiments of the present invention.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.