阅读说明：本技术 一种多芯片堆叠封装结构及其制作方法 (Multi-chip stacking packaging structure and manufacturing method thereof ) 是由 李恒甫 曹立强 于 2019-08-29 设计创作，主要内容包括：本发明提供一种多芯片堆叠封装结构及其制作方法。上述多芯片堆叠封装结构包括：转接板,开设有贯通其正面与背面的硅通孔,所述转接板的背面开设有凹槽；第一芯片,通过第一塑封体封装在所述凹槽内；重布线结构,设置在所述转接板靠近背面的一侧,且分别与所述第一芯片和所述硅通孔电连接；第二芯片,设置在所述转接板靠近正面的一侧,且通过所述硅通孔与所述重布线结构电连接。通过转接板设置的凹糟,使第一芯片与第二芯片处于转接板不同空间位置,故第一芯片和第二芯片的封装总尺寸可以超出转接板尺寸,拓展封装空间；第一芯片无需通过硅通孔与重布线结构连接,降低了封装难度、提升了封装可行性,节约了生产成本及工序,适于大规模加工与生产。(The invention provides a multi-chip stacking packaging structure and a manufacturing method thereof. The above multi-chip stack package structure includes: the adapter plate is provided with a through silicon hole penetrating through the front surface and the back surface of the adapter plate, and the back surface of the adapter plate is provided with a groove; the first chip is packaged in the groove through the first plastic packaging body; the rewiring structure is arranged on one side, close to the back surface, of the adapter plate and is electrically connected with the first chip and the silicon through hole respectively; and the second chip is arranged on one side of the adapter plate close to the front surface and is electrically connected with the rewiring structure through the silicon through hole. The first chip and the second chip are positioned at different spatial positions of the adapter plate through the grooves arranged on the adapter plate, so that the total packaging size of the first chip and the second chip can exceed the size of the adapter plate, and the packaging space is expanded; the first chip is not required to be connected with the rewiring structure through the silicon through hole, the packaging difficulty is reduced, the packaging feasibility is improved, the production cost and the working procedures are saved, and the method is suitable for large-scale processing and production.)

1. A multi-chip stacked package structure, comprising:

the adapter plate (1) is provided with a through silicon hole (2) which penetrates through the front surface and the back surface of the adapter plate, and the back surface of the adapter plate (1) is provided with a groove (3);

the first chip (4) is packaged in the groove (3) through a first plastic packaging body (5);

the rewiring structure is arranged on one side, close to the back surface, of the adapter plate (1) and is electrically connected with the first chip (4) and the through silicon via (2) respectively;

and the second chip (6) is arranged on one side, close to the front, of the adapter plate (1) and is electrically connected with the rewiring structure through the through silicon via (2).

2. The multi-chip stack package structure of claim 1, further comprising:

a first insulating dielectric layer (10) having a front surface encapsulating a first conductive pad (11) and a back surface encapsulating a second conductive pad (12), the first conductive pad (11) and the second conductive pad (12) being connected by a first conductive transfer structure encapsulated in the first insulating dielectric layer (10), the second conductive pad (12) being electrically connected to the through-silicon via (2);

and the welding structure (13) is electrically connected with the second chip (6) at one end and electrically connected with the first conductive pad (11) at the other end.

3. The multi-chip stack package structure of claim 1 or 2, wherein the rewiring structure comprises:

a second insulating dielectric layer (15) having a front surface encapsulating a third conductive pad (16) and a back surface encapsulating a fourth conductive pad (17), the third conductive pad (16) and the fourth conductive pad (17) being connected by a second conductive transfer structure encapsulated in the second insulating dielectric layer (15), the third conductive pad (16) being electrically connected to the through-silicon via (2) and the first chip (4), respectively;

and the external solder ball (18) is electrically connected with the fourth conductive pad (17).

4. The multi-chip stacked package structure according to any one of claims 1-3, wherein the front surface of the first chip (4) faces the opening direction of the recess (3), and the front surface of the first chip (4) is connected to the rewiring structure (6) through a fifth conductive pad (7).

5. The multi-chip stack package structure according to any of claims 1-4, further comprising a second molding compound (14) encapsulating the second chip (6).

6. A method of fabricating a multi-chip stack package structure according to any of claims 1-5, comprising:

providing an adapter plate (1), wherein a through silicon hole (2) penetrating through the front surface and the back surface of the adapter plate (1) is formed in the adapter plate (1), and a groove (3) is formed in the back surface of the adapter plate (1);

manufacturing a conductive interconnection structure on one side, close to the front surface, of the adapter plate (1), wherein the conductive interconnection structure is electrically connected with the through silicon via (2);

placing a first chip (4) in the groove (3), and manufacturing a first plastic package body (5) to encapsulate the first chip (4);

a rewiring structure is manufactured on one side, close to the back surface, of the adapter plate (1), and the rewiring structure is electrically connected with the silicon through hole (2) and the first chip (4);

and placing a second chip (6) on one side of the conductive interconnection structure, which is deviated from the silicon through hole (2), and connecting the second chip (6) with the silicon through hole (2) through the conductive interconnection structure.

7. The method of claim 6, further comprising: and manufacturing a second plastic packaging body (14) to encapsulate the second chip (6).

8. The method of claim 6 or 7, wherein the conductive interconnect structure comprises:

connecting a second conductive pad (12) on the through silicon via (2);

connecting a first conductive transfer structure on the second conductive pad (12);

a first conductive pad (11) is connected on the first conductive transfer structure.

9. The method of fabricating a multi-chip stack package structure according to any one of claims 6-8, wherein the method of fabricating the rewiring structure comprises:

manufacturing third conductive pads (16) on the first chip (4) and the through silicon via (2) respectively;

connecting a second conductive transfer structure on the third conductive pad (16);

connecting a fourth conductive pad (17) on the second conductive transfer structure;

and manufacturing an external solder ball (18) on the fourth conductive pad (17).

10. The method of fabricating a multi-chip stack package structure according to any of claims 6-9, wherein the method of connecting the second chip (6) to the through-silicon-via (2) comprises:

manufacturing a welding structure (13) on the front surface of the second chip (6);

and welding the welding structure (13) with the conductive interconnection structure.

Technical Field

The invention relates to the technical field of semiconductor packaging, in particular to a multi-chip stacking packaging structure and a manufacturing method thereof.

Background

The multi-chip integration is an important technical means for realizing the multi-functionalization of products, the multi-chip integration package is rapidly developed along with the requirement of the multi-functionalization of electronic products, and the multi-chip package is required to be developed towards the system integration, high speed, high frequency, three-dimensional and ultrathin directions. Tsv (through silicon via) technology is an abbreviation of through silicon via technology, generally referred to as "through silicon via" technology for short, and is a new technical solution for implementing interconnection of stacked chips in a three-dimensional integrated circuit, and is called as the 4 th generation packaging technology after wire bonding, tape bonding (TAB), and Flip Chip (FC). The TSV packaging technology can meet the requirements of high density, small size and large output terminal I/O quantity of multiple chips, can realize high integration, and can meet the product packaging requirements of the characteristics of high performance, low delay, high frequency, large bandwidth and the like.

Disclosure of Invention

Therefore, the technical problem to be solved by the present invention is to overcome the defects that the size and the number of chips are limited by the size of the surface of the interposer and the packaging space is limited because the chip packaging in the existing interposer packaging technology is a planar packaging, thereby providing a multi-chip stacked package structure and a manufacturing method thereof.

A first aspect of the present invention provides a multi-chip stacked package structure, comprising:

the adapter plate is provided with a through silicon hole penetrating through the front surface and the back surface of the adapter plate, and the back surface of the adapter plate is provided with a groove;

the first chip is packaged in the groove through the first plastic packaging body;

the rewiring structure is arranged on one side, close to the back surface, of the adapter plate and is electrically connected with the first chip and the silicon through hole respectively;

and the second chip is arranged on one side of the adapter plate close to the front surface and is electrically connected with the rewiring structure through the silicon through hole.

Further, the multi-chip stacked package structure further comprises:

a first insulating dielectric layer, wherein a first conductive pad is encapsulated on the front surface of the first insulating dielectric layer, a second conductive pad is encapsulated on the back surface of the first insulating dielectric layer, the first conductive pad and the second conductive pad are connected through a first conductive transfer structure encapsulated in the first insulating dielectric layer, and the second conductive pad is electrically connected with the through silicon via;

and one end of the welding structure is electrically connected with the second chip, and the other end of the welding structure is electrically connected with the first conductive pad.

Further, the rewiring structure includes:

a second insulating dielectric layer, wherein a front surface of the second insulating dielectric layer is encapsulated with a third conductive pad, a back surface of the second insulating dielectric layer is encapsulated with a fourth conductive pad, the third conductive pad and the fourth conductive pad are connected through a second conductive transfer structure encapsulated in the second insulating dielectric layer, and the third conductive pad is electrically connected with the through silicon via and the first chip respectively;

and the external solder ball is electrically connected with the fourth conductive pad.

Further, the front surface of the first chip faces the opening direction of the groove, and the front surface of the first chip is connected with the rewiring structure through a fifth conductive pad.

Furthermore, the multi-chip stack package structure further comprises a second plastic package body for packaging the second chip.

The second aspect of the present invention provides a method for manufacturing the above multi-chip stacked package structure, including:

providing an adapter plate, wherein a through silicon hole penetrating through the front surface and the back surface of the adapter plate is formed in the adapter plate, and a groove is formed in the back surface of the adapter plate;

manufacturing a conductive interconnection structure on one side of the adapter plate close to the front surface, wherein the conductive interconnection structure is electrically connected with the through silicon via;

placing a first chip in the groove, and manufacturing a first plastic package body to encapsulate the first chip;

manufacturing a rewiring structure on one side of the adapter plate close to the back surface, wherein the rewiring structure is electrically connected with the silicon through hole and the first chip;

and placing a second chip on one side of the conductive interconnection structure, which is deviated from the through silicon via, and connecting the second chip with the through silicon via through the conductive interconnection structure.

Further, the manufacturing method of the multi-chip stack package structure further comprises: and manufacturing a second plastic package body to encapsulate the second chip.

Further, the method for manufacturing the conductive interconnection structure comprises the following steps:

connecting a second conductive pad on the through silicon via;

connecting a first conductive transfer structure on the second conductive pad;

a first conductive pad is connected on the first conductive transfer structure.

Further, the method of fabricating the re-wiring structure includes:

manufacturing third conductive pads on the first chip and the through silicon via respectively;

connecting a second conductive transfer structure on the third conductive pad;

connecting a fourth conductive pad on the second conductive transfer structure;

and manufacturing an external solder ball on the fourth conductive pad.

Further, the method for connecting the second chip and the through silicon via includes:

manufacturing a welding structure on the front surface of the second chip;

and welding the welding structure with the conductive interconnection structure.

The technical scheme of the invention has the following advantages:

1. according to the multi-chip stacking and packaging structure provided by the invention, the back surface of the adapter plate provided with the through silicon via is provided with the groove, the first chip is packaged in the groove, the rewiring structure is arranged on one side of the adapter plate close to the back surface and is connected with the first chip, the second chip is arranged on one side of the adapter plate close to the front surface and is connected with the rewiring structure through the through silicon via, on one hand, the first chip and the second chip are positioned at different spatial positions of the adapter plate due to the groove arranged on the adapter plate, so that the total packaging size of the first chip and the second chip can exceed the size of the adapter plate, and the packaging space is expanded; on the other hand, the first chip is not required to be connected with a rewiring structure through the silicon through hole, so that the packaging difficulty is reduced, the packaging feasibility is improved, the production cost and the working procedures are saved, and the method is suitable for large-scale processing and production.

2. According to the multi-chip stacking and packaging structure provided by the invention, the front surface of the first chip faces the opening direction of the groove, and the front surface of the first chip is connected with the rewiring structure through the conductive pad, so that the connection structure is simple and effective, and the cost is low.

3. According to the manufacturing method of the multi-chip stacking and packaging structure, the silicon through hole penetrating through the adapter plate is formed on the adapter plate, the opening depth does not need to be controlled, the manufacturing is simple and convenient, the first chip is directly connected with the rewiring structure through the conductive pad, the cost is low, and the operation is convenient.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a schematic structural diagram of a multi-chip stacked package structure according to an embodiment of the present disclosure;

FIG. 2 is a top view of a multi-chip stacked package structure according to an embodiment of the present disclosure;

FIG. 3 is a flow chart illustrating a method for fabricating a multi-chip stacked package structure according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram obtained in step S2 in the embodiment of the present application;

fig. 5 is a schematic structural diagram obtained in step S3 in this embodiment of the present application;

fig. 6 is a schematic structural diagram obtained in step S4 in this embodiment of the present application;

fig. 7 is a schematic structural diagram obtained in step S5 in the embodiment of the present application;

fig. 8 is a schematic structural diagram obtained in step S6 in this embodiment.

Description of reference numerals:

1-an adapter plate; 2-through silicon vias; 3-a groove; 4-a first chip; 5-a first plastic package body; 6-a second chip; 7-a fifth conductive pad; 8-a third insulating dielectric layer; 9-a sixth conductive pad; 10-a first insulating dielectric layer; 11-a first conductive pad; 12-a second conductive pad; 13-welding the structure; 14-a second plastic package body; 15-a second insulating dielectric layer; 16-a third conductive pad; 17-a fourth conductive pad; 18-external solder balls; 19-an adhesive layer; 20-carrying a sheet; 21-PCB board.

Detailed Description

The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

In a first aspect, an embodiment of the invention provides a multi-chip stacked package structure.

As shown in fig. 1, the multi-chip stacked package structure includes:

the adapter plate 1 is provided with a through silicon hole 2 penetrating through the front surface and the back surface of the adapter plate 1, and the back surface of the adapter plate 1 is provided with a groove 3;

the first chip 4 is encapsulated in the groove 3 through a first plastic package body 5;

the rewiring structure is arranged on one side, close to the back, of the adapter plate 1 and is electrically connected with the first chip 4 and the through silicon via 2 respectively;

and the second chip 6 is arranged on one side of the adapter plate 1 close to the front surface and is electrically connected with the rewiring structure through the through silicon via 2.

In the multi-chip stacked package structure provided by the embodiment, the back surface of the interposer 1 provided with the through silicon via 2 is provided with the groove 3, the first chip 4 is packaged in the groove 3, the rewiring structure is arranged on one side of the interposer 1 close to the back surface and connected with the first chip 4, the second chip 6 is arranged on one side of the interposer 1 close to the front surface and connected with the rewiring structure through the through silicon via 2, on one hand, the first chip 4 and the second chip 6 are located at different spatial positions of the interposer 1 due to the groove 3 arranged on the interposer 1, so that the total packaging size of the first chip 4 and the second chip 6 can exceed the size of the interposer 1, and the packaging space is expanded; on the other hand, the first chip 4 is not required to be connected with a rewiring structure through the silicon through hole 2, so that the packaging difficulty is reduced, the packaging feasibility is improved, the production cost and the working procedures are saved, and the method is suitable for large-scale processing and production.

The carrier of the interposer 1 is made of silicon, glass or other materials, the through-silicon via 2 can be obtained by forming a through-hole in the carrier and filling a conductive metal in the through-hole, the conductive metal is generally copper, and other metals may also be used, the interposer 1 is obtained by a manufacturing method in the prior art, which is not described in detail in this embodiment.

A groove 3 is manufactured on the back surface of the adapter plate 1 through a chemical corrosion or plasma etching method, the groove 3 is located in a region where the adapter plate 1 is not provided with the through silicon via 2, the groove 3 is used for packaging the first chip 4 and is connected with the rewiring structure, and the through silicon via 2 is used for communicating the second chip 6 with the rewiring structure. The area, depth, shape, etc. of the bottom surface of the groove 3 can be adjusted according to actual needs, and the depth is generally controlled to be larger than the thickness of the first chip 4.

The present embodiment does not limit the type of the first chip 4, and may be, for example, an integrated circuit device, and may also be an application processor, a central processing unit, a graphics processor, a memory array, a radio frequency transceiver, a photonic integrated circuit, a micro-electro-mechanical system, a floating gate array (FPGA), a power management IC, an image sensor, and other devices.

The first chip 4 is electrically connected to the rewiring structure through the conductive structure, and the front surface of the first chip 4 may face or depart from the opening direction of the groove 3, as a preferred embodiment, the front surface of the first chip 4 faces the opening direction of the groove 3, and the front surface of the first chip 4 is connected to the rewiring structure through the fifth conductive pad 7. The front surface of the first chip 4 faces the opening direction of the groove 3, and the front surface of the first chip 4 is connected with the rewiring structure through the fifth conductive pad 7, so that the connection structure is simple and effective, and the cost is low. In this embodiment, the shape, structure and size of the fifth conductive pad 7 are not limited, and may be a bump, a copper pillar or other shapes, and the material thereof may be metal such as copper, tin, silver, nickel, gold, etc.

Preferably, in this embodiment, a third insulating medium layer 8 is formed on the interposer 1 at a side where the recess 3 is disposed, and a sixth conductive pad 9 is embedded in the third insulating medium layer 8 at a position corresponding to the through-silicon via 2, so that the sixth conductive pad 9 is electrically connected to the through-silicon via 2. The sum of the thicknesses of the first chip 4 and the fifth conducting pad 7 is controlled to be consistent with the sum of the heights of the groove 3 and the third insulating medium layer 8, the first chip 4 with the fifth conducting pad 7 connected to the front surface is placed in the groove 3 in a picking mode in a mode that the front surface faces upwards, and one end, not connected with the first chip 4, of the fifth conducting pad 7 is flush with the surface of one side, away from the through silicon via 2, of the third insulating medium layer 8. The third insulating dielectric layer 8 may be made of inorganic materials such as silicon dioxide, silicon nitride, and low-K dielectric, or organic materials such as Polyimide (PI) and poly-p-Phenylene Benzobisoxazole (PBO).

The first plastic package body 5 is used for packaging the first chip 4 in the groove 3, and the first plastic package body 5 can be made of organic materials such as epoxy resin and phenolic resin or other materials. Preferably, the planarization and the height reduction can be realized by processes such as grinding, chemical etching, UV illumination, etc., so that the surface of the fifth conductive pad 7 is exposed out of the first plastic package body 5 and is flush with the surface of the first plastic package body 5, so as to reduce the thickness of the whole package structure, and facilitate the subsequent processes.

The second chip 6 is not limited in type, and may be, for example, a circuit component, an application processor, a central processing unit, a graphics processor, a memory array, a radio frequency transceiver, a photonic integrated circuit, a micro-electro-mechanical system, a floating gate array (FPGA), a power management IC, an image sensor, and the like.

The second chip 6 is electrically connected with the through-silicon via 2 through a conductive structure, so that conductive interconnection with a rewiring structure is realized. As a preference of the present embodiment, the conductive structure connecting the second chip 6 and the through silicon via 2 includes: a first insulating dielectric layer 10, a first conductive pad 11 is encapsulated on the front surface, a second conductive pad 12 is encapsulated on the back surface, the first conductive pad 11 and the second conductive pad 12 are connected through a first conductive transfer structure encapsulated in the first insulating dielectric layer 10, and the second conductive pad 12 is electrically connected with the through silicon via 2; the solder structure 13 has one end electrically connected to the second chip 6 and the other end electrically connected to the first conductive pad 11.

The first insulating dielectric layer 10 may be made of inorganic materials such as silicon dioxide, silicon nitride, and low-K dielectric, or organic materials such as Polyimide (PI) and poly-p-Phenylene Benzobisoxazole (PBO).

In this embodiment, the shape, structure and size of the first conductive pad 11 and the second conductive pad 12 are not limited, and the first conductive pad may be a bump, a copper pillar or other shapes, and the material thereof may be copper, tin, silver, nickel, gold or other metals.

The first conductive transfer structure (not shown) may be a transfer line layer or a combination of a transfer line layer and a conductive via/conductive pillar, and may be selected reasonably according to actual situations.

The soldering structure 13 is used to electrically connect the second chip 6 and the first conductive pad 11, and the material of the soldering structure may be copper, nickel, tin, silver, gold, or other metals.

Preferably, the multi-chip stacked package structure further includes a second plastic package body 14 encapsulating the second chip 6, wherein the second plastic package body 14 may be made of an organic material such as epoxy resin, phenolic resin, or other materials, and further preferably, the second plastic package body 14 is planarized and thinned by processes such as grinding, chemical etching, and UV irradiation, so as to reduce the thickness of the package structure as a whole.

The rewiring structure, that is, a structure for conducting signals between the first chip 4 and the second chip 6 and other devices (such as the PCB 21), realizes fan-out packaging of the first chip 4 and the second chip 6. As a preferable aspect of the present embodiment, the rewiring structure includes: a second insulating dielectric layer 15, wherein a third conductive pad 16 is encapsulated on the front surface and a fourth conductive pad 17 is encapsulated on the back surface, the third conductive pad 16 and the fourth conductive pad 17 are connected through a second conductive transfer structure encapsulated in the second insulating dielectric layer 15, and the third conductive pad 16 is electrically connected with the through silicon via 2 and the first chip 4 respectively; and an external solder ball 18 electrically connected to the fourth conductive pad 17.

The second insulating dielectric layer 15 may be made of inorganic materials such as silicon dioxide, silicon nitride, and low-K dielectric, or organic materials such as Polyimide (PI) and poly-p-Phenylene Benzobisoxazole (PBO).

In the present embodiment, the shape, structure and size of the third conductive pad 16 and the fourth conductive pad 17 are not limited, and the third conductive pad may be a bump, a copper pillar or other shapes, and the material thereof may be copper, tin, silver, nickel, gold or other metals.

The second conductive transfer structure (not shown in the figure) may be a transfer line layer or a combination of a transfer line layer and a conductive via/conductive pillar, and may be selected reasonably according to actual situations. The third conductive pad 16 is electrically connected to the through silicon via 2 through the sixth conductive pad 9, and the third conductive pad 16 is electrically connected to the first chip 4 through the fifth conductive pad 7.

The external solder balls 18 are used for interconnecting the first chip 4 and the second chip 6 with other devices (such as a PCB 21), and the material of the external solder balls 18 may be metal such as copper, nickel, tin, silver, gold, etc., and the external solder balls 18 may be manufactured by electroplating or ball-planting.

It should be emphasized that the number of the first chips 4 is not limited to two shown in the figures, the second chips 6 are not limited to two shown in the figures, and in addition, other chips and the like can be stacked above the second chips 6, which can be selected and matched according to practical situations, and the application is not limited thereto.

The multi-chip stacking packaging structure provided by the embodiment is suitable for packaging chips with various sizes and has strong flexibility. As shown in fig. 2, the widths of the two first chips 4 and the one second chip 6 are smaller than the width of the interposer 1, but there is no requirement for the width size between the first chips 4 and the second chips 6, and the lengths of the two first chips 4 and the one second chip 6 are smaller than the length of the interposer 1, but there is no requirement for the length size between the first chips 4 and the second chips 6, that is, the sizes of the first chips 4 and the second chips 6 do not affect each other, so that the stacked package of chips with various sizes can be realized.

In a second aspect, an embodiment of the invention provides a method for manufacturing a multi-chip stacked package structure.

As shown in FIG. 3, the method for fabricating the multi-chip stacked package structure includes steps S1-S5:

step S1, providing an interposer 1, wherein the interposer 1 is provided with a through-silicon via 2 penetrating the front and back surfaces thereof, and the back surface of the interposer 1 is provided with a groove 3.

The adapter plate 1 provided with the through silicon via 2 is manufactured by adopting a method for manufacturing the adapter plate 1 with the through silicon via 2 in the prior art. And manufacturing a groove 3 on the back surface of the adapter plate 1 by adopting a chemical corrosion or plasma etching method.

Step S2, a conductive interconnection structure is fabricated on one side of the interposer 1 close to the front surface, and the conductive interconnection structure is electrically connected to the through-silicon via 2.

As a preference of this embodiment, the method of manufacturing the conductive interconnection structure includes: connecting a second conductive pad 12 on the through silicon via 2; connecting a first conductive transfer structure over the second conductive pad 12; a first conductive pad 11 is connected on the first conductive transfer structure. Specifically, a second conductive pad 12 is welded on the through silicon via 2, a first conductive transfer structure is connected to the second conductive pad 12, the first conductive transfer structure is connected to the first conductive pad 11, the second conductive pad 12, the first conductive transfer structure, and the first conductive pad 11 are all prepared in an insulating medium, each insulating medium forms a first insulating medium layer 10, and the methods for preparing the second conductive pad 12, the first conductive transfer structure, and the second conductive pad 12 all belong to the prior art and are not described herein.

Preferably, the manufacturing method further includes manufacturing a third insulating dielectric layer 8 on the side of the interposer 1 where the groove 3 is formed, and manufacturing a sixth conductive pad 9 in the third insulating dielectric layer 8 at a position corresponding to the through-silicon-via 2, for example, by manufacturing a through-hole in the third insulating dielectric layer 8 through a process such as photolithography or chemical etching, PVD, CVD, or electroplating, and forming the sixth conductive pad 9 through conductive metal filling. The structure obtained after step S2 is shown in fig. 4.

Step S3, placing the first chip 4 in the recess 3, and making the first plastic package body 5 to encapsulate the first chip 4.

The first chip 4 is placed right side up in the recess 3 by means of picking. The fifth conductive pad 7 can be formed on the first chip 4 in advance, and then the first chip 4 connected with the fifth conductive pad 7 is placed in the groove 3, so that the first molding compound 5 is formed to encapsulate the first chip 4 and the fifth conductive pad 7. Mechanical grinding, chemical etching, UV irradiation, and other processes can be used to expose the fifth conductive pad 7 on the surface of the first plastic package body 5. The structure obtained after step S3 is shown in fig. 5.

In step S4, a redistribution structure is formed on the side of the interposer 1 close to the back surface, and the redistribution structure is electrically connected to the through-silicon via 2 and the first chip 4.

As a preferable aspect of this embodiment, the method of manufacturing the rewiring structure includes: respectively manufacturing a third conductive pad 16 on the first chip 4 and the through silicon via 2; connecting a second conductive transfer structure on the third conductive pad 16; connecting a fourth conductive pad 17 on the second conductive transfer structure; and fabricating an external solder ball 18 on the fourth conductive pad 17.

The third conductive pad 16, the second conductive transfer structure, and the fourth conductive pad 17 are all prepared in an insulating medium, each layer of insulating medium forms a second insulating medium layer 15, and the methods for preparing the third conductive pad 16, the second conductive transfer structure, and the fourth conductive pad 17 all belong to the prior art, and are not described herein again. The external solder balls 18 can be manufactured by electroplating or ball-planting. The structure obtained after step S4 is shown in fig. 6.

The conductive interconnect structures are all connected to the chip in the steps involved in fig. 4-6, not shown.

Step S5, placing the second chip 6 on a side of the conductive interconnection structure away from the through-silicon via 2, and connecting the second chip 6 and the through-silicon via 2 through the conductive interconnection structure.

As a preference of the present embodiment, the method of connecting the second chip 6 and the through silicon via 2 includes: manufacturing a welding structure 13 on the front surface of the second chip 6; the solder structures 13 are soldered to the conductive interconnect structures. Specifically, the external solder balls 18 prepared in step S4 are first placed downward and connected to the carrier 20 through the adhesive layer 19, the external solder balls 18 are bonded to the adhesive layer 19, wherein the carrier 20 may be silicon, glass, or the like, then the solder structure 13 is formed on the front surface of the second chip 6, and finally the solder structure 13 is soldered to the first conductive pad 11 by a soldering method. The structure obtained in step S5 is shown in fig. 7.

As a further improvement of this embodiment, the manufacturing method further includes:

in step S6, the second molding compound 14 is manufactured to encapsulate the second chip 6. Preferably, the thickness of the second plastic package body 14 can be reduced by mechanical grinding, chemical etching, UV irradiation, and other processes, so as to reduce the thickness of the whole package structure. Further, the step of peeling off the adhesive layer 19 and the carrier sheet 20 is also included after the second plastic package body 14 is manufactured, and the bonding can be achieved by heating, UV irradiation, or mechanical external force or the like. The structure obtained after step S6 is shown in fig. 8.

According to the manufacturing method of the multi-chip stacking and packaging structure, the silicon through hole 2 penetrating through the adapter plate 1 is formed in the adapter plate, the opening depth does not need to be controlled, the manufacturing is simple and convenient, the first chip 4 is directly connected with the rewiring structure through the conductive pad, the cost is low, and the operation is convenient.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.