阅读说明：本技术 一种基于cmos工艺的反馈增强型跨阻放大器 (Feedback enhancement type trans-impedance amplifier based on CMOS (complementary Metal oxide semiconductor) process ) 是由 毛陆虹 周高磊 谢生 于 2019-09-16 设计创作，主要内容包括：一种基于CMOS工艺的反馈增强型跨阻放大器,第一反馈放大器和第二反馈放大器的偏置电压输入端连接外部偏置电压VBIAS,第一反馈放大器的输出端连接第一主放大器的偏置电压输入端,第一反馈放大器和第一主放大器的信号输入端连接第一输入信号VIN1,第一主放大器的信号输出端构成跨阻放大器的第一输出端VOUT1,第二反馈放大器的输出端连接第二主放大器的偏置电压输入端,第二反馈放大器和第二主放大器的信号输入端连接第二输入信号VIN2,第二主放大器的信号输出端构成跨阻放大器的第二输出端VOUT2,负电容电路连接第一输出端VOUT1和第二输出端VOUT2。本发明输入端降低跨阻放大器等效输入阻抗,输出端缓解跨阻放大器增益和带宽的矛盾。(A feedback enhancement type trans-impedance amplifier based on a CMOS process is characterized in that bias voltage input ends of a first feedback amplifier and a second feedback amplifier are connected with an external bias voltage VBIAS, an output end of the first feedback amplifier is connected with a bias voltage input end of a first main amplifier, signal input ends of the first feedback amplifier and the first main amplifier are connected with a first input signal VIN1, a signal output end of the first main amplifier forms a first output end VOUT1 of the trans-impedance amplifier, an output end of the second feedback amplifier is connected with a bias voltage input end of a second main amplifier, signal input ends of the second feedback amplifier and the second main amplifier are connected with a second input signal VIN2, a signal output end of the second main amplifier forms a second output end VOUT2 of the trans-impedance amplifier, and a negative capacitance circuit is connected with the first output end VOUT1 and the second output end VOUT 2. The input end of the invention reduces the equivalent input impedance of the trans-impedance amplifier, and the output end relieves the contradiction between the gain and the bandwidth of the trans-impedance amplifier.)

1. A feedback enhancement type trans-impedance amplifier based on a CMOS (complementary metal oxide semiconductor) process is characterized by comprising a first feedback amplifier, a first main amplifier, a negative capacitance circuit, a second main amplifier and a second feedback amplifier, wherein bias voltage input ends of the first feedback amplifier and the second feedback amplifier are both connected with an external bias voltage VBIAS, an output end of the first feedback amplifier is connected with the bias voltage input end of the first main amplifier, signal input ends of the first feedback amplifier and the first main amplifier are both connected with a first input signal VIN1, a signal output end of the first main amplifier forms a first output end VOUT1 of the trans-impedance amplifier, an output end of the second feedback amplifier is connected with a bias voltage input end of the second main amplifier, and signal input ends of the second feedback amplifier and the second main amplifier are both connected with a second input signal VIN2, the signal output end of the second main amplifier forms a second output end VOUT2 of the transimpedance amplifier, and the negative capacitance circuit is respectively connected with the first output end VOUT1 and the second output end VOUT 2.

2. The CMOS process based feedback enhanced transimpedance amplifier according to claim 1, wherein the first feedback amplifier comprises a fifth NMOS transistor (Mt)₅) And the third NMOS transistor₃) And seventh P MOS transistor (M)₇) Wherein the fifth NMOS transistor (M)₅) Is connected with an external bias voltage VBIAS and a fifth NMOS tube (M)₅) Is connected with a third NMOS tube (M)₃) Drain electrode of (D), fifth NMOS transistor (M)₅) The drain electrode of the first transistor is connected with the bias voltage output end of the first main amplifier, and the drain electrode of the first transistor is also connected with a seventh P MOS transistor (M)₇) The third NMOS transistor (M)₃) And seventh P MOS transistor (M)₇) Is connected to the first input signal VIN1, the third NMOS transistor (M)₃) The source of (A) is grounded, and the seventh P MOS tube (M)₇) Is connected to the power supply VDD.

3. The CMOS process based feedback enhanced transimpedance amplifier according to claim 1, wherein said first main amplifier comprises a first NMOS transistor (Ml)₁) The first NMOS transistor (M)₁) The grid of the first NMOS tube (M) forms a bias voltage input end of the first main amplifier and is connected with a bias voltage output end of the first feedback amplifier₁) Is connected to the first input signal VIN1, and is also passed through a third current source (I)₃) Ground, the first NMOS transistor (M)₁) Form a first output terminal VOUT1 of the transimpedance amplifier, the drains further passing through respective first resistors (R)₁) A power supply VDD, and a negative capacitance circuit.

4. The CMOS process based feedback enhanced transimpedance amplifier according to claim 1, wherein said second feedback amplifier comprisesComprises a sixth NMOS tube (M)₆) And the fourth NMOS transistor (M)₄) And eighth P MOS transistor (M)₈) Wherein the sixth NMOS transistor (M)₆) Is connected with an external bias voltage VBIAS and a sixth NMOS tube (M)₆) Is connected with a fourth NMOS tube (M)₄) Drain electrode of (D), sixth NMOS transistor (M)₆) The drain electrode of the first transistor is connected with the bias voltage output end of the second main amplifier, and the drain electrode of the first transistor is also connected with an eighth P MOS tube (M)₈) The fourth NMOS tube (M)₄) And eighth P MOS transistor (M)₈) Is connected to the second input signal VIN2, and the fourth NMOS transistor (M)₄) The source of (A) is grounded, and the eighth P MOS tube (M)₈) Is connected to the power supply VDD.

5. The CMOS process based feedback enhanced transimpedance amplifier according to claim 1, wherein said second main amplifier comprises a second NMOS transistor (Ml)₂) The second NMOS transistor (M)₂) The grid of the second NMOS tube (M) forms a bias voltage input end of a second main amplifier and is connected with a bias voltage output end of a second feedback amplifier₂) Is connected to the second input signal VIN2, and is also passed through a fourth current source (I)₄) Ground, the second NMOS transistor (M)₂) Constitutes a second output terminal VOUT2 of the transimpedance amplifier, which further pass through respective second resistors (R)₂) A power supply VDD, and a negative capacitance circuit.

6. The CMOS process based feedback enhanced transimpedance amplifier according to claim 1, wherein said negative capacitance circuit comprises a ninth NMOS transistor (Mc)₉) And tenth P MOS transistor (M)₁₀) Wherein, the ninth NMOS tube (M)₉) Drain electrode of (1) and tenth P MOS transistor (M)₁₀) Is connected with the first output terminal VOUT1 and the ninth NMOS transistor (M)₉) Gate of (1) and tenth P MOS transistor (M)₁₀) Is connected with the second output terminal VOUT2, the ninth NMOS transistor (M)₉) And tenth P MOS transistor (M)₁₀) A capacitor (C) is connected between the source electrodes, and the ninth NMOS tube (M)₉) Is/are as followsThe source electrode passes through a first current source (I)₁) Grounded, tenth P MOS transistor (M)₁₀) Is passed through a second current source (I)₂) And (4) grounding.

Technical Field

The invention relates to a transimpedance amplifier. And more particularly to a feedback enhanced transimpedance amplifier based on a CMOS process.

Background

With the advent of the big data age, the demand of human society for network bandwidth and data traffic has increased exponentially. Due to the existence of skin effect, when high-speed data is transmitted in a traditional electrical interconnection transmission mode taking a copper core cable as a medium, serious loss and crosstalk occur, and the requirements of data transmission quantity and transmission rate in the information age cannot be met. The optical interconnection mode using light as a transmission carrier and optical fiber as a transmission medium can get rid of the constraints of skin effect, has the advantages of low loss, small crosstalk, high bandwidth and the like, and is certainly the main mode of data transmission in the future. The optical receiver, as one of the core modules of the optical interconnection system, naturally becomes a hot research direction of silicon-based photoelectrons. Meanwhile, as the semiconductor technology enters the deep submicron era, the minimum size of the CMOS technology is continuously reduced, the characteristic frequency is gradually increased, and compared with the BiCMOS technology, the CMOS technology has the advantages of high integration level, low power consumption, low cost and the like, is a commonly used technology in the design of the analog front-end amplification circuit of the high-speed optical receiver at present, and is also a future development direction.

The transimpedance amplifier converts and amplifies the output photocurrent of the photodetector, which is the first stage of the optical receiver system, and the performance of gain, noise, bandwidth and the like directly determines the quality of the optical receiver system. The photoelectric detector usually has a large junction capacitance, the trans-impedance amplifier is directly connected with the photoelectric detector, and on the premise that the equivalent input resistance is fixed, the large junction capacitance of the photoelectric detector causes the time constant of the input end to be increased, and the bandwidth of the circuit is reduced accordingly.

According to the traditional transimpedance amplifier with the adjusting type common source common gate (RGC) structure, a common source amplifier is introduced between the output end and the output end of a single-stage common gate amplifier to serve as active feedback, so that the equivalent impedance of the input end can be effectively reduced, and the bandwidth of the transimpedance amplifier is improved. But due to the miller capacitance, the common source amplifier introduces capacitance at the input. And the miller capacitance is increased along with the increase of the feedback depth, which seriously limits the further improvement of the bandwidth of the trans-impedance amplifier. Meanwhile, with the continuous progress of semiconductor manufacturing technology, the junction capacitance of the photodetector is smaller and smaller, the input pole of the transimpedance amplifier gradually moves to high frequency, the primary and secondary relations of the input pole and the output pole become fuzzy, and therefore the frequency of the output pole also determines the speed of the circuit. In this case, the contradiction between the gain and the bandwidth of the traditional RGC trans-impedance amplifier is particularly prominent. In summary, the main problem faced by the conventional RGC structure transimpedance amplifier based on the CMOS process at present is that the frequency of the input pole is raised by the common-source active feedback structure to a limited extent, and the balance between the frequency of the output pole and the gain is difficult.

Disclosure of Invention

The invention aims to solve the technical problem of providing a feedback enhanced trans-impedance amplifier based on a CMOS (complementary metal oxide semiconductor) process, which has the advantages of high bandwidth, low cost and the like.

The technical scheme adopted by the invention is as follows: a feedback enhancement type transimpedance amplifier based on a CMOS (complementary metal oxide semiconductor) process comprises a first feedback amplifier, a first main amplifier, a negative capacitance circuit, a second main amplifier and a second feedback amplifier, wherein bias voltage input ends of the first feedback amplifier and the second feedback amplifier are connected with an external bias voltage VBIAS, an output end of the first feedback amplifier is connected with the bias voltage input end of the first main amplifier, signal input ends of the first feedback amplifier and the first main amplifier are connected with a first input signal VIN1, a signal output end of the first main amplifier forms a first output end VOUT1 of the transimpedance amplifier, an output end of the second feedback amplifier is connected with a bias voltage input end of the second main amplifier, signal input ends of the second feedback amplifier and the second main amplifier are connected with a second input signal VIN2, and a signal output end of the second main amplifier forms a second output end VOUT2 of the transimpedance amplifier, the negative capacitance circuit is respectively connected with the first output terminal VOUT1 and the second output terminal VOUT 2.

According to the feedback enhancement type transimpedance amplifier based on the CMOS process, the feedback enhancement technology is introduced, the input pole frequency is improved by adopting the feedback enhancement technology at the input end, the amplifier with the reverser structure is used as the feedback of the main amplifier, and the equivalent input impedance of the transimpedance amplifier is further reduced. A Cascode structure is used in the feedback structure to isolate the Miller capacitance and reduce the influence of the feedback amplifier on the input pole of the main amplifier; a negative capacitance structure is introduced into an output stage to offset the influence of load capacitance, namely, the contradiction between the gain and the bandwidth of the trans-impedance amplifier is relieved by using a negative capacitance bandwidth expansion technology at the output end. The invention has the following advantages:

1. the feedback depth is enhanced and the input equivalent impedance is further reduced. The inverter is used as a feedback amplifier of the common-gate amplifier, and under the same power consumption, stronger feedback depth can be provided.

2. The miller capacitance introduced by the input terminal is reduced. By introducing the cascode structure, the output and the input of the feedback amplifier are isolated, the influence of the Miller effect is reduced, and the equivalent parasitic capacitance of the input end is further reduced.

3. The frequency of an output pole is improved, and the contradiction between the gain and the bandwidth of the trans-impedance amplifier is relieved. The introduction of the negative capacitance technology can offset the influence of load capacitance, and the output pole frequency is improved under the condition of the same gain.

Drawings

FIG. 1 is a schematic circuit diagram of a feedback enhanced transimpedance amplifier according to the present invention based on a CMOS process;

FIG. 2 is a schematic diagram of a feedback enhanced transimpedance amplifier half-side circuit configuration;

FIG. 3 is a schematic diagram of a half-edge small-signal equivalent circuit of a feedback enhanced transimpedance amplifier;

fig. 4 is a circuit schematic of the negative capacitance circuit of the present invention.

Detailed Description

A feedback enhanced transimpedance amplifier based on a CMOS process according to the present invention is described in detail with reference to the following embodiments and accompanying drawings.

As shown in fig. 1, the feedback enhanced transimpedance amplifier based on the CMOS process according to the present invention includes a first feedback amplifier, a first main amplifier, a negative capacitance circuit, a second main amplifier and a second feedback amplifier, wherein bias voltage input terminals of the first feedback amplifier and the second feedback amplifier are both connected to an external bias voltage VBIAS, an output terminal of the first feedback amplifier is connected to the bias voltage input terminal of the first main amplifier, signal input terminals of the first feedback amplifier and the first main amplifier are both connected to a first input signal VIN1, a signal output terminal of the first main amplifier forms a first output terminal VOUT1 of the transimpedance amplifier, an output terminal of the second feedback amplifier is connected to the bias voltage input terminal of the second main amplifier, signal input terminals of the second feedback amplifier and the second main amplifier are both connected to a second input signal VIN2, the signal output end of the second main amplifier forms a second output end VOUT2 of the transimpedance amplifier, and the negative capacitance circuit is respectively connected with the first output end VOUT1 and the second output end VOUT 2.

The first feedback amplifier comprises a fifth NMOS transistor M₅And the third NMOS transistor M₃And a seventh P MOS transistor M₇Wherein, the fifth NMOS tube M₅The grid electrode of the NMOS tube M is connected with an external bias voltage VBIAS, and the fifth NMOS tube M₅Is connected with a third NMOS tube M₃Drain electrode of (1), fifth NMOS tube M₅The drain electrode of the first P MOS transistor M is connected with the bias voltage output end of the first main amplifier, and the drain electrode of the first P MOS transistor M is connected with the bias voltage output end of the first main amplifier₇The third NMOS tube M₃And a seventh P MOS transistor M₇Is connected with the first input signal VIN1, and the third NMOS transistor M₃The source electrode of the seventh P MOS transistor M is grounded, and the seventh P MOS transistor M₇Is connected to the power supply VDD.

The second feedback amplifier comprises a sixth NMOS transistor M₆And the fourth NMOS tube M₄And eighth P MOS transistor M₈Wherein, the sixth NMOS tube M₆The grid electrode of the NMOS transistor is connected with an external bias voltage VBIAS, and a sixth NMOS transistor M₆Is connected with a fourth NMOS tube M₄The sixth NMOS transistor M₆The drain electrode of the first transistor is connected with the bias voltage output end of the first main amplifier, and the drain electrode of the first transistor is connected with the bias voltage input end of the second main amplifier and the eighth P MOS transistor M₈The fourth NMOS tube M₄And eighth P MOS transistor M₈Is connected with the second input signal VIN2, and the fourth NMOS transistor M₄The source electrode of the eighth P MOS tube M is grounded, and the eighth P MOS tube M₈Is connected to the power supply VDD.

In the first feedback amplifier and the second feedback amplifier, a third NMOS transistor M₃And a seventh P MOS transistor M₇Or the fourth NMOS transistor M₄And eighth P MOS transistor M₈An inverter type amplifier is constituted, and the amplifier is a feedback amplifier, and the equivalent input impedance can be effectively reduced. Is positioned in the third NMOS tube M₃And a fifth NMOS transistor M₅Or the fourth NMOS transistor M₄And a sixth NMOS transistor M₆And forming a cascode structure to isolate the miller capacitance of the input node.

The first main amplifier comprises a first NMOS transistor M₁The first NMOS tube M₁The grid electrode of the first NMOS tube M forms a bias voltage input end of a first main amplifier and is connected with a bias voltage output end of a first feedback amplifier₁Is connected to the first input signal VIN1, and is also passed through a third current source I₃Grounded, the first NMOS tube M₁Form a first output terminal VOUT1 of the transimpedance amplifier, the drains further passing through respective first resistors R₁A power supply VDD, and a negative capacitance circuit.

The second main amplifier comprises a second NMOS transistor M₂The second NMOS tube M₂The grid electrode of the first NMOS tube M forms a bias voltage input end of a first main amplifier and is connected with a bias voltage output end of a first feedback amplifier, and a first NMOS tube M₂Is connected to the second input signal VIN2, and is also passed through a fourth current source I₄Grounded, the second NMOS tube M₂Form a second output terminal VOUT2 of the transimpedance amplifier, the drains further passing through respective second resistors R₂A power supply VDD, and a negative capacitance circuit.

The first main amplifier and the second main amplifier are common-gate amplifiers formed by NMOS tubes and resistors R, and the input resistor with a small common-gate structure can improve the frequency of an input pole.

The negative capacitance circuit comprises a ninth NMOS transistor M₉And a tenth P MOS transistor M₁₀Wherein, the ninth NMOS tube M₉Drain electrode of (1) and tenth P MOS tube M₁₀Is connected to the first output terminal VOUT1,the ninth NMOS tube M₉Grid and tenth P MOS tube M₁₀Is connected with the second output terminal VOUT2, and the ninth NMOS transistor M₉And a tenth P MOS transistor M₁₀A capacitor C is connected between the source electrodes, and the ninth NMOS tube M₉By a first current source I₁Grounded tenth P MOS transistor M₁₀By a second current source I₂And (4) grounding. And the capacitor C generates a negative capacitor at the output node in a positive feedback mode, so that the influence of an output load capacitor is counteracted, the output pole frequency can be improved, and the bandwidth of the trans-impedance amplifier is further expanded.

The feedback-enhanced transimpedance amplifier according to the present invention based on a CMOS process is analyzed and explained in detail below.

A. Feedback enhancement techniques

The traditional RGC type trans-impedance amplifier uses a common source structure amplifier as the feedback of a common gate main amplifier, and the larger the gain of the feedback amplifier is, the smaller the equivalent input resistance is. But due to the existence of the miller capacitance, the larger the gain of the common source amplifier is, the larger the miller capacitance must be introduced at the input end. In order to solve the problem, the invention provides a feedback enhancement technology, a single-ended circuit structure is as shown in fig. 2, a Cascode (Cascode) structure inverter is adopted as a feedback amplifier, and Mn and Mp in the inverter can share drain-source current, so that the inverter can provide twice feedback gain of the Cascode amplifier for the common-gate TIA. Cascaded M₂And a Cascode structure is formed with Mn, so that the output resistance of the inverter can be increased, the feedback gain is further improved, and meanwhile, the Miller capacitance generated by Mn at the input end can be reduced. Neglecting the influence of the gate source capacitances Cgsn and Cgsp of Mn and Mp, equating the sum of the equivalent miller capacitance generated at the output end by the PAD capacitance Cpad, Mn and the gate drain capacitances Cgdn and Cgdp of Mp and the static protection parasitic capacitance Cesd to Cin and equ, and analyzing according to the novel TIA small signal model shown in FIG. 2 to obtain the transimpedance gain:

in the formula: a. the_INV,feed＝(1+(g_mn+g_mp)(r_op||(r_o2+(1+g_m2r_o2)r_on))). The above equation shows that the feedback enhancement mode can provide nearly twice the feedback gain for the common-gate TIA compared to the conventional RGC structure, so that the input-end equivalent input resistance Rin, equ is 1/(a)_INV,feed·_gm1) And the input pole moves to high frequency, so that the bandwidth of the TIA is expanded.

B. Negative capacitance compensation technique

In an optical receiver system, a trans-impedance amplifier needs to be cascaded with a limiting amplifier to improve gain and ensure that the output swing can meet the processing requirement of a subsequent digital circuit. However, the parasitic capacitance of the subsequent stage may cause a large capacitive load to the previous stage, and particularly, the load capacitance may further increase in consideration of the miller effect. The negative capacitance compensation technology connects a capacitor to the input end of a compensated capacitor in a positive feedback mode, introduces a negative capacitor at the connection position of the two-stage amplifier, and compensates a load capacitor, so that the output pole is pushed to high frequency, and the purpose of expanding the bandwidth is achieved.

The most basic negative capacitance compensation structure is shown in FIG. 4, in which a field effect transistor M₁And M₂The gate and the drain of (1) are cross-connected to each other. The equivalent output impedance, regardless of the channel length modulation effect, can be expressed as:

ignoring sC under low frequency conditions_GSThe above equation can be simplified to:

obviously, the negative capacitance structure circuit introduces a negative capacitance value at the circuit access end, and the structure can be arranged between the outputs of the trans-impedance amplifier by utilizing the characteristic of the negative capacitance structure, so that the equivalent load capacitance can be reduced, the bandwidth expansion of the cascade circuit can be realized, and the contradiction between the gain and the bandwidth of the trans-impedance amplifier can be relieved.

The invention relates to a CMOS (complementary Metal-oxide-semiconductor transistor) -based processThe feedback enhanced transimpedance amplifier has a differential structure, as shown in fig. 1, a current signal generated by the photodetector enters the first NMOS transistor M through the input terminal VIN1₁Source electrode and third NMOS transistor M₃And a seventh P MOS transistor M₇Because of the characteristic of no current in the grid of the CMOS circuit, the current signal passes through the first NMOS tube M₁And a drain resistor R1, and the voltage signal is converted into a voltage signal, and the signal is output from an output port VOUT 1. At the same time, the input port VIN1 is connected to the third NMOS transistor M₃And a seventh P MOS transistor M₇Is connected with the grid electrode of the first transistor, and the output signal is amplified and inverted by the inverter and then passes through a seventh P MOS transistor M₇And a fifth NMOS transistor M₅The drain electrode of the first NMOS transistor M acts on₁For which a bias voltage is provided. Fifth NMOS transistor M₅In the third NMOS transistor M₃And a seventh P MOS transistor M₇In between, the grid voltage is provided by off-chip bias, and plays a role of isolating the Miller capacitor. Meanwhile, the output terminal VOUT1 is also connected with the ninth NMOS transistor M₉Drain and tenth P MOS transistor M₁₀Is connected with the grid electrode of the NMOS transistor, the capacitor C is arranged in the ninth NMOS transistor M₉And a tenth P MOS transistor M₁₀The negative capacitance structure is formed. Current sources I1, I2, I3, I4 provide DC bias for the respective paths. The left and right structures of the circuit are symmetrical with each other.