Advanced pass-through mechanism for low power sequencers
阅读说明：本技术 用于低功率定序器的高级直通机制 (Advanced pass-through mechanism for low power sequencers ) 是由 S·班纳吉 M·辛格 V·贾因 V·德瓦拉赛蒂 于 2018-03-26 设计创作，主要内容包括：本公开的各方面涉及DC功率管理。定序器可以被配置为执行第一命令,其中第一命令与唯一组标签相关联；将唯一组标签与主组标签进行比较；确定是否检测到中断；锁定主组标签以产生锁定的主组标签；执行第二命令,其中第二命令与锁定的主组标签相关联；确定到达锁定的主组标签中的命令的结尾,并且执行序列跳转命令以使处理器回到常规功率状态。(Aspects of the present disclosure relate to DC power management. The sequencer may be configured to execute a first command, wherein the first command is associated with a unique group tag; comparing the unique group tag to the master group tag; determining whether an interrupt is detected; locking the master group tag to produce a locked master group tag; executing a second command, wherein the second command is associated with the locked master group tag; it is determined that the end of the command in the locked main group tag is reached and a sequence jump command is executed to return the processor to a normal power state.)
1. A method for DC power management, the method comprising:
executing a first command, wherein the first command is associated with a unique group tag;
comparing the unique group tag to a master group tag;
determining whether an interrupt is detected;
locking the master group tag to produce a locked master group tag;
executing a second command, wherein the second command is associated with the locked master group tag;
determining that the end of the command in the locked main group tag has been reached, an
A sequence jump command is executed to return the processor to a normal power state.
2. The method of claim 1, further comprising:
organizing the plurality of commands into a plurality of sequentially arranged commands;
grouping the plurality of sequentially ordered commands into a plurality of groups, wherein each command of the plurality of sequentially ordered commands is associated with a group of the plurality of groups; and
assigning the unique group tag to one of the plurality of groups, wherein the first command is a command in the one group.
3. The method of claim 1, further comprising:
determining that the processor is in the normal power state; and
measuring a duration of time the processor is in the normal power state.
4. The method of claim 3, further comprising determining whether the duration is greater than a duration threshold.
5. The method of claim 4, further comprising executing a third command to transition the processor from the normal power state to an idle power state.
6. The method of claim 5, wherein the idle power state consumes less power than the regular power state.
7. The method of claim 6, wherein the idle power state is a shallow low power state.
8. The method of claim 6, wherein the idle power state is a deep low power state.
9. The method of claim 1, further comprising determining whether a duration of time elapsed by the processor is greater than a duration threshold, wherein the duration of time is an amount of latency in a shallow low power state.
10. The method of claim 9, further comprising transitioning to an idle power state.
11. The method of claim 10, wherein the idle power state is a deep low power state having a lower power consumption than the shallow low power state.
12. An apparatus configured for DC power management, comprising:
at least one processor;
a memory coupled to the at least one processor;
a time counter coupled to the at least one processor,
wherein the at least one processor is configured to:
executing a first command, wherein the first command is associated with a unique group tag;
comparing the unique group tag to a master group tag;
determining whether an interrupt is detected;
locking the master group tag to produce a locked master group tag;
executing a second command, wherein the second command is associated with the locked master group tag;
determining that the end of the command in the locked main group tag has been reached and
a sequence jump command is executed to return the Central Processing Unit (CPU) to a normal power state.
13. The apparatus of claim 12, wherein the at least one processor is further configured to:
organizing the plurality of commands into a plurality of sequentially arranged commands;
grouping the plurality of sequentially ordered commands into a plurality of groups, wherein each command of the plurality of sequentially ordered commands is associated with a group of the plurality of groups; and
assigning the unique group tag to one of the plurality of groups, wherein the first command is a command in the one group.
14. The apparatus of claim 13, wherein the at least one processor is further configured to:
determining that the CPU is in the normal power state; and
measuring a duration of time the CPU is in the normal power state.
15. The apparatus of claim 14, wherein the at least one processor is further configured to:
determining whether the duration is greater than a duration threshold; and
if the duration is greater than the duration threshold, executing a third command to transition the CPU from the regular power state to an idle power state, the idle power state having less power consumption than the regular power state.
16. An apparatus configured for DC power management, comprising:
at least one time counter;
at least one sequencer coupled to the time counter;
means for executing a first command, wherein the first command is associated with a unique group tag;
means for comparing the unique group tag to a master group tag;
means for determining whether an interrupt is detected;
means for locking the master group tag to produce a locked master group tag;
means for executing a second command, wherein the second command is associated with the locked master group tag;
means for determining that the end of the command in the locked main group tag has been reached, an
Means for executing a sequence jump command to return the processor to a normal power state.
17. The apparatus of claim 16, further comprising:
means for organizing the plurality of commands into a plurality of sequentially arranged commands;
means for grouping the plurality of sequentially ordered commands into a plurality of groups, wherein each command of the plurality of sequentially ordered commands is associated with a group of the plurality of groups; and
means for assigning the unique group tag to one of the plurality of groups, wherein the first command is a command in the one group.
18. The apparatus of claim 16, further comprising:
means for determining that the processor is in the normal power state; and
means for measuring a duration that the processor is in the normal power state.
19. The apparatus of claim 18, further comprising means for determining whether the duration is greater than a duration threshold.
20. The apparatus of claim 19, further comprising means for executing a third command to transition the processor from the normal power state to an idle power state.
21. The apparatus of claim 20, wherein the idle power state consumes less power than the regular power state.
22. The apparatus of claim 20, wherein the idle power state is a shallow low power state.
23. The apparatus of claim 20, wherein the idle power state is a deep low power state.
24. The apparatus of claim 16, further comprising determining whether a duration of time elapsed by the processor is greater than a duration threshold, wherein the duration of time is an amount of latency in a shallow low power state.
25. The apparatus of claim 24, further comprising means for transitioning to an idle power state.
26. The apparatus of claim 25, wherein the idle power state is a deep low power state having a lower power consumption than the shallow low power state.
27. A computer-readable medium storing computer-executable code operable on a device comprising at least one processor and at least one memory coupled to the at least one processor, the at least one processor configured to manage a DC power source, the computer-executable code comprising:
instructions for causing a computer to execute a first command, wherein the first command is associated with a unique group tag;
instructions for causing the computer to compare the unique group tag to a master group tag;
instructions for causing the computer to determine whether an interrupt is detected;
instructions for causing the computer to lock the master group tag to produce a locked master group tag;
instructions for causing the computer to execute a second command, wherein the second command is associated with the locked master group tag;
instructions for causing said computer to determine that the end of the command in said locked main group tag has been reached, an
Instructions for causing the computer to execute a sequence jump command to return the processor to a normal power state.
28. The computer-readable medium of claim 27, wherein the computer-executable code further comprises:
instructions for causing the computer to organize a plurality of commands into a plurality of sequentially arranged commands;
instructions for causing the computer to group the plurality of sequentially ordered commands into a plurality of groups, wherein each command of the plurality of sequentially ordered commands is associated with a group of the plurality of groups; and
instructions for causing the computer to assign the unique group tag to one of the plurality of groups, wherein the first command is a command in the one group.
29. The computer-readable medium of claim 27, wherein the computer-executable code further comprises:
instructions for causing the computer to determine that the processor is in a normal power state; and
instructions for causing the computer to measure a duration of time that the processor is in the normal power state.
30. The computer-readable medium of claim 29, wherein the computer-executable code further comprises:
instructions for causing the computer to determine whether the duration is greater than a duration threshold; and
instructions for causing the computer to execute a third command to transition the processor from the normal power state to an idle power state.
Technical Field
The present disclosure relates generally to the field of power management, and in particular to power management logic, e.g., related to a fall through mechanism for a power sequencer.
Background
A processor system (e.g., a multi-processor system) maintains different power states to optimize DC power savings. The processor system may contain a DC power management system that activates most or all of the total number of processors when computing demand is high (i.e., normal power state). Also, the DC power management system may idle (i.e., deactivate) a subset of the total number of processors when computing demand is low to minimize energy consumption (i.e., idle power state). However, conventional DC power management systems tend to have a large latency if the processor system needs to be woken up when it enters a deep low power state. Thus, conventional DC power management systems involve DC power consumption inefficiencies and increase latency when a required DC power state change occurs.
Disclosure of Invention
The following presents a simplified summary of one or more aspects of the disclosure in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated features of the disclosure, and is intended to neither identify key or critical elements of all aspects of the disclosure, nor delineate the scope of any or all aspects of the disclosure. Its sole purpose is to present some concepts of one or more aspects of the disclosure in a simplified form as a prelude to the more detailed description that is presented later.
In one aspect, the present disclosure provides a method for DC power management, the method comprising executing a first command, wherein the first command is associated with a unique group tag; comparing the unique group tag to the master group tag; determining whether an interrupt is detected; locking the master group tag to produce a locked master group tag; executing a second command, wherein the second command is associated with the locked master group tag; it is determined that the end of the command in the locked main group tag has been reached and a sequence jump command is executed to return the processor to a normal power state. In one example, the method further comprises one or more of: organizing the plurality of commands into a plurality of sequentially arranged commands; grouping the plurality of sequentially ordered commands into a plurality of groups, wherein each command of the plurality of sequentially ordered commands is associated with a group of the plurality of groups; assigning a unique group tag to one of the plurality of groups, wherein the first command is a command in one of the groups; determining that the processor is in a normal power state; measuring a duration of time that the processor is in a normal power state; determining whether the duration is greater than a duration threshold and/or executing a third command to transition the processor from the normal power state to the idle power state.
Another aspect of the present disclosure provides an apparatus configured for DC power management, comprising at least one processor; a memory coupled to the at least one processor; a time counter coupled to the at least one processor, wherein the at least one processor is configured to: executing a first command, wherein the first command is associated with a unique group tag; comparing the unique group tag to the master group tag; determining whether an interrupt is detected; locking the master group tag to produce a locked master group tag; executing a second command, wherein the second command is associated with the locked master group tag; determining that the end of the command in the locked main group tag has been reached, and executing a sequence jump command to return the Central Processing Unit (CPU) to a normal power state. In one aspect, the at least one processor is further configured to perform one or more of the following: organizing the plurality of commands into a plurality of sequentially arranged commands; grouping the plurality of sequentially ordered commands into a plurality of groups, wherein each command of the plurality of sequentially ordered commands is associated with a group of the plurality of groups; assigning a unique group tag to one of the plurality of groups, wherein the first command is a command in one of the groups; determining that the CPU is in a normal power state; measuring the duration of the CPU in a conventional power state; determining whether the duration is greater than a duration threshold; and/or if the duration is greater than the duration threshold, executing a third command to transition the CPU from the regular power state to an idle power state, the idle power state having less power consumption (i.e., lower power consumption) than the regular power state.
Another aspect of the present disclosure provides an apparatus configured for DC power management, comprising: at least one time counter; at least one sequencer coupled to the time counter; means for executing a first command, wherein the first command is associated with a unique group tag; means for comparing the unique group tag to the master group tag; means for determining whether an interrupt is detected; means for locking the master group tag to produce a locked master group tag; means for executing a second command, wherein the second command is associated with the locked master group tag; means for determining that the end of the command in the locked main group tag has been reached; and means for executing a sequence jump command to return the processor to a normal power state. In one aspect, the apparatus further comprises one or more of: means for organizing the plurality of commands into a plurality of sequentially arranged commands; means for grouping the plurality of sequentially ordered commands into a plurality of groups, wherein each command of the plurality of sequentially ordered commands is associated with a group of the plurality of groups; means for assigning a unique group tag to one of a plurality of groups, wherein the first command is a command in one of the groups; means for determining that the processor is in a normal power state; means for measuring a duration that the processor is in a normal power state; means for determining whether the duration is greater than a duration threshold; and/or means for executing a third command to transition the processor from the normal power state to the idle power state.
Another aspect of the disclosure provides a computer-readable medium storing computer-executable code operable on a device, the device comprising at least one processor and at least one memory coupled to the at least one processor, and the at least one processor configured to manage a DC power source, the computer-executable code comprising: instructions for causing a computer to execute a first command, wherein the first command is associated with a unique group tag; instructions for causing a computer to compare the unique group tag to the master group tag; instructions for causing a computer to determine whether an interrupt is detected; instructions for causing the computer to lock the master group tag to produce a locked master group tag; instructions for causing the computer to execute a second command, wherein the second command is associated with the locked master group tag; instructions for causing a computer to determine that an end of a command in a locked main group tag has been reached; and instructions for causing the computer to execute a sequence jump command to return the processor to a normal power state. In one aspect, the computer executable code further comprises one or more of: instructions for causing a computer to organize a plurality of commands into a plurality of sequentially arranged commands; instructions for causing a computer to group a plurality of sequentially ordered commands into a plurality of groups, wherein each command of the plurality of sequentially ordered commands is associated with a group of the plurality of groups; instructions for causing a computer to assign a unique group tag to one of a plurality of groups, wherein the first command is a command in one group; instructions for causing a computer to determine that a processor is in a normal power state; instructions for causing a computer to measure a duration of time that a processor is in a normal power state; instructions for causing a computer to determine whether the duration is greater than a duration threshold; and/or instructions for causing the computer to execute a third command to transition the processor from the normal power state to the idle power state.
These and other aspects of the invention will be more fully understood upon reading the following detailed description. Other aspects, features and embodiments of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific exemplary embodiments of the invention in conjunction with the accompanying figures. While features of the invention may be discussed with respect to certain embodiments and figures below, all embodiments of the invention may include one or more of the advantageous features discussed herein. In other words, while one or more embodiments may be discussed as having certain advantageous features, one or more such features may also be used in accordance with the various embodiments of the invention discussed herein. In a similar manner, although example embodiments may be discussed below as device, system, or method embodiments, it should be understood that such example embodiments may be implemented in a variety of devices, systems, and methods.
Drawings
Fig. 1 illustrates an example block diagram of a DC power management system.
Fig. 2 illustrates a comparison of a conventional power profile to a first example power profile of a processor system using the DC power management system of the present disclosure.
Fig. 3 illustrates a second example power distribution of a processor system using the DC power management system of the present disclosure.
Fig. 4 shows an example low power state information table for different DC power states.
FIG. 5 illustrates an example command arrangement.
FIG. 6 shows an example execution flow according to the example command arrangement of FIG. 5.
FIG. 7 shows an example command sequence with a group tag.
FIG. 8 shows an example pass-through algorithm flow diagram.
Fig. 9 shows example timing of low power entry for different DC power states.
Fig. 10 illustrates a flow diagram of an example method for performing DC power management in accordance with various aspects of the disclosure.
Fig. 11 is an example block diagram of an illustrative hardware configuration for an apparatus including a processor coupled to a memory for performing DC power management in accordance with various aspects of the present disclosure.
Detailed Description
The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. It will be apparent, however, to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.
Various aspects of the present disclosure relate to systems and methods for power management. In a particular aspect, a processor system (e.g., a multi-processor system) may maintain different power states to optimize DC power savings. For example, the processor system may contain a DC power management system that idles (i.e., deactivates) a subset of the total number of processors when computing demand is low to minimize energy consumption (i.e., idle power state). In one example, the idle power state may include a deep low power state or a shallow low power state. For a particular processor system, a shallow low power state is defined as having a power consumption greater than a deep low power state. In other words, when the processor system is in the deep low power state, its power consumption will be less than when the processor system is in the shallow low power state. That is, the deep low power state consumes less power (has lower power consumption) than the shallow low power state. For example, computational requirements may be quantified by operands per second or instructions per second. DC power management systems may aim to balance battery life (i.e., minimize energy consumption) with processor performance.
The DC power management system may contain multiple sequential logic stages to enter a deep low power state, which is one example of an idle power state. In one example, a deep low power state may increase latency. Once the sequence for entering the deep low power state is initiated, the sequence may continue until the deep low power state is reached unless an interrupt occurs. An interrupt is an unplanned request to the processor system to return to a normal power state. When an interrupt occurs asynchronously within the sequence for entering the deep low power state, the DC power management system may return and begin the process for restoring the processor system to its normal power state by aborting the sequence entering the deep low power state. In one example, if the sequence of entering the deep low power state is in its last phase, for example, the DC power management system may mask (i.e., ignore) the interrupt until the deep low power state is reached.
If entering the deep low power state is not at its last stage, continuing to sequentially advance toward the deep low power state before resuming the normal power state will increase inefficiencies and latency. The delay is defined as the time delay to return to the normal power state. Also, the DC power management system may attempt to improve latency by placing the processor system in a shallow low power state. The shallow low power state has better DC power consumption efficiency than the conventional power state because the shallow low power state consumes less DC power than the conventional power state. That is, the shallow low power state consumes less power (has lower power consumption) than the conventional power state. However, the shallow low power state does consume more DC power than the deep low power state. If the DC power management system instructs the processor system to enter a shallow low power state to reduce latency to more quickly revert to a regular power state, the DC power consumption may be unnecessarily increased. Therefore, merely placing a processor system in a shallow low power state may not always be a desirable power consumption solution.
Fig. 1 illustrates an example block diagram of a DC power management system 100. As shown in fig. 1, DC power management system 100 includes a time counter 110 and a sequencer 120. Processor system (e.g., CPU)150c1、150c2、150c3……150cnIs shown connected to the DC power management system 100. The DC power management system 100 may manage the processor system 150c1、150c2、150c3……150cnPower consumption of one or more of.
In one example, the time counter 110 is used to help determine when to transition from one power state to another; i.e., a power state transition (e.g., a transition from a normal power state to a deep low power state). In one example, sequencer 120 executes commands required to transition from one power state to another.
In one aspect, the improved DC power management system sequencer effects a power state transition upon expiration of the first duration T1. The first duration T1 is measured by the time counter 110. The time counter 110 may be implemented by a clock. The clock may include, for example, an oscillator and a counter. In one example, the time counter 110 may be an oscillator and a counter. In one aspect, the time counter 110 may be initially set to a counter value corresponding to the first duration T1, and the counter value may be decremented until it reaches zero. The counter value may be predetermined or may be adjusted depending on the application (e.g., by the user).
In one aspect, sequencer 120 includes an interrupt handling process that includes a set of commands. For example, the sequencer includes sequencer logic for setting preprogrammed time limits for power state transitions. In one example, the sequencer logic is executed by a component separate from the processors in the processor system. In another example, the sequencer logic is executed by one of the processors in the processor system. Also, sequencer 120 may be an external component from the processor system. Alternatively, sequencer 120 may be one of the processors in a processor system.
In one example, sequencer 120 employs pass-through mechanism 130 to improve wake performance from an idle power state. In one example, pass-through mechanism 130 includes a sequence of commands to reduce latency in transitioning power state transitions. Wake performance may be measured by the amount of time required to transition from an idle power state to a regular power state. For example, commands for transitioning from one power state to another power state (e.g., transitioning from a regular power state to an idle power state, which may be a deep low power state) may be grouped into two or more groups. For example, the command sequences in each group (i.e., command group) may be associated with a tag. Each command group includes one or more commands. The command groups may be placed in order and may be executed in order. In one example, the order of the command groups may be predetermined. In another example, the order of the command sets may be adjusted according to a particular application, according to a particular power state of the processor system, or as determined by a user.
In one example, as each command group is executed, an interrupt check is performed. If an interrupt is detected, sequencer 120 continues to execute commands in the particular command group that was being executed at the time the interrupt occurred (i.e., the interrupt command group). Once all of the commands within the interrupt command set have been executed, sequencer 120 may execute sequence jump commands to return the processor system to a normal power state. The sequence jump command is a command for executing one or more commands associated with transitioning the processor system from the power state at the time the interrupt was detected to the normal power state. By executing the sequence jump command, the processor system returns to the trace back to its normal power state when an interrupt is detected and after the commands in the interrupt command set are executed. Thus, latency is minimized by the sequence jump command and the processor system returns to its normal power state without first reaching the idle power state (e.g., deep low power state), since completion of the transition to the idle power state (e.g., deep low power state) is avoided upon detection of the interrupt.
In one aspect, the DC power management system 100 tracks entry sequence commands that are executed prior to a power transition, at wake-up, or while in a normal power state. The DC power management system 100 also selectively triggers a minimum number of recovery sequence commands to restore the processor system to a normal power state to execute the commands in the command group. An enter sequence command is a set of commands that are executed between the time the processor system is in an inactive state (i.e., prior to waking up) or a normal power state until an interrupt is detected. The resume sequence command is a set of commands that need to be executed to resume the processor system from whatever state the processor system is currently in to the normal power state. In one example, sequencer 120 (which is part of DC power management system 100) is a component that tracks incoming sequence commands and triggers a resume sequence command.
In one aspect, once an interrupt is detected, DC power management system 100 (such as sequencer 120) may instruct the processor system to return to a normal power state. Upon returning to the normal power state, the time counter 110 may be activated. In one example, timing activation may be achieved by setting a time limit in a state element (e.g., a register or memory location) of a time counter. Upon expiration of the first duration T1, and if no additional conditions indicate to remain in the normal power state, the DC power management system 100 (such as the sequencer 120) may continue to transition the processor system from the normal power state back to an idle power state (e.g., a shallow low power state or a deep low power state).
In another aspect, during a transition from a normal power state to a deep low power state, the DC power management system 100 (such as the sequencer 120) may remain idle in a shallow low power state for a second duration T2. The second duration T2 may be measured by the time counter 110. Upon expiration of the second duration T2, and if no additional conditions indicate that the processor system remains in the shallow low power state or returns to the normal power state, the DC power management system 100 (such as sequencer 120) may continue to transition to the deep low power state. The timing feature having the first duration and/or the second duration to help enable transitions between power states may improve DC power management efficiency and may reduce latency.
In one example, the duration of the time counter 110 may be based on the number of logical passes. In one example, a logical cut-through is an event such as: where interrupts occur while the sequence is being executed and certain sequence steps need to be aborted or bypassed to restore the normal power state as soon as possible. For example, the amount of logical pass-through may be related to the number of command groups in the command sequence. In one example, the first duration T1 and/or the second duration T2 may be proportional to the number of command groups in the command sequence. In another example, the first duration T1 and/or the second duration T2 may be monotonically related to the number of command groups in the command sequence.
Fig. 2 illustrates a comparison 200 of a conventional power profile 210 and a first example power profile 220 of a processor system using the DC power management system of the present disclosure. In fig. 2, the normalized DC power consumption is shown on the vertical axis, and time is shown on the horizontal axis. In the example of FIG. 2, the normalized DC power consumption has a value of unity 1 ("1") when the processor system is in the normal power state. In fig. 2, the normalized DC power consumption is expressed in normalized units of DC power with respect to the DC power in the normal power state. Time is represented as a sequence index, where each command sequence may have a unique sequence index that monotonically increases over time. As shown in fig. 2, even if an interrupt 250 is detected, the conventional system continues the transition from its normal power state (whose normalized DC power consumption is 1) to the deep low power state (whose normalized DC power consumption is 0). In the power profile 220 of a processor system using the DC power management system of the present disclosure, once an interrupt 250 is detected, steps are taken to return to a normal power state. As shown in power profile 220, once interrupt 250 is detected, there is a short duration that causes power profile 220 to remain flat at 0.6 normalized DC power consumption (in this example), and then a tilt of power profile 220 until it reaches a value of 1, which is a normal power state. In one example, a short duration in which power profile 220 is flat at 0.6 normalized DC power consumption may indicate: a duration when the remaining commands in the interrupt command set are executed. And, a tilt in the power profile 220 until it returns to a value of 1 at the fifth sequence index may indicate: when executing the resume sequence command to resume the processor system to a normal power state.
Fig. 3 illustrates a second example power profile 300 of a processor system using the DC power management system of the present disclosure. In fig. 3, the power profile 300 is shown normalized. The normalized DC power consumption is shown on the vertical axis and time is shown on the horizontal axis. In fig. 3, the power profile 300 includes two branches: an interrupted power profile 350 and an uninterrupted power profile 330. Interrupt power profile 350 shows: normalized power consumption versus time for low power switching when an interrupt 310 (i.e., interrupt scenario) is detected. The uninterrupted power profile 330 shows: normalized power consumption versus time for low power switching when no interrupt 310 is detected (i.e., no interrupt scenario).
As shown in power profile 300, if there is no interrupt, the processor system is first placed in a shallow low power state under the fifth sequential index before proceeding to a deep low power state. In fig. 3, the normalized DC power consumption has a value of unit 1 when in the normal power state. In this example, the normalized DC power consumption is expressed in normalized units of DC power relative to the DC power in the normal power state. Time is represented as a sequence index, where each command sequence may have a unique sequence index that monotonically increases over time. In this example, the interrupted power profile 350 and the uninterrupted power profile 330 both begin in a regular power state with a normalized DC power consumption of unit 1 ("1"). Then, in this example, in the fourth sequence index, the power profiles (the interrupted power profile 350 and the uninterrupted power profile 330) transition to a shallow low power state, whose normalized DC power consumption is 0.6 in this example. In the seventh sequence index, two power profiles (the interrupted power profile 350 and the uninterrupted power profile 330) diverge.
For the interrupt power profile 350 where the interrupt 310 (i.e., interrupt scenario) is detected at the seventh sequence index, the interrupt power profile 350 returns to the normal power state with normalized DC power consumption at unit 1 ("1") until the end of the duration. The duration may be measured by a time counter 110. In one example, the duration 320 may be programmed or predetermined. Upon expiration of the duration, the interrupt power profile 350 then transitions to the deep low power state, whereby fig. 3 shows that in this example, the fifteenth sequence index reaches the deep low power state. Beyond the fifteenth sequence index, FIG. 3 also shows the processor system in a deep low power state.
For the no-break power profile 330 where no break is detected (i.e., no-break scenario), the no-break power profile 330 continues its transition to the deep low power state reached by the eleventh sequence index at the seventh sequence index. Beyond the eleventh sequence index, FIG. 3 also shows the processor system in a deep low power state.
Fig. 4 illustrates an example low power state information table 400 for different DC power states. Five DC power states are shown in fig. 4, namely C0 being a normal power state and C1 through C4 being idle power states, ranging from a shallow low power state to a deep low power state. In the example of FIG. 4, C1 is the shallowest low power state and C4 is the deepest low power state. The example low power state information table 400 shows trends to increase wake-up time, increase target dwell time, and decrease DC power consumption as the power state transitions sequentially from C0 to C4. In the example of fig. 4, the target dwell time is the target duration for the DC power state. Those skilled in the art will appreciate that these five different power consumptions are not exclusive, and that the processor system may operate in other different DC power states not shown in fig. 4 and still be within the scope and spirit of the present disclosure.
Fig. 5 illustrates an example command arrangement 500. In FIG. 5, a command arrangement 500 shows a sequence of commands organized in order within processor registers. In the example of FIG. 5, the processor registers are 32-bit AHB (AMBA high Performance bus) registers. AMBA stands for ARM advanced microcontroller bus architecture, where the acronym "ARM" is a trade name. Those skilled in the art will appreciate that although many skilled in the art may use the AMBA high performance bus register (i.e., AHB register), the present disclosure does not preclude other types of registers. Accordingly, the use of other types of registers is within the scope and spirit of the present disclosure. In one example, the command sequence includes a set of complementary command pairs CMDx and CMDx ', where CMDx is a power down command for component x and CMDx' is a complementary power down command for component x. In this example, the power up sequence is the inverse of the power up sequence.
FIG. 6 illustrates an example execution flow 600 according to the example command arrangement 500 of FIG. 5. Execution of flow 600 begins with a trigger event. In block 610, the processor system (e.g., CPU) triggers a command "standbywfi" to cause the processor system to enter an idle power state (also referred to as a standby power state). In block 620, the DC power management system executes a first enter sequence command (cmd1) to cause the processor system (e.g., CPU) to enter a sleep mode. In one example, the sleep mode may be a shallow low power state. In one example, the sleep mode may be a deep low power state. After block 620, in block 630, the DC power management system executes a second enter sequence command (cmd2) to cause the processor system (e.g., CPU) to enter a sleep mode (e.g., a shallow low power state). In block 640, the processor system (e.g., CPU) is in a sleep mode (e.g., a shallow low power state or a deep low power state).
In block 620, it is determined whether one or more wake-up triggers 615 are detected. In one example, the interrupt is a wake trigger. If one or more wake triggers 615 are detected in block 620, then block 660 is advanced through the first bypass path 625 instead of block 630. Similarly, in block 630, it is determined whether one or more wake-up triggers 615 are detected. If one or more wake triggers 615 are detected in block 630, then block 650 is advanced through a second bypass path 635, instead of block 640.
In block 650, the DC power management system executes a third enter sequence command (cmd3) to cause the processor system (e.g., CPU) to enter into a task mode. In one example, the mission mode is a normal power state. In block 660, the DC power management system executes a fourth enter sequence command (cmd4) to cause the processor system (e.g., CPU) to enter a task mode. In block 670, the processor system (e.g., CPU) is in a task mode (e.g., a normal power state).
FIG. 7 shows an example command sequence 700 with a group tag. The command sequence 700 includes, for example, an enter sequence command action list 710 and an exit sequence command action list 720. The entry sequence command action list 710 includes a plurality of entry sequence commands, where each entry sequence command appears as a row in the entry sequence command action list 710. As shown in fig. 7, each entry sequence command includes three components: a command opcode, an enter sequence command action, and a group tag. Those skilled in the art will appreciate that the three components shown for the enter sequence command are not exclusive or mandatory. That is, none of the three components shown need be included, and other components may be included and are within the scope and spirit of the present disclosure.
Similarly, the exit sequence command action list 720 includes a plurality of exit sequence commands, where each exit sequence command appears as a row in the exit sequence command action list 720. As shown in FIG. 7, each exit sequence command includes three components: command opcode, exit sequence command action, and group tag. Those skilled in the art will appreciate that the three components shown for the exit sequence command are not exclusive or mandatory. That is, none of the three components shown need be included, and other components may be included and are within the scope and spirit of the present disclosure. In one aspect, the exit sequence command is a recovery sequence command.
In one aspect, all command sequences are divided into groups such that if any command from a group is executed to enter an idle power state, all commands in the group must be executed to get the processor hardware to function properly. For example, the on reset and the off reset are assigned to the same group. That is, if the reset is turned on to enter the idle power state, the reset must be turned off to exit. As another example, if there is a first command to trigger opening of the headswitch and a second command to wait for its acknowledgement, the first command and the second command are executed together and thus assigned to the same group. Correspondingly, the headswitches are turned off and wait for their acknowledgement to be performed together and assigned to the same group. In addition, grouping of commands is done so that the number of commands per group can be minimized. In another aspect, the command packet may be dynamically configured by software. In addition, each group is assigned a group tag. In one example, each group tag is unique.
In the example command sequence 700, each command opcode may include two hexadecimal digits. In one example, the group tag identifies a command group. In one example, when an interrupt is detected, all sequence command actions (e.g., entry sequence command actions) having the same group tag as the particular entry sequence command action currently being executed are allowed to be executed before the interrupt is processed (i.e., before other commands (e.g., a resume sequence command) are executed to restore the processor system to a normal power state). In fig. 7, the command group in the incoming sequence command action with group tag 6 is specifically identified. Similarly, the command group in the exit sequence command action with group tag 6 is specifically identified.
Fig. 8 shows an example pass-through algorithm flow diagram 800. In block 810, a low power entry sequence is initiated. In one example, a low power entry sequence is performed to enter an idle power state. The idle power state may be a shallow low power state, a deep low power state, or any idle power state that consumes less power than a regular power state. For example, the extent of different power consumption with different DC power states C0, C1, C2, C3, C4 is shown in fig. 4. Those skilled in the art will appreciate that the different power consumptions are not limited to the five DC power states shown in fig. 4.
In block 820, the command is executed. In one example, the command is one of the command actions shown in FIG. 7. In block 830, it is determined whether the group tag (also referred to as a command tag value) associated with the executing command exceeds the master group tag (also referred to as a master group tag value). In one example, the main group tag is a reference tag value. In one aspect, the primary group tag also represents a group for the set of commands currently being executed. If not, proceed to block 835 to retain the main group tag. After block 835, proceed to block 850. If so, then proceed to block 840 to update the main group tag. In one example, the update indicates incrementing the main group tag by a value such as "1", for example. One skilled in the art will appreciate that the increment units may be a design choice or an application choice, and may be predetermined or adjusted by a user. After block 840, proceed to block 850.
In block 850, the interrupt is checked. If no interruption is detected, return to block 820. If an interrupt is detected, proceed to block 860. At block 860, the master group tag is locked. In one example, locking the master group tag means that the master group tag is not allowed to increment. In block 870, proceed to the next command and determine if the next command tag value exceeds the main group tag. If not, proceed to block 875. In block 875, the next command is executed. After block 875, proceed to block 890. If so, proceed to block 880 and ignore the next command (i.e., perform no operation "NOP"). After block 880, proceed to block 890. In block 890, it is determined whether the next command is an end command. If not, proceed to block 870. If so, then proceed to block 895. In block 895, the low power entry sequence is ended.
Fig. 9 illustrates an example timing sequence 900 for low power input for different DC power states. In the example timing sequence 900, the variation of normalized DC power consumption over time is shown for four idle power states C1, C2, C3, C4 ordered from the shallowest to the deepest low power state. C0 is the normal power state. In fig. 9, the normalized DC power consumption is shown on the vertical axis, and time is shown on the horizontal axis. Time is represented as a sequence index, where each command sequence may have a unique sequence index that monotonically increases over time. In one example, the power states shown in fig. 9 (idle power states C1, C2, C3, C4, and regular power state C0) have the same wake time, target dwell time, and power consumption values as the power states shown in fig. 4.
Fig. 10 illustrates a flowchart 1000 of an example method for performing DC power management in accordance with various aspects of the present disclosure.
In block 1010, the plurality of commands are organized into a plurality of sequentially arranged commands. In one example, the plurality of commands are organized in a sequence for execution. These commands are enter sequence commands. The enter sequence command may include a command to place the processor system in an idle power state. The idle power state may be, for example, a shallow low power state or a deep low power state.
In block 1015, the plurality of sequentially ordered commands are grouped into a plurality of groups, wherein each command of the plurality of sequentially ordered commands is associated with a group of the plurality of groups. That is, each of the plurality of sequentially arranged commands belongs to one of the plurality of groups. Also, the grouping preserves the order of the multiple commands.
In block 1020, a unique group tag is assigned to one of the plurality of groups. That is, each group of the plurality of groups is associated with a group tag that is unique to the group.
In block 1025, each command in a group is associated with a unique group tag.
In block 1030, a command (e.g., a first command) of the plurality of sequentially ordered commands in a group is executed. The first command is a command that is ordered in the order of the commands in a group as the next command to be executed. In block 1035, it is determined whether all commands in the current group have been executed. If so, proceed to block 1040. If not, proceed to block 1045.
In block 1040, the unique group tag is compared to the master group tag. If the unique group of tags is greater than the primary group of tags, the primary group of tags is updated. In one example, updating the master group tag is incrementing the value of the master group tag by a predetermined number. If the unique group tag is not greater than the primary group tag, then no action is taken (i.e., the primary group tag is not updated). In an alternative example, block 1040 includes determining whether the first duration is greater than a first duration threshold. In one example, the first duration is an amount of latency before continuing to transition to another idle power state (e.g., a deep low power state) in the shallow low power state. The first duration threshold may be predetermined or adjusted according to the application, design, or user selection. If the first duration is not greater than the first duration threshold, no further action is taken. If the first duration is greater than the first duration threshold, proceed to block 1045. In one example, the time counter 110 may be used to measure the first duration. In one example, the time counter 110 may be used to determine whether the first duration is greater than a first duration threshold.
In block 1045, it is determined whether an interrupt is detected. If not, proceed to block 1030. If so, proceed to block 1050. In block 1050, the master group tag is locked to produce a locked master group tag. In one example, locking the master group tag indicates that the master group tag is not allowed to be updated (i.e., the value is not incremented).
In block 1055, the group tag of the second command is compared to the locked master group tag. If the group tag of the second command is greater than the locked master group tag, block 1060 is advanced and the second command is not executed. If the group tag of the second command is not greater than the locked master group tag, proceed to block 1065.
In block 1060, the second command is ignored and flow proceeds to block 1070. By ignoring the second command, the second command is not executed. That is, no operation "NOP" is performed.
In block 1065, a second command is executed. The second command is a command in the group associated with the locked master group tag that is ordered as the next command to be executed. In one example, the group associated with the locked master group tag is the current group mentioned in block 1035.
In block 1070, a determination is made whether the end of the command in the group associated with the locked master group tag has been reached. If not, block 1055 returns. If so, proceed to block 1075.
In block 1075, a sequence jump command is executed to return the processor system to a normal power state. The sequence jump command is a command for executing one or more commands associated with transitioning the processor system from the power state at the time the interrupt was detected to the normal power state.
In block 1080, it is determined that the processor is in a normal power state and a second duration of time that the processor is in the normal power state is measured. In one example, the second duration is measured using a time counter. In one example, the time counter 110 may be used to measure the second duration.
In block 1085, it is determined whether the second duration is greater than a second duration threshold. In one example, the second duration is an amount of latency after returning to the normal power state before transitioning to the idle power state. The second duration threshold may be predetermined or adjusted according to the application, design, or user selection. If the second duration is not greater than the second duration threshold, proceed to block 1080. If the second duration is greater than the second duration threshold, proceed to block 1090. In one example, the time counter 110 may be used to determine whether the second duration is greater than a second duration threshold.
In block 1090, a third command is executed to place (i.e., transition to) the processor in an idle power state. The idle power state may be a shallow low power state, a deep low power state, or any idle power state that consumes less power than a regular power state. In one aspect, each step in each block of fig. 10 may be implemented by one or more of: a DC power management system (e.g., DC power management system 100 of fig. 1); a sequencer (e.g., sequencer 120 of FIG. 1 or sequencer 120 employing pass-through mechanism 130 as shown in FIG. 1); a software algorithm (e.g., software 1150; processor 1100; or a processor coupled to a memory (e.g., processor 1110 and memory 1120 of fig. 11)).
Fig. 11 is an example block diagram of an illustrative hardware configuration for an apparatus 1100 including a processor 1110 coupled to a memory 1120 for performing DC power management in accordance with various aspects of the present disclosure. In this example, the processor 1110 may be implemented with a bus architecture, represented generally by the bus 1130. The bus 1130 may include any number of interconnecting buses and bridges depending on the specific application of the device 1100 and the overall design constraints. The bus 1130 may link other circuitry (not shown) including the computer-readable medium 1140 to the processor 1110 and the memory 1120. Although computer-readable media are described herein, those skilled in the art will appreciate that a single computer-readable medium is also within the scope and spirit of the present disclosure. The bus 1140 may also link various other circuits such as timing sources, peripherals, and voltage regulators, which are well known in the art and therefore, will not be described further.
In one example, the memory 1120 may be used to store data or information. For example, the memory 1120 may store commands and/or parameters related to commands (such as, but not limited to, command codes, group tags, etc.).
In one example, the processor 1110 may manage the bus 1130 and general processing, including the execution of software 1150 stored on a computer-readable medium 1140 and/or memory 1120. In one aspect, processor 1110 may include multiple processors and may include microprocessors, microcontrollers, Digital Signal Processors (DSPs), Field Programmable Gate Arrays (FPGAs), Programmable Logic Devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout this disclosure.
Processor 1110 may execute software 1150. Software should be construed broadly to refer to instructions, instruction sets, code segments, program code, programs, subprograms, software modules, applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or the like. The software may reside on computer-readable medium 1140. The computer-readable medium 1140 may be a non-transitory computer-readable medium. By way of example, a non-transitory computer-readable medium includes, for example, a magnetic storage device (e.g., hard disk, floppy disk, magnetic strip), an optical disk (e.g., Compact Disk (CD) or Digital Versatile Disk (DVD)), a smart card, a flash memory device (e.g., card, stick, or key drive), a Random Access Memory (RAM), a Read Only Memory (ROM), a programmable ROM (prom), an erasable prom (eprom), an electrically erasable prom (eeprom), a register, a removable disk, and any other suitable medium for storing software and/or instructions that may be accessed and read by a computer.
By way of example, computer-readable media may also include carrier waves, transmission lines, and any other suitable media for transmitting software and/or instructions that may be accessed and read by a computer. In one example, computer-readable medium 1140 may reside in processor 1110. In another example, computer-readable medium 1140 may be external to processor 1110 (as shown in fig. 11). In yet another example, computer-readable media 1140 may be distributed across multiple entities including processor system 1110. The computer-readable medium 1140 may be embodied in a computer program product. By way of example, the computer program product may comprise a computer-readable medium in a packaging material. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure, depending on the particular application and the overall design constraints imposed on the overall system.
The steps in fig. 6, 8, and 10 may be performed by one or more of the circuitry described in fig. 11, in accordance with aspects of the present disclosure. In the above examples, the circuitry included in apparatus 1100 is provided merely as an example, and other means for performing the various functions described may be included within the various aspects of the disclosure, including, but not limited to, instructions stored in computer-readable medium 1140, or any other suitable means or means described in any one of the figures and utilizing the processes and/or algorithms described herein, e.g., with respect to fig. 6, 8, and 10.
Several aspects of DC power management have been proposed. As those skilled in the art will readily appreciate, the various aspects described throughout this disclosure may be extended to various types of DC power management on various types of circuits, components, or devices.
Within this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration. Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term "coupled" is used herein to mean a direct or indirect coupling between two objects. For example, if object a physically touches object B, while object B touches object C, objects a and C may still be considered to be coupled to each other even though they are not physically touching each other directly. For example, a first die may be coupled to a second die in a package even though the first die is never in direct physical contact with the second die. The terms "circuit" and "circuitry" are used broadly and are intended to include both hardware implementations of electrical devices and conductors (which when connected and configured are capable of performing the functions described in this disclosure, without limitation by the type of electronic circuitry) as well as software implementations of information and instructions (which when executed by a processor are capable of performing the functions described in this disclosure).
One or more components, steps, features and/or functions illustrated in the figures may be rearranged and/or combined into a single component, step, feature or function or implemented into several components, steps or functions. Additional elements, components, steps, and/or functions may also be added without departing from the novel features disclosed herein. The apparatus, devices, and/or components shown in the figures may be configured to perform one or more of the methods, features, or steps described herein. The novel algorithms described herein may also be effectively implemented in software, and/or embedded in hardware.
It should be understood that the specific order or hierarchy of steps in the methods disclosed is an illustration of exemplary processes. It should be understood that the specific order or hierarchy of steps in the methods may be rearranged based on design preferences. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented unless specifically recited therein.
The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean "one and only one" unless specifically so stated, but rather "one or more. The term "some" means one or more unless specifically stated otherwise. A phrase referring to "at least one of" a list of items refers to any combination of those items, including a single member. For example, "at least one of a, b, or c" is intended to encompass: a; b; c; a and b; a and c; b and c; and a, b and c. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Furthermore, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element should be construed in accordance with the provisions of 35u.s.c. § 112 sixth paragraph unless the element is explicitly recited using the phrase "means for … …", or in the case of the method claims, the element is recited using the phrase "means for … …".