阅读说明：本技术 半导体集成电路装置 (Semiconductor integrated circuit device having a plurality of semiconductor chips ) 是由 祖父江功弥 于 2018-04-25 设计创作，主要内容包括：就包括多列IO单元的半导体集成电路装置而言,提供一种能够在不使面积增大的情况下避免闩锁错误的构成。半导体集成电路装置包括布置得离芯片边缘最近的IO单元列(10A)和在比IO单元列(10A)靠核心区域一侧相邻布置的IO单元列(10B)。IO单元列(10A、10B)的IO单元(10)具有在与IO单元(10)的排列方向垂直的方向上分开而设的高电源电压区域(12)和低电源电压区域(11)。IO单元列(10A、10B)布置为IO单元列(10A)的高电源电压区域(12)与IO单元列(10B)的高电源电压区域(12)彼此相向。(Provided is a semiconductor integrated circuit device including a plurality of columns of IO cells, wherein a latch-up error can be avoided without increasing the area. The semiconductor integrated circuit device includes an IO cell column (10A) disposed closest to an edge of a chip and an IO cell column (10B) disposed adjacent to the IO cell column (10A) on a side closer to a core region. The IO cells (10) of the IO cell columns (10A, 10B) have a high power supply voltage region (12) and a low power supply voltage region (11) that are provided apart in a direction perpendicular to the arrangement direction of the IO cells (10). The IO cell columns (10A, 10B) are arranged so that the high power supply voltage region (12) of the IO cell column (10A) and the high power supply voltage region (12) of the IO cell column (10B) face each other.)

1. A semiconductor integrated circuit device, characterized in that:

the semiconductor integrated circuit device includes a chip, a core region and an IO region,

the core region is provided on the chip,

the IO regions are disposed on the chip and around the core region,

in the IO region, two or more IO cell rows each including a plurality of IO cells arranged in a first direction are arranged in a second direction, the first direction is a direction extending along an outer side of the chip, the second direction is perpendicular to the first direction,

the IO cell columns more than two columns include a first IO cell column and a second IO cell column,

the first IO cell column is disposed closest to an edge of the chip in two or more of the IO cell columns,

the second IO cell column is arranged on the core region side of the first IO cell column so as to be adjacent to the first IO cell column,

the IO cells of the first IO cell column and the IO cells of the second IO cell column have a high power supply voltage region and a low power supply voltage region, respectively, the high power supply voltage region and the low power supply voltage region being separately provided in the second direction,

the first IO cell column and the second IO cell column are arranged such that the high power supply voltage region of the first IO cell column and the high power supply voltage region of the second IO cell column face each other.

2. The semiconductor integrated circuit device according to claim 1, wherein:

the high power supply voltage region has a P-type transistor region and an N-type transistor region provided separately in the second direction,

the first IO cell column and the second IO cell column are arranged such that the P-type transistor regions of the first IO cell column and the P-type transistor regions of the second IO cell column face each other.

3. The semiconductor integrated circuit device according to claim 1, wherein:

the dimension of the IO cell of the first IO cell column in the second direction and the position in the second direction are the same,

the dimension of the IO cell of the second IO cell column in the second direction is the same as the position in the second direction.

4. The semiconductor integrated circuit device according to claim 1, wherein:

in the first IO cell column and the second IO cell column, the dimension of the opposing IO cells in the first direction is the same as the position in the first direction.

5. The semiconductor integrated circuit device according to claim 1, wherein:

in the first IO cell row and the second IO cell row, a space through which a signal line can pass is provided between the IO cell groups facing each other.

6. The semiconductor integrated circuit device according to claim 1, wherein:

with respect to the first IO cell column and the second IO cell column, between the IO cells facing each other, a power supply line extending in the first direction is arranged.

7. The semiconductor integrated circuit device according to claim 1, wherein:

first power supply lines extending in the first direction are respectively disposed in the high power supply voltage regions of the IO cells of the first IO cell column and the high power supply voltage regions of the IO cells of the second IO cell column,

in the first IO cell column and the second IO cell column, an upper power supply line is arranged in a wiring layer on an upper layer than the first power supply line, the upper power supply line being formed to extend in the second direction and to connect the first power supply lines to each other.

8. The semiconductor integrated circuit device according to claim 7, wherein:

the semiconductor integrated circuit device includes pads provided for external connection to the chip,

the upper power supply line is formed in the same wiring layer as the pad.

9. A semiconductor integrated circuit device, characterized in that:

the semiconductor integrated circuit device includes a chip, a core region and an IO region,

the core region is provided on the chip,

the IO region is disposed on the chip around the core region and includes a first IO cell block and a second IO cell block adjacent in a first direction, the first direction being a direction extending along an outer side of the chip,

in the first IO cell block, two or more IO cell columns respectively including a plurality of IO cells arrayed in the first direction are arrayed in a second direction, the second direction being perpendicular to the first direction,

the IO cell columns more than two columns include a first IO cell column and a second IO cell column,

the first IO cell column is disposed closest to an edge of the chip in two or more of the IO cell columns,

the second IO cell column is arranged on the core region side of the first IO cell column so as to be adjacent to the first IO cell column,

in the second IO cell block, only one third IO cell column including a plurality of IO cells arranged in the first direction is arranged,

the IO cells of the first to third IO cell columns have a high power supply voltage region and a low power supply voltage region, respectively, the high power supply voltage region and the low power supply voltage region being separately provided in the second direction,

the first IO cell column and the second IO cell column are arranged such that the high power supply voltage region of the first IO cell column and the high power supply voltage region of the second IO cell column face each other,

the third IO cell column is arranged such that the high power supply voltage region of the third IO cell column is located on one side of an edge of the chip.

10. The semiconductor integrated circuit device according to claim 9, wherein:

the first IO cell column and the third IO cell column are arranged in a column along the first direction.

11. The semiconductor integrated circuit device according to claim 9, wherein:

the size of the IO cell in the first IO cell column and the position of the IO cell in the third IO cell column in the second direction are the same.

12. The semiconductor integrated circuit device according to claim 9, wherein:

between the first IO cell block and the second IO cell block, a power supply line extending in the second direction is arranged.

13. The semiconductor integrated circuit device according to claim 9, wherein:

the high power supply voltage region has a P-type transistor region and an N-type transistor region provided separately in the second direction,

the first IO cell column and the second IO cell column are arranged such that the P-type transistor regions of the first IO cell column and the P-type transistor regions of the second IO cell column face each other.

14. The semiconductor integrated circuit device according to claim 9, wherein:

the dimension of the IO cell of the first IO cell column in the second direction and the position in the second direction are the same,

the dimension of the IO cell of the second IO cell column in the second direction is the same as the position in the second direction.

15. The semiconductor integrated circuit device according to claim 9, wherein:

in the first IO cell column and the second IO cell column, the dimension of the opposing IO cells in the first direction is the same as the position in the first direction.

16. The semiconductor integrated circuit device according to claim 9, wherein:

in the first IO cell row and the second IO cell row, a space through which a signal line can pass is provided between the IO cell groups facing each other.

17. The semiconductor integrated circuit device according to claim 9, wherein:

with respect to the first IO cell column and the second IO cell column, between the IO cells facing each other, a power supply line extending in the first direction is arranged.

18. The semiconductor integrated circuit device according to claim 9, wherein:

first power supply lines extending in the first direction are respectively disposed in the high power supply voltage regions of the IO cells of the first IO cell column and the high power supply voltage regions of the IO cells of the second IO cell column,

in the first IO cell column and the second IO cell column, an upper power supply line is arranged in a wiring layer on an upper layer than the first power supply line, the upper power supply line being formed to extend in the second direction and to connect the first power supply lines to each other.

19. The semiconductor integrated circuit device according to claim 18, wherein:

the semiconductor integrated circuit device includes pads provided for external connection to the chip,

the upper power supply line is formed in the same wiring layer as the pad.

Technical Field

The present disclosure relates to a semiconductor integrated circuit device having a core region and an IO region arranged on a chip.

Background

In recent years, the scale of semiconductor integrated circuits has been increasing, and the number of input/output signals has been increasing. Therefore, if input-output cells (IO cells) are arranged as a single layer around the core region, there is a problem in that: since the area of the semiconductor integrated circuit depends on the number of IO cells, the area of a semiconductor integrated circuit device, which is a device formed of the semiconductor integrated circuit, may be increased.

Patent document 1 discloses a structure of a semiconductor integrated circuit device in which IO cells are arranged in a double layer. Patent document 2 discloses a structure of a semiconductor device in which IO cells are arranged in one row, two rows, and three columns.

Patent document 1: japanese laid-open patent publication No. 2003-100891

Patent document 2: specification of U.S. patent application publication No. 2005/0127405

Disclosure of Invention

Technical problems to be solved by the invention

The IO cell generally has a high power supply voltage region including an output buffer and the like for outputting signals to the outside of the ESD circuit or the semiconductor integrated circuit device, and a low power supply voltage region including a circuit portion and the like for inputting and outputting signals to the inside of the semiconductor integrated circuit device. In the low power supply voltage region, the same power supply voltage as that of the internal circuit formed in the core region of the chip is used.

In recent years, the power supply voltage inside the chip has been reduced due to the progress of miniaturization. However, the degree of reduction of the power supply voltage outside the chip does not reach the degree of reduction of the power supply voltage inside the chip, and in particular, there are cases where: the voltage reduction has not been advanced due to various interface standards and the like. Therefore, in the IO cell, the difference between the power supply potential in the high power supply voltage region and the power supply potential in the low power supply voltage region is large.

As a result, the difference between the voltages applied to the transistor and the well is large in the high power supply voltage region and the low power supply voltage region, and destruction due to so-called latch-up error is likely to occur. In order to prevent latch-up errors, it is necessary to maintain a sufficiently large distance between transistors and between wells between a high power supply voltage region and a low power supply voltage region. In particular, in a high power supply voltage region, it is necessary to adopt the above-described processing method for an output buffer and an ESD circuit which are directly connected to a terminal outside the chip and to which noise from outside the chip is easily applied.

However, in the configuration of fig. 1 of patent document 1, for example, the external signal terminal 14b on the high power supply voltage side of the IO cell in the second column faces the core region, and therefore, in order to prevent a latch-up error, a large space needs to be left between the IO cell and the core region. In the configuration of fig. 2 of patent document 2, since the low power supply voltage side of the first column IO cell 27 and the high power supply voltage side of the second column IO cell 28 face each other, a large space needs to be left between the IO cells 27, 28 in order to prevent a latch-up error.

Therefore, the configurations of patent documents 1 and 2 are not preferable because the area of the semiconductor integrated circuit device is increased to solve the problem of the latch error.

The present disclosure provides a configuration of a semiconductor integrated circuit device including a plurality of rows of IO cells, which is capable of avoiding a latch-up error without increasing an area.

Solution to the technical problem

In an aspect of the present disclosure, a semiconductor integrated circuit device includes a chip, a core region, and an IO region, the core region is provided on the chip, the IO region is provided on the chip and located around the core region, in the IO region, two or more IO cell rows respectively including a plurality of IO cells arranged in a first direction are arranged in a second direction, the first direction is a direction extending along an outer side of the chip, the second direction is perpendicular to the first direction, the two or more IO cell rows include a first IO cell row and a second IO cell row, the first IO cell row is arranged in the two or more IO cell rows to be closest to an edge of the chip, the second IO cell row is arranged closer to the core region than the first IO cell row in a manner adjacent to the first IO cell row, the IO cells of the first IO cell row and the IO cells of the second IO cell row have a high power supply voltage region and a low power supply voltage region which are separately set in the second direction, respectively, and the first IO cell row and the second IO cell row are arranged such that the high power supply voltage region of the first IO cell row and the high power supply voltage region of the second IO cell row are opposite to each other.

According to the above aspect, the semiconductor integrated circuit device includes the first IO cell column disposed closest to the edge of the chip and the second IO cell column disposed on the core region side of the first IO cell column in such a manner as to be adjacent to the first IO cell column. The IO cells of the first and second IO cell columns have a high power supply voltage region and a low power supply voltage region, respectively, which are provided to be separated in a second direction perpendicular to the arrangement direction of the IO cells. The first and second IO cell columns are arranged such that the high power supply voltage region of the first IO cell column and the high power supply voltage region of the second IO cell column face each other. That is, since the first IO cell column and the second IO cell column face each other in the high power supply voltage region, it is not necessary to provide a space between the first IO cell column and the second IO cell column in order to avoid a latch-up error. In addition, since the low power supply voltage region is located on the core region side of the second IO cell row, it is not necessary to leave a space on the core region side of the second IO cell row in order to avoid a latch-up error. As a result, a latch-up error can be avoided without increasing the area of the semiconductor integrated circuit device.

In another aspect of the present disclosure, a semiconductor integrated circuit device includes a chip, a core region and an IO region, the core region is provided on the chip, the IO region is provided on the chip and located around the core region, and includes a first IO cell block and a second IO cell block adjacent in a first direction, the first direction is a direction extending along an outer side of the chip, in the first IO cell block, two or more IO cell rows respectively including a plurality of IO cells arranged in the first direction are arranged in a second direction, the second direction is perpendicular to the first direction, the two or more IO cell rows include a first IO cell row and a second IO cell row, the first IO cell row is arranged in the two or more IO cell rows closest to an edge of the chip, the second IO cell row is arranged closer to the first IO cell row than the first IO cell row in a manner adjacent to the first IO cell row And on one side of the core region, only one third IO cell row is arranged in the second IO cell block, the third IO cell row includes a plurality of IO cells arranged in the first direction, the IO cells from the first IO cell row to the third IO cell row respectively have a high power supply voltage region and a low power supply voltage region that are set apart in the second direction, the first IO cell row and the second IO cell row are arranged such that the high power supply voltage region of the first IO cell row and the high power supply voltage region of the second IO cell row face each other, and the third IO cell row is arranged such that the high power supply voltage region of the third IO cell row is located on one side of the edge of the chip.

According to the above aspect, the semiconductor integrated circuit device includes the first and second IO cell blocks adjacent in the first direction which is the same as the arrangement direction of the IO cells. The first IO cell block includes a first IO cell column and a second IO cell column, the first IO cell column is disposed closest to an edge of the chip, and the second IO cell column is disposed on a side closer to the core region than the first IO cell column in a manner adjacent to the first IO cell column. The second IO cell block includes only one column of the third IO cell column. The IO cells of the first to third IO cell columns respectively have a high power supply voltage region and a low power supply voltage region that are provided separately in a second direction perpendicular to the arrangement direction of the IO cells. The first and second IO cell columns are arranged such that the high power supply voltage region of the first IO cell column and the high power supply voltage region of the second IO cell column face each other. That is, since the first IO cell column and the second IO cell column face each other in the high power supply voltage region, it is not necessary to provide a space between the first IO cell column and the second IO cell column in order to avoid a latch-up error. In addition, since the low power supply voltage region is located on the core region side of the second IO cell row, it is not necessary to leave a space on the core region side of the second IO cell row in order to avoid a latch-up error. The third IO cell column is arranged such that the high power supply voltage region is located on the side of the edge of the chip. That is, since the low power supply voltage region is located on the core region side of the third IO cell column, it is not necessary to leave a space on the core region side of the third IO cell column in order to avoid a latch-up error. As a result, a latch-up error can be avoided without increasing the area of the semiconductor integrated circuit device.

Effects of the invention

According to the semiconductor integrated circuit device of the present disclosure, a latch-up error can be avoided without increasing the area of the semiconductor integrated circuit.

Drawings

Fig. 1 is a plan view schematically showing the entire configuration of a semiconductor integrated circuit device according to an embodiment.

Fig. 2 shows an example of the configuration of the IO cell.

Fig. 3 shows an example of the layout of the IO cells of the semiconductor integrated circuit device according to the first embodiment.

Fig. 4 shows a comparative example of the IO cell layout of fig. 3.

Fig. 5 shows a modification of the IO cell layout of fig. 3.

Fig. 6 shows an example of the layout of IO cells in the semiconductor integrated circuit device according to the second embodiment.

Fig. 7(a) and 7(b) show comparative examples of the IO cell layout of fig. 6.

Fig. 8 shows an example in which a power supply line is provided in a dead space (Deadspace) on the basis of the IO cell layout of fig. 6.

Fig. 9 shows a modification of the IO cell layout of fig. 6.

Fig. 10 shows another example of the IO cell layout.

Fig. 11 shows another example of the IO cell layout.

Detailed Description

The embodiments are described below with reference to the drawings.

Fig. 1 is a plan view schematically showing the entire configuration of a semiconductor integrated circuit device according to an embodiment. In the semiconductor integrated circuit device shown in fig. 1, a core region 2 and an IO region 3 are provided in a chip 1, an internal core circuit is formed in the core region 2, and an interface circuit (IO circuit) is formed in the IO region 3. The IO area 3 is disposed around the core area 2. In the IO region 3, two IO cell rows 10A, 10B are arranged along the outer side of the chip 1. However, in a part of the IO region 3, only one IO cell column 10C is arranged. It should be noted that the IO cell rows arranged in the IO region 3 may be two rows. Alternatively, two or more IO cell columns may be arranged. Although a plurality of IO cells 10 constituting an interface circuit are arranged in each of the IO cell columns 10A, 10B, and 10C, the illustration is simplified in fig. 1. In the semiconductor integrated circuit device 1, a plurality of external connection pads (pads) are arranged, but illustration is omitted in fig. 1.

Fig. 2 shows an example of the configuration of the IO cell 10. In fig. 2, the internal configuration of the IO cell, the signal line, and the like are not shown. The same is true in the following figures. The IO cell generally has a high power supply voltage region including an output buffer and the like for outputting signals to the outside of the ESD circuit or the semiconductor integrated circuit device, and a low power supply voltage region including a circuit portion and the like for inputting and outputting signals to the inside of the semiconductor integrated circuit device. The IO cell 10 of fig. 2 is divided into a low power supply voltage region 11 and a high power supply voltage region 12 in the Y direction (vertical direction in the drawing). Here, the X direction is a direction extending along the outer side of the chip 1, and corresponds to the first direction in which the IO cells 10 are arranged. The Y direction is a direction from the edge of the chip 1 toward the core region 2, and corresponds to a second direction perpendicular to the X direction when viewed from above.

In the low power supply voltage region 11, a P-type transistor and an N-type transistor are mixed. The P-type transistor is formed in the P-type transistor region, and the N-type transistor is formed in the N-type transistor region. In the high power supply voltage region 12, a P-type transistor region 12a in which a P-type transistor is formed and an N-type transistor region 12b in which an N-type transistor is formed are provided separately in the Y direction. The P-type transistor region 12a is provided with a power supply line 21, and the power supply line 21 extends in the X direction and supplies an IO power supply potential VDDIO to the IO cell 10. A power supply line 22 is provided in the N-type transistor region 12b, the power supply line 22 extends in the X direction, and the ground potential VSS is supplied to the IO cell 10. Note that the power supply line is also provided in the low power supply voltage region 11, but illustration thereof is omitted. In the low power supply voltage region 11 and the high power supply voltage region 12 of the IO cell 10, devices other than transistors, such as diodes, may be formed.

(first embodiment)

Fig. 3 is a diagram showing an example of the layout of the IO cell 10 of the semiconductor integrated circuit device according to the first embodiment, and corresponds to an enlarged view of the X1 portion in fig. 1. In fig. 3, two IO cell rows 10A and 10B each include a plurality of IO cells 10 arranged in an X direction (a lateral direction in the drawing, a direction extending along an outer side of the chip 1), and two IO cell rows 10A and 10B are arranged in a Y direction (a longitudinal direction in the drawing, a direction from an edge of the chip 1 toward the core region 2). The IO cell column 10A corresponding to the first IO cell column is arranged closest to the edge of the chip 1 in two or more IO cell columns (here, the IO cell columns 10A and 10B) arranged in a row in the Y direction. The IO cell column 10B corresponding to the second IO cell column is disposed adjacent to the IO cell column 10A on the core region 2 side of the IO cell column 10A.

In the layout example of fig. 3, in the IO cell column 10A, the IO cells 10 are arranged such that the high power supply voltage region 12 is located closer to the core region 2, and in the IO cell column 10B, the IO cells 10 are arranged such that the low power supply voltage region 11 is located closer to the core region 2. That is, the two columns of IO cells 10A, 10B are arranged such that the high power supply voltage region 12 of the IO cell column 10A and the high power supply voltage region 12 of the IO cell column 10B face each other. In the layout example of fig. 3, the sizes and positions of the IO cells 10 in the IO cell column 10A in the Y direction are made the same, and the sizes and positions of the IO cells 10 in the IO cell column 10B in the Y direction are made the same. In the IO cell column 10A and the IO cell column 10B, the opposing IO cells 10 are equal in size and position in the X direction.

In the layout example of fig. 3, since the N-type transistor regions 12B of the same high power supply voltage region 12 of the IO cell column 10A and the IO cell column 10B face each other, it is not necessary to leave a space (arrow a1 of fig. 3) between the IO cell column 10A and the IO cell column 10B in order to avoid a latch-up error. In the IO cell column 10B, the low power supply voltage region 11 is located closer to the core region 2, and therefore, it is not necessary to provide a space (arrow a2 in fig. 3) between the IO cell column 10B and the core region 2 in order to avoid a latch-up error.

Fig. 4 is a diagram showing an IO cell layout according to a comparative example. In the configuration of fig. 4, in the two IO cell rows 10G and 10H, each IO cell 10 is arranged such that the low power supply voltage region 11 is located closer to the core region 2. In this layout, the low power supply voltage region 11 of the IO cell column 10G and the high power supply voltage region 12 of the IO cell column 10H face each other, and therefore, in order to avoid a latch-up error, a space needs to be left between the IO cell column 10G and the IO cell column 10H. As a result, dead space DS is generated between IO cell column 10G and IO cell column 10H, and the area of the semiconductor integrated circuit device increases.

In contrast, in the layout example of fig. 3, since it is not necessary to leave a space for avoiding a latch-up error, a latch-up error can be avoided without increasing the area of the semiconductor integrated circuit device.

Fig. 5 is a modification of the layout example of fig. 3. In the layout example of fig. 5, an IO cell 15 is arranged instead of the IO cell 10, and in the IO cell 15, the positions of the P-type transistor region and the N-type transistor region in the high power supply voltage region are switched. That is, in the IO cell 15, the low power supply voltage region 16 and the high power supply voltage region 17 are provided separately in the Y direction, and in the high power supply voltage region 17, the P-type transistor region 17a and the N-type transistor region 17b are provided separately in the Y direction.

As in the layout example of fig. 3, in the IO cell column 15A, the IO cells 15 are arranged such that the high power supply voltage region 17 is located closer to the core region 2, and in the IO cell column 15B, the IO cells 15 are arranged such that the low power supply voltage region 16 is located closer to the core region 2. That is, the two columns of IO cell columns 15A, 15B are arranged such that the high power supply voltage region 17 of the IO cell column 15A and the high power supply voltage region 17 of the IO cell column 15B face each other. According to this layout, as in the layout example of fig. 3, there is no need to leave a space between the IO cell column 15A and the IO cell column 15B, and since the IO cell column 15B has the low power supply voltage region 16 located closer to the core region 2, there is no need to leave a space between the IO cell column 15B and the core region 2.

In the configuration of the IO cell 10 shown in fig. 2, a large potential difference exists between the N-well of the P-type transistor region 12a of the high power supply voltage region 12 and the low power supply voltage region 11 in which the P-type/N-type transistors are mixed. Therefore, a large space needs to be left between the P-type transistor region 12a and the low power supply voltage region 11. In contrast, in the configuration of the IO cell 15 shown in fig. 5, it is not necessary to provide a large space between the N-type transistor region 17b and the low power supply voltage region 16, and therefore the area of the IO cell can be further reduced.

In the configuration of the IO cell 10 shown in fig. 2, the P-type/N-type transistors are mixed in the low power supply voltage region 11, but the P-type transistor region and the N-type transistor region may be provided separately in the Y direction in the low power supply voltage region 11. In this case, in fig. 2, it is preferable that, in the low power supply voltage region 11, an N-type transistor region is provided on the upper side in the drawing and a P-type transistor region is provided on the lower side in the drawing. That is, in the case where the transistor regions of the same conductivity type (P-type transistor regions in this case) face each other between the low power supply voltage region 11 and the high power supply voltage region 12, the potential difference between the low power supply voltage region 11 and the high power supply voltage region 12 becomes smaller. In the configuration of the IO cell 15 shown in fig. 5, when the low power supply voltage region 16 is provided separately in the Y direction for the same reason, it is preferable that a P-type transistor region is provided on the upper side in the drawing and an N-type transistor region is provided on the lower side in the drawing.

In the present embodiment, two IO cell rows 10A and 10B are arranged, but the number of IO cell rows is not limited to two. For example, when four IO cell columns are arranged, two IO cell columns 10A and 10B may be arranged in the Y direction. In this case, the same operation and effect as those of the present embodiment can be obtained.

In the layout example of fig. 3, the sizes and positions of the IO cells 10 in the IO cell column 10A in the Y direction are made the same, and the sizes and positions of the IO cells 10 in the IO cell column 10B in the Y direction are made the same, but the configuration of the present embodiment is not limited to this. Further, the opposing IO cells 10 in the IO cell column 10A and the IO cell column 10B are made to have the same size and position in the X direction, but the configuration of the present embodiment is not limited to this.

(second embodiment)

Fig. 6 is a diagram showing an example of the layout of the IO cell 10 of the semiconductor integrated circuit device according to the second embodiment, and corresponds to an enlarged view of the X2 portion in fig. 1. In fig. 6, the first IO cell block 4 and the second IO cell block 5 are adjacent in the X direction. The layout of the IO cells 10 of the first IO cell block 4 is the same as the configuration of fig. 3. That is, the two IO cell rows 10A, 10B include a plurality of IO cells 10 arranged in the X direction, respectively, and the two IO cell rows 10A, 10B are arranged in the Y direction. The IO cell column 10A corresponding to the first IO cell column is arranged closest to the edge of the chip 1 in two or more IO cell columns (here, the IO cell columns 10A and 10B) arranged in a row in the Y direction. The IO cell column 10B corresponding to the second IO cell column is disposed adjacent to the IO cell column 10A on the core region 2 side of the IO cell column 10A.

The second IO cell block 5 includes only one IO cell column 10C, and the IO cell column 10C corresponds to a third IO cell column including a plurality of IO cells 10 arranged in the X direction. In the configuration of fig. 6, the IO cell columns 10A and 10C are arranged in a row in the X direction.

In the layout example of fig. 6, in the first IO cell block 4, the IO cells 10 are arranged such that the high power supply voltage region 12 is located closer to the core region 2 in the IO cell column 10A, and the IO cells 10 are arranged such that the low power supply voltage region 11 is located closer to the core region 2 in the IO cell column 10B. That is, the two columns of IO cells 10A, 10B are arranged such that the high power supply voltage region 12 of the IO cell column 10A and the high power supply voltage region 12 of the IO cell column 10B face each other. In the layout example of fig. 6, the sizes and positions of the IO cells 10 in the IO cell column 10A in the Y direction are the same, and the sizes and positions of the IO cells 10 in the IO cell column 10B in the Y direction are the same. In the IO cell column 10A and the IO cell column 10B, the opposing IO cells 10 are equal in size and position in the X direction. The dimensions and positions of the IO cells 10 in the Y direction of the IO cell columns 10A, 10C are made the same.

In the first IO cell block 4, the N-type transistor regions 12B of the same high power supply voltage region 12 of the IO cell column 10A and the IO cell column 10B face each other, and therefore, it is not necessary to leave a space between the IO cell column 10A and the IO cell column 10B in order to avoid a latch-up error. In the IO cell column 10B, the low power supply voltage region 11 is located closer to the core region 2, and therefore, it is not necessary to provide a space between the IO cell column 10B and the core region 2 in order to avoid a latch-up error. The above-described operation and effect are the same as those of the first embodiment.

In the second IO cell block 5, the IO cell column 10C is arranged such that the high power supply voltage region 12 is located on the side of the edge of the chip 1. That is, in the IO cell column 10A of the first IO cell block 4 and the IO cell column 10C of the second IO cell block 5, the orientation of the IO cells 10 is opposite. Between the first IO cell block 4 and the second IO cell block 5, since the high power supply voltage region is adjacent to the low power supply voltage region or the high power supply voltage region is adjacent to the core region, the dead space DS is generated.

Fig. 7 is a diagram showing an IO cell layout according to a comparative example. In fig. 7, IO cell columns 10I, 10J having different lengths are arranged, and the IO cell layout includes a portion where the IO cells are two columns and a portion where the IO cells are one column. In fig. 7(a), the IO cells 10 are all oriented in the same direction. Therefore, in the portion where the IO cell rows are two rows, a space needs to be provided between the IO cell row 10I and the IO cell row 10J for the same reason as in fig. 4, and therefore a dead space is generated. Note that, in the right side of the IO cell column 10J, a dead space is generated in part because the high power supply voltage region is adjacent to the core region. In fig. 7(b), the orientation of the IO cell 10 is reversed in the entire IO cell column 10I. Therefore, in the portion where the IO cell rows are two rows, the respective high power supply voltage regions 12 face each other, and therefore no dead space is generated between the IO cell row 10I and the IO cell row 10J. However, in the portion where the IO cells are arranged in a row, the high power supply voltage region 12 is located closer to the core region, and therefore, the high power supply voltage region is adjacent to the core region over the entire portion, and therefore, a dead space is generated closer to the core region.

In contrast, in the configuration of fig. 6, no dead space is generated between the IO cell rows 10A and 10B in the first IO cell block 4. In the second IO cell block 5, since the low power supply voltage region 11 of the IO cell row 10C is located closer to the core region, no dead space is generated closer to the core region. That is, in the part where the IO cells of the first IO cell block 4 are arranged in two rows, the blind space does not occur over the entire part as in (a) of fig. 7. In the second IO cell block 5, i.e., the portion in which the IO cells are arranged in a row, the dead space does not occur over the entire area as in fig. 7 (b). Therefore, although the dead space DS is generated between the first IO cell block 4 and the second IO cell block 5, the total amount of the dead space can be significantly reduced when the first and second IO cell blocks 4 and 5 are viewed as a whole. As a result, it is possible to prevent a latch-up error while suppressing the area of the semiconductor integrated circuit device to be small.

Fig. 8 shows an example in which a power supply line is provided in a dead space in addition to the configuration of fig. 6. In the configuration of fig. 8, between the first IO cell block 4 and the second IO cell block 5, power supply lines 23, 24 extending in the Y direction are arranged. The power supply line 23 is a line connecting the power supply line 21 arranged in the first IO cell block 4 and the power supply line 21 arranged in the second IO cell block 5, and is formed in a wiring layer on an upper layer than the power supply line 21. The power supply line 24 is a line connecting the power supply line 22 arranged in the first IO cell block 4 and the power supply line 22 arranged in the second IO cell block 5, and is formed in a wiring layer on an upper layer than the power supply line 22. In the configuration of fig. 8, the dead space between the first IO cell block 4 and the second IO cell block 5 can be effectively used to strengthen the power supply.

In the configuration of fig. 6, the sizes and positions of the IO cells 10 in the IO cell row 10A in the Y direction are the same, and the sizes and positions of the IO cells 10 in the IO cell row 10B in the Y direction are the same, but the configuration of the present embodiment is not limited to this. Further, the opposing IO cells 10 in the IO cell column 10A and the IO cell column 10B are made to have the same size and position in the X direction, but the configuration of the present embodiment is not limited to this. In the configuration of fig. 6, the dimensions and positions of the IO cells 10 in the IO cell rows 10A and 10C in the Y direction are made the same, but the configuration of the present embodiment is not limited to this. In the configuration of fig. 6, the IO cell columns 10A and the IO cell columns 10C are arranged in a row in the X direction, but the configuration of the present embodiment is not limited to this.

(other constitution example)

Fig. 9 shows another example of the layout of the IO cell. The layout example of fig. 9 is basically the same as the layout example of fig. 6. However, the difference from fig. 6 is that: in the first IO cell block 4, a space through which a signal line can pass is provided. That is, in the IO cell rows 10A and 10B, a space S1 through which a signal line can pass is provided between the opposing groups of IO cells 10. On the side of the IO cell row 10A close to the edge of the chip 1, a space S2 through which a signal line can pass is provided. In general, the IO cell 10 is provided with an input/output unit at an end of the low power supply voltage region 11. Therefore, the connection between the input/output unit of each IO cell 10 of the IO cell column 10A and the internal core circuit provided in the core region 2 is facilitated by providing the spaces S1 and S2.

In the first embodiment, a space through which a signal line can pass may be provided as in the layout example of fig. 9.

Fig. 10 shows another configuration example of the IO cell layout. Fig. 10 shows a configuration of a pair of IO cells 10 facing each other for convenience of illustration. In practical cases, two IO cell columns are formed by arranging a group of IO cells 10 shown in fig. 10 in the X direction. In fig. 10, between the IO cells 10 facing each other, a power supply line 25 extending in the X direction is arranged. The power supply is further strengthened by the power supply line 25. Here, the power supply line 25 is used to intensify the supply of the ground potential VSS, for example. However, it may be used to enhance the supply of the power supply potential VDDIO. In the first or second embodiment, the configuration as shown in fig. 10 may be adopted.

Fig. 11 shows still another configuration example of the IO cell layout. Fig. 11 shows a configuration of a pair of IO cells 10 facing each other for convenience of illustration. In practical cases, two IO cell columns are formed by arranging a set of IO cells 10 shown in fig. 11 in the X direction. Fig. 11 shows a pad 30 provided for connection to the outside of the chip 1. The connecting lines between the IO cells 10 and the pads 30 are not illustrated. In fig. 11, upper power supply lines 26, 27 extending in the Y direction are arranged in the same wiring layer as the pad 30. The upper power supply line 26 connects the power supply lines 21 of the IO cells 10 facing each other. The upper power supply line 27 connects the power supply lines 22 of the IO cells 10 facing each other. The power supply is further strengthened by the upper power supply lines 26, 27. In the first or second embodiment, the configuration shown in fig. 11 may be adopted.

Industrial applicability-

According to the present disclosure, a latch-up error can be avoided without increasing the area of the semiconductor integrated circuit device, and therefore, the present disclosure is useful for, for example, downsizing of an LSI and improvement of performance.

-description of symbols-

1 chip

2 core region

3 IO region

4 first IO cell Block

5 second IO cell Block

10 IO cell

10A IO cell column (first IO cell column)

10B IO cell column (second IO cell column)

10C IO cell column (third IO cell column)

11 low power supply voltage region

12 high supply voltage region

Transistor region of type 12a P

Transistor region of type 12b N

15 IO cell

15A, 15B IO cell columns

16 low supply voltage region

17 high supply voltage region

17a P type transistor region

17b N type transistor region

21. 22 power cord

25 power cord

26. 27 upper power supply line

30 bonding pad

Space for signal wire to pass through S1 and S2