阅读说明：本技术 电容器及其制造方法 (Capacitor and method for manufacturing the same ) 是由 樋口和人 小幡进 松尾圭一郎 佐野光雄 于 2019-01-09 设计创作，主要内容包括：提供一种能够实现大的电容量的电容器。实施方式的电容器(1A)包括：基板(10),具有第一面与第二面,设置有一个以上的贯通孔(TH1),该一个以上的贯通孔(TH1)分别从所述第一面延伸至所述第二面；第一导电层(20a),覆盖所述第一面、所述第二面以及所述一个以上的贯通孔(TH1)的侧壁；第二导电层(20b),隔着所述第一导电层(20a)而与所述第一面、所述第二面以及所述一个以上的贯通孔(TH1)的侧壁相对；以及电介质层(50),夹设于所述第一导电层(20a)与所述第二导电层(20b)之间。(Provided is a capacitor capable of realizing a large capacitance. A capacitor (1A) according to an embodiment includes: a substrate (10) having a first surface and a second surface, and provided with one or more through holes (TH1) extending from the first surface to the second surface; a first conductive layer (20a) covering the first surface, the second surface, and side walls of the one or more through holes (TH 1); a second conductive layer (20b) facing the first surface, the second surface, and the side walls of the one or more through holes (TH1) with the first conductive layer (20a) therebetween; and a dielectric layer (50) interposed between the first conductive layer (20a) and the second conductive layer (20 b).)

1. A capacitor is provided with:

the substrate is provided with a first surface and a second surface, and is provided with more than one first through hole which respectively extends from the first surface to the second surface;

a first conductive layer covering the first surface, the second surface, and sidewalls of the one or more first through holes;

a second conductive layer facing the first surface, the second surface, and the side wall of the one or more first through holes with the first conductive layer interposed therebetween; and

a dielectric layer sandwiched between the first conductive layer and the second conductive layer.

2. The capacitor of claim 1, wherein,

the first surface and the second surface are a first main surface and a second main surface perpendicular to a thickness direction of the substrate, respectively, and the one or more through holes are one or more through holes extending in the thickness direction, respectively.

3. The capacitor of claim 2, wherein,

the at least one first groove is provided in the first main surface, the at least one second groove is provided in the second main surface, a longitudinal direction of the at least one first groove and a longitudinal direction of the at least one second groove intersect with each other, and the at least one first groove and the at least one second groove are connected to each other to form the at least one first through hole.

4. The capacitor of claim 3, wherein,

the first conductive layer further covers sidewalls and a bottom surface of the one or more first trenches and sidewalls and a bottom surface of the one or more second trenches, and the second conductive layer is opposed to the sidewalls and the bottom surface of the one or more first trenches and the sidewalls and the bottom surface of the one or more second trenches with the first conductive layer interposed therebetween.

5. The capacitor of claim 3 or 4,

the sum of the depth of each of the one or more first grooves and the depth of each of the one or more second grooves is equal to or greater than the thickness of the substrate.

6. The capacitor of any one of claims 3 to 5,

the one or more first trenches and the one or more second trenches form the one or more first through holes at positions where they intersect.

7. The capacitor of any one of claims 3 to 6,

the one or more first trenches are a plurality of first trenches, one or more second through holes are provided in one or more portions of the substrate, which are sandwiched between two adjacent ones of the plurality of first trenches, respectively, the one or more second through holes connect one of the two adjacent ones of the plurality of first trenches to the other one of the two adjacent ones of the plurality of first trenches, the first conductive layer further covers sidewalls of the one or more second through holes, and the second conductive layer further faces the sidewalls of the one or more second through holes with the first conductive layer interposed therebetween.

8. The capacitor of any one of claims 3 to 7,

the one or more second trenches are a plurality of second trenches, one or more third through holes are provided in one or more portions of the substrate, which are sandwiched between two adjacent ones of the plurality of second trenches, respectively, the one or more third through holes connect one of the two adjacent ones of the plurality of second trenches to the other one of the two adjacent ones of the plurality of second trenches, the first conductive layer further covers sidewalls of the one or more third through holes, and the second conductive layer further faces the sidewalls of the one or more third through holes with the first conductive layer interposed therebetween.

9. The capacitor of claim 1, wherein,

the substrate further includes a first main surface and a second main surface perpendicular to a thickness direction of the substrate, the first main surface is provided with a plurality of grooves, and the first surface and the second surface are two adjacent side walls of the plurality of grooves.

10. The capacitor of claim 9, wherein,

the first conductive layer further covers the first main surface and the bottom surfaces of the plurality of trenches, and the second conductive layer is further opposed to the first main surface and the bottom surfaces of the plurality of trenches with the first conductive layer interposed therebetween.

11. A capacitor is provided with:

a substrate having a first main surface and a second main surface, the first main surface being provided with a plurality of grooves, and at least one through-hole being provided in at least one portion sandwiched between two adjacent grooves among the plurality of grooves, the at least one through-hole connecting one of the two adjacent grooves to the other;

a first conductive layer covering the first main surface, the side walls and the bottom surface of the trench, and the side walls of the one or more through holes;

a second conductive layer facing the first main surface, the side walls and the bottom surface of the trench, and the side walls of the one or more through holes with the first conductive layer interposed therebetween; and

a dielectric layer sandwiched between the first conductive layer and the second conductive layer.

12. The capacitor according to any one of claims 2 to 11, further comprising:

an insulating layer facing the first main surface with a part of the first conductive layer, a part of the second conductive layer, and a part of the dielectric layer interposed therebetween;

the first electrode is arranged on the insulating layer and is electrically connected with the first conducting layer; and

and the second electrode is arranged on the insulating layer and is electrically connected with the second conducting layer.

13. The capacitor of any one of claims 1 to 12,

the first conductive layer and the second conductive layer are made of metal.

14. The capacitor of any one of claims 1 to 13,

the substrate contains silicon.

15. A method for manufacturing a capacitor, comprising the steps of:

forming a first catalyst layer containing a first noble metal on a substrate so as to partially cover a surface of the substrate;

etching the substrate under the action of the first noble metal as a catalyst to form more than one first through hole in the substrate;

forming a first conductive layer on the substrate on which the one or more first through holes are formed;

forming a dielectric layer on the first conductive layer; and

a second conductive layer is formed on the dielectric layer.

16. The method of claim 15, wherein,

one or more through holes extending in the thickness direction of the substrate are formed as the one or more first through holes.

17. The method of claim 16, wherein,

the substrate has a first main surface and a second main surface,

the one or more first through holes are formed by forming one or more first grooves in the first main surface and forming one or more second grooves in the second main surface so that the longitudinal direction of the one or more second grooves intersects the longitudinal direction of the one or more first grooves.

18. The method of claim 17, further comprising the steps of:

forming a plurality of first trenches as the one or more first trenches and a plurality of second trenches as the one or more second trenches,

forming a second catalyst layer containing a second noble metal on the substrate after the one or more first through holes are formed and before the first conductive layer is formed, so as to partially cover sidewalls of the plurality of first trenches and sidewalls of the plurality of second trenches; and

the substrate is etched under the action of the second noble metal as a catalyst, one or more second through holes connecting one of the two adjacent first trenches to the other are formed in one or more portions of the substrate sandwiched by the two adjacent first trenches, respectively, and one or more third through holes connecting one of the two adjacent second trenches to the other are formed in one or more portions of the substrate sandwiched by the two adjacent second trenches, respectively, of the plurality of second trenches.

19. The method of claim 15, wherein,

further comprising a step of forming a plurality of grooves in the substrate before forming the first catalyst layer,

one or more through holes connecting one of the two adjacent trenches to the other are formed as the one or more first through holes in one or more portions of the substrate sandwiched between the two adjacent trenches.

20. The method of any one of claims 15 to 19,

each of the first conductive layer and the second conductive layer is formed by a plating method using a plating solution containing a salt of a metal to be plated, a surfactant, and carbon dioxide in a supercritical or subcritical state.

21. A capacitor is provided with:

a substrate having a first main surface and a second main surface, wherein the first main surface is provided with one or more first grooves, and sidewalls of the one or more first grooves are provided with a plurality of first holes each extending in a first direction inclined with respect to the sidewalls of the first groove;

a first conductive layer covering the first main surface, the side walls and the bottom surface of the first trench, and the side walls of the plurality of first holes;

a second conductive layer facing the first main surface, the side walls and the bottom surface of the first trench, and the side walls of the one or more first holes with the first conductive layer interposed therebetween; and

a dielectric layer sandwiched between the first conductive layer and the second conductive layer.

22. The capacitor of claim 21, wherein,

the one or more first grooves are two or more grooves, and at least one of the plurality of first holes is a through hole connecting one of two adjacent grooves of the two or more first grooves to the other.

23. The capacitor of claim 21 or 22,

the sidewall of the first trench is further provided with a plurality of second holes each extending in a second direction intersecting the first direction, the first conductive layer further covers the sidewalls of the plurality of second holes, and the second conductive layer is opposed to the sidewalls of the plurality of second holes with the first conductive layer interposed therebetween.

24. The capacitor of claim 23, wherein,

the first direction is orthogonal to the second direction.

25. The capacitor of any one of claims 21 to 24,

the portion of the substrate adjacent to the one or more first trenches is composed of crystals having a face-centered cubic structure.

26. The capacitor of claim 25, wherein,

the first direction is parallel to the < 110 > axis.

27. The capacitor of any one of claims 21 to 26,

one or more second grooves are provided in the second main surface, a longitudinal direction of the one or more first grooves and a longitudinal direction of the one or more second grooves intersect with each other, the one or more first grooves and the one or more second grooves are connected to each other to form one or more first through holes,

a plurality of third holes extending in a third direction inclined with respect to the side wall of the second trench are provided in the side wall of the second trench, the first conductive layer further covers the side walls of the plurality of third holes, and the second conductive layer is further opposed to the side walls of the plurality of third holes with the first conductive layer interposed therebetween.

28. The capacitor of claim 27, wherein,

the portion of the substrate adjacent to the one or more second trenches is composed of crystals having a face-centered cubic structure.

29. The capacitor of claim 28, wherein,

the third direction is parallel to the < 110 > axis.

30. The capacitor of any one of claims 27 to 29,

the first direction is parallel or orthogonal to the third direction.

31. The capacitor of any one of claims 27 to 30,

the sidewall of the second trench is further provided with a plurality of fourth holes each extending in a fourth direction intersecting the third direction, the first conductive layer further covers the sidewalls of the plurality of fourth holes, and the second conductive layer is further opposed to the sidewalls of the plurality of fourth holes with the first conductive layer interposed therebetween.

32. The capacitor of claim 31, wherein,

the third direction is orthogonal to the fourth direction.

33. A method for manufacturing a capacitor, comprising the steps of:

forming one or more first grooves in a first main surface of a substrate having the first main surface and a second main surface;

forming a first catalyst layer containing a first noble metal on a sidewall of the one or more first trenches so as to partially cover the sidewall of the one or more first trenches;

etching the side wall of the first trench under the action of the first noble metal as a catalyst, and forming a plurality of first holes in the side wall of the first trench, the first holes extending in a first direction inclined with respect to the side wall of the first trench;

forming a first conductive layer on the substrate on which the plurality of first holes are formed;

forming a dielectric layer on the first conductive layer; and

a second conductive layer is formed on the dielectric layer.

34. The method of claim 33, wherein,

the portion of the substrate adjacent to the one or more first trenches is composed of crystals having a face-centered cubic structure.

35. The method of claim 33 or 34,

the first direction is parallel to the < 110 > axis.

36. The method of any one of claims 33 to 35,

each of the first conductive layer and the second conductive layer is formed by a plating method using a plating solution containing a salt of a metal to be plated, a surfactant, and carbon dioxide in a supercritical or subcritical state.

Technical Field

Embodiments of the invention relate to a capacitor and a method of manufacturing the same.

Background

Most electrical and electronic devices include capacitors. Such a capacitor is obtained by forming a conductive layer and a dielectric layer on a silicon substrate, for example (see japanese patent laid-open No. 8-213565).

Disclosure of Invention

The present invention addresses the problem of providing a capacitor capable of achieving a large capacitance.

According to a first aspect, there is provided a capacitor including: a substrate having a first surface and a second surface, and provided with one or more first through holes extending from the first surface to the second surface, respectively; a first conductive layer covering the first surface, the second surface, and sidewalls of the one or more first through holes; a second conductive layer facing the first surface, the second surface, and the side wall of the one or more first through holes with the first conductive layer interposed therebetween; and a dielectric layer sandwiched between the first conductive layer and the second conductive layer.

According to a second aspect, there is provided a capacitor including: a substrate having a first main surface and a second main surface, the first main surface being provided with a plurality of grooves, and at least one through-hole being provided in at least one portion sandwiched between two adjacent grooves of the plurality of grooves, the at least one through-hole connecting one of the two adjacent grooves to the other; a first conductive layer covering the first main surface, the side walls and the bottom surface of the trench, and the side walls of the one or more through holes; a second conductive layer facing the first main surface, the side walls and the bottom surface of the trench, and the side walls of the one or more through holes with the first conductive layer interposed therebetween; and a dielectric layer sandwiched between the first conductive layer and the second conductive layer.

According to a third aspect, there is provided a method of manufacturing a capacitor, comprising the steps of: forming a first catalyst layer containing a first noble metal on a substrate so as to partially cover a surface of the substrate; etching the substrate under the action of the first noble metal as a catalyst to form more than one first through hole in the substrate; forming a first conductive layer on the substrate on which the one or more first through holes are formed; forming a dielectric layer on the first conductive layer; and forming a second conductive layer on the dielectric layer.

According to a fourth aspect, there is provided a capacitor including: a substrate having a first main surface and a second main surface, wherein the first main surface is provided with one or more first grooves, and a plurality of first holes extending in a first direction inclined with respect to the side walls of the first grooves are provided in the side walls of the one or more first grooves; a first conductive layer covering the first main surface, the side walls and the bottom surface of the first trench, and the side walls of the plurality of first holes; a second conductive layer facing the first main surface, the side walls and the bottom surface of the first trench, and the side walls of the one or more first holes with the first conductive layer interposed therebetween; and a dielectric layer sandwiched between the first conductive layer and the second conductive layer.

According to a fifth aspect, there is provided a method of manufacturing a capacitor, comprising the steps of: forming one or more first grooves in a first main surface of a substrate having the first main surface and a second main surface; forming a first catalyst layer containing a first noble metal on a sidewall of the one or more first trenches so as to partially cover the sidewall of the one or more first trenches; etching the sidewall of the first trench under the action of the first noble metal as a catalyst to form a plurality of first holes in the sidewall of the first trench, the plurality of first holes extending in a first direction inclined with respect to the sidewall of the first trench, respectively; forming a first conductive layer on the substrate on which the plurality of first holes are formed; forming a dielectric layer on the first conductive layer; and forming a second conductive layer on the dielectric layer.

Drawings

Fig. 1 is a plan view schematically showing a capacitor according to a first embodiment.

Fig. 2 is a cross-sectional view of the capacitor shown in fig. 1.

Fig. 3 is another cross-sectional view of the capacitor shown in fig. 1.

Fig. 4 is yet another cross-sectional view of the capacitor shown in fig. 1.

Fig. 5 is yet another cross-sectional view of the capacitor shown in fig. 1.

Fig. 6 is yet another cross-sectional view of the capacitor shown in fig. 1.

Fig. 7 is a sectional view schematically showing a step in manufacturing the capacitor shown in fig. 1 to 6.

Fig. 8 is a sectional view schematically showing another step in manufacturing the capacitor shown in fig. 1 to 6.

Fig. 9 is a sectional view schematically showing still another step in manufacturing the capacitor shown in fig. 1 to 6.

Fig. 10 is another sectional view schematically showing the step of fig. 9.

Fig. 11 is a cross-sectional view schematically showing an example of the structure obtained by the steps of fig. 9 and 10.

Fig. 12 is another cross-sectional view of the construction shown in fig. 11.

Fig. 13 is a sectional view schematically showing a capacitor according to a second embodiment.

Fig. 14 is a sectional view schematically showing a capacitor according to a third embodiment.

Fig. 15 is a perspective view schematically showing a part of the capacitor shown in fig. 14.

Fig. 16 is a perspective view schematically showing an example of a substrate provided with a groove used for manufacturing the capacitor shown in fig. 14.

Fig. 17 is a perspective view schematically showing a step in manufacturing the capacitor shown in fig. 14.

Fig. 18 is a perspective view schematically showing an example of a structure obtained by another step in manufacturing the capacitor shown in fig. 14.

Fig. 19 is a perspective view schematically showing a part of a capacitor according to a fourth embodiment.

Fig. 20 is a sectional view schematically showing a capacitor according to a fifth embodiment.

Fig. 21 is a perspective view schematically showing a part of the capacitor shown in fig. 20.

Fig. 22 is a cross-sectional view taken along line XXII-XXII of the capacitor shown in fig. 21.

Fig. 23 is a photomicrograph showing a cross section of the capacitor shown in fig. 21.

Fig. 24 is a perspective view schematically showing a part of a capacitor according to a sixth embodiment.

Detailed Description

Hereinafter, embodiments will be described in detail with reference to the drawings. Note that the same reference numerals are given to the components that perform the same or similar functions throughout the drawings, and redundant description is omitted.

< first embodiment >

Fig. 1 is a plan view schematically showing a capacitor according to a first embodiment. Fig. 2 is a cross-sectional view along line II-II of the capacitor shown in fig. 1. Fig. 3 is a cross-sectional view along the line III-III of the capacitor shown in fig. 1. Fig. 4 is a cross-sectional view along line IV-IV of the capacitor shown in fig. 1. Fig. 5 is a cross-sectional view taken along line V-V of the capacitor shown in fig. 1. Fig. 6 is a cross-sectional view taken along line VI-VI of the capacitor shown in fig. 1.

As shown in fig. 2 to 6, the capacitor 1A shown in fig. 1 to 6 includes a substrate 10, a first conductive layer 20a, a second conductive layer 20b, and a dielectric layer 50.

In each drawing, the X direction is a direction parallel to the main surface of the substrate 10, and the Y direction is a direction parallel to the main surface of the substrate 10 and perpendicular to the X direction. The Z direction is a thickness direction of the substrate 10, that is, a direction perpendicular to the X direction and the Y direction.

The substrate 10 is, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. The substrate 10 is preferably a semiconductor substrate. The substrate 10 is preferably a silicon-containing substrate such as a silicon substrate. Such a substrate can be processed by a semiconductor process.

As shown in fig. 2 to 6, the substrate 10 has a first main surface S1 and a second main surface S2 as a rear surface thereof. Here, the first main surface S1 and the second main surface S2 are a first surface and a second surface, respectively.

The first main surface S1 is provided with a first recessed portion R1 shown in fig. 1, 2, and 4 to 6. Here, the first recesses R1 are first grooves each having a shape extending in the X direction. As shown in fig. 1, 2, and 4, the first concave portions R1 are aligned in the Y direction. On the first main surface S1, a plurality of first recesses R1 may be provided, or only one first recess R1 may be provided.

The second main surface S2 is provided with a second recessed portion R2 shown in fig. 1, 3, and 4 to 6. Here, the second recesses R2 are second grooves each having a shape extending in the Y direction. As shown in fig. 1, 3, and 5, the second recesses R2 are aligned in the X direction. On the second main surface S2, a plurality of second recesses R2 may be provided, or only one second recess R2 may be provided.

The longitudinal direction of the first recessed portion R1 and the longitudinal direction of the second recessed portion R2 intersect with each other. Here, the longitudinal direction of the first concave portion R1 is orthogonal to the longitudinal direction of the second concave portion R2. The longitudinal direction of the first recessed portion R1 and the longitudinal direction of the second recessed portion R2 may obliquely intersect.

The "longitudinal direction" of the first or second concave portion is a longitudinal direction in which the first or second concave portion is orthographically projected onto a plane perpendicular to the thickness direction of the substrate 10. Therefore, the longitudinal direction of the first concave portion R1 intersecting the longitudinal direction of the second concave portion R2 means that the longitudinal direction of the first concave portion orthographically projecting onto a plane perpendicular to the thickness direction of the substrate 10 intersects the longitudinal direction of the second concave portion orthographically projecting onto the plane.

The sum D1+ D2 of the depth D1 of the first recessed portion R1 and the depth D2 of the second recessed portion R2 is equal to or greater than the thickness T of the substrate 10. With this configuration, the first recessed portion R1 and the second recessed portion R2 are connected to each other at a position where they intersect each other, and the first through hole TH1 shown in fig. 6 is formed.

The ratio of the sum of D1+ D2 to the thickness T (D1+ D2)/T is preferably in the range of 1 to 1.4, more preferably in the range of 1.1 to 1.3. From the viewpoint of increasing the capacitance, it is preferable that the ratio of (D1+ D2)/T is large. In addition, it is preferable that the ratio of (D1+ D2)/T is large in order to make the electrical connection between the portions of the first conductive layer 20a and the second conductive layer 20b located on the side walls and the bottom surface of the first recess R1 and the portions located on the side walls and the bottom surface of the second recess R2 more favorable. However, if the depths D1 and D2 are increased, the mechanical strength of the capacitor 1A is reduced.

The ratio of (D1+ D2)/T may be less than 1. In this case, the first through hole TH1 shown in fig. 6 is not formed at the position where the first recess R1 and the second recess R2 intersect. Therefore, in this case, in addition to the first concave portion R1 and the second concave portion R2, a first through hole is provided at a certain position of the substrate 10. In this case, one or both of the first recessed portion R1 and the second recessed portion R2 can be omitted.

The size of the openings of the first recessed portion R1 and the second recessed portion R2 is preferably 0.3 μm or more. The size of the openings of the first concave portion R1 and the second concave portion R2 is the diameter or width of the openings of the first concave portion R1 and the second concave portion R2. Here, the size of the opening of the first concave portion R1 and the second concave portion R2 is a size in a direction perpendicular to the longitudinal direction thereof. If these dimensions are reduced, a larger capacitance can be realized. However, if these dimensions are reduced, it becomes difficult to form a laminated structure including the first conductive layer 20a, the dielectric layer 50, and the second conductive layer 20b in the first recess R1 and the second recess R2.

The distance between the adjacent first recesses R1 and the distance between the adjacent second recesses R2 are preferably 0.1 μm or more. If these distances are reduced, a larger capacitance can be realized. However, if these distances are reduced, the substrate 10 is likely to be damaged at the portion sandwiched between the first concave portions R1 and at the portion sandwiched between the second concave portions R2.

The first recess R1 and the second recess R2 may have various shapes. For example, the first concave portion R1 and the second concave portion R2 may have a curved or bent shape, or may be circular or square, as long as their orthographic projections on a plane perpendicular to the Z direction intersect with each other.

Here, the cross section parallel to the depth direction of the first recess R1 and the second recess R2 is rectangular. These cross sections may not be rectangular. For example, the cross-sections may also have a shape that tapers at the front end.

The first through holes TH1 are aligned to correspond to intersections of the first recesses R1 and the second recesses R2. The first through hole TH1 is formed by a part of the first recess R1 and a part of the second recess R2, respectively. The first through holes TH1 extend from the first main face S1 to the second main face S2, respectively. That is, the first through holes TH1 each extend in the Z direction, which is the thickness direction of the substrate 10.

As shown in fig. 2 to 6, the first conductive layer 20a is disposed on the substrate 10. The first conductive layer 20a constitutes a conductive substrate CS together with the substrate 10.

The first conductive layer 20a is made of polycrystalline silicon doped with impurities, or a metal or an alloy of nickel, copper, or the like, in order to improve conductivity. The first conductive layer 20a may have a single-layer structure or a multi-layer structure.

The thickness of the first conductive layer 20a is preferably in the range of 0.05 μm to 1 μm, more preferably in the range of 0.1 μm to 0.3 μm. If the first conductive layer 20a is thin, a discontinuity may occur in the first conductive layer 20a, or the sheet resistance of the first conductive layer 20a may excessively increase. If the first conductive layer 20a is thickened, it may be difficult to form a laminated structure of the first conductive layer 20a, the dielectric layer 50, and the second conductive layer 20b in the first recessed portion R1 and the second recessed portion R2.

The first conductive layer 20a includes the first portion P1 shown in fig. 2 to 4 and 6, the second portion P2 shown in fig. 2, 3, 5 and 6, the third portion P3 shown in fig. 2 and 4 to 6, and the fourth portion P4 shown in fig. 3 to 6. The first portion P1 is a portion of the first conductive layer 20a disposed on the first main face S1. The second portion P2 is a portion of the first conductive layer 20a disposed on the second main face S2. The third portion P3 is a portion of the first conductive layer 20a disposed on the inner surface of the first recess R1. The fourth portion P4 is a portion of the first conductive layer 20a disposed on the inner surface of the second recess R2.

That is, the first conductive layer 20a covers the first main surface S1, the second main surface S2, and the side wall of the first through hole TH 1. The first conductive layer 20a covers the side walls and the bottom surface of the first recess R1 and the side walls and the bottom surface of the second recess R2.

As can be seen from fig. 2, 4 and 6, the first portion P1 and the third portion P3 are electrically connected to each other. As is apparent from fig. 3, 5, and 6, the second portion P2 and the fourth portion P4 are also electrically connected to each other. Also, the third portion P3 and the fourth portion P4 are electrically connected to each other at the position of the first through hole TH1 shown in fig. 6.

In the case where the substrate 10 is a semiconductor substrate such as a silicon substrate, the first conductive layer 20a may be a high-concentration doped layer in which impurities are doped at a high concentration in a surface region of the silicon substrate. When the silicon substrate itself has high conductivity, the first conductive layer 20a can be omitted. In this case, at least the surface region of the substrate 10, for example, the entire substrate 10 functions as the first conductive layer 20 a.

The second conductive layer 20b is opposed to the first conductive layer 20a with the dielectric layer 50 sandwiched therebetween. The second conductive layer 20b is made of polycrystalline silicon doped with impurities, or a metal or an alloy of nickel, copper, or the like, in order to improve conductivity. The second conductive layer 20b may have a single-layer structure or a multi-layer structure.

The thickness of the second conductive layer 20b is preferably in the range of 0.05 μm to 1 μm, more preferably in the range of 0.1 μm to 0.3 μm. When the second conductive layer 20b is thin, a discontinuous portion may be formed in the second conductive layer 20b, or the sheet resistance of the second conductive layer 20b may excessively increase. If the second conductive layer 20b is thick, it may be difficult to form the first conductive layer 20a and the dielectric layer 50 to have a sufficient thickness.

The second conductive layer 20b includes a fifth portion P5 shown in fig. 2 to 4 and 6, a sixth portion P6 shown in fig. 2, 3, 5 and 6, a seventh portion P7 shown in fig. 2 and 4 to 6, and an eighth portion P8 shown in fig. 3 to 6. The fifth portion P5 is a portion of the second conductive layer 20b that opposes the first main face S1 sandwiching the first portion P1. The sixth portion P6 is a portion of the second conductive layer 20b that opposes the second main face S2 with the second portion P2 sandwiched therebetween. The seventh portion P7 is a portion of the second conductive layer 20b that opposes the inner surface of the first recess R1 with the third portion P3 sandwiched therebetween. The eighth portion P8 is a portion of the second conductive layer 20b that sandwiches the fourth portion P4 against the inner surface of the second recess R2.

That is, the second conductive layer 20b is opposed to the first main surface S1, the second main surface S2, and the side wall of the first through hole TH1 with the first conductive layer 20a interposed therebetween. The second conductive layer 20b is opposed to the side wall and the bottom surface of the first recess R1 and the side wall and the bottom surface of the second recess R2 with the first conductive layer 20a interposed therebetween.

As can be seen from fig. 2, 4 and 6, the fifth portion P5 and the seventh portion P7 are electrically connected to each other. As is apparent from fig. 3, 5, and 6, the sixth portion P6 and the eighth portion P8 are also electrically connected to each other. Further, the seventh portion P7 and the eighth portion P8 are electrically connected to each other at the position of the first through hole TH1 shown in fig. 6.

In fig. 2 to 6, the second conductive layer 20b is provided so that the first recess R1 and the second recess R2 are completely filled with the first conductive layer 20a, the second conductive layer 20b, and the dielectric layer 50. The second conductive layer 20b may be a conformal (conformal) layer with respect to the first conductive layer 20 a. That is, the second conductive layer 20b may be a layer having a substantially uniform thickness. In this case, the first and second recesses R1 and R2 are not completely filled with the first and second conductive layers 20a and 20b and the dielectric layer 50.

The second conductive layer 20b is provided with a plurality of through holes. Here, the through holes are provided in the second conductive layer 20b at positions corresponding to the portions of the first conductive layer 20a and the dielectric layer 50 which face the first main surface with the first conductive layer therebetween and the intersections of the first recesses R1 and the second recesses R2. The second conductive layer 20b may be provided with a through hole at another position. In addition, only one through hole may be provided in the second conductive layer 20 b.

The dielectric layer 50 is sandwiched between the first conductive layer 20a and the second conductive layer 20 b. The dielectric layer 50 is a layer conformal to the first conductive layer 20 a. The dielectric layer 50 electrically insulates the first conductive layer 20a and the second conductive layer 20b from each other.

The dielectric layer 50 is made of, for example, an inorganic dielectric. As the inorganic dielectric, a ferroelectric can be used, but for example, a paraelectric (japanese patent No. ) such as silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, and tantalum oxide is preferable. These paraelectric bodies have a small change in dielectric constant due to temperature. Therefore, when a paraelectric material is used for the dielectric layer 50, the heat resistance of the capacitor 1A can be improved.

The thickness of the dielectric layer 50 is preferably in the range of 0.005 μm to 0.5 μm, more preferably in the range of 0.01 μm to 0.1 μm. If the dielectric layer 50 is thin, a discontinuity may occur in the dielectric layer 50, and the first conductive layer 20a and the second conductive layer 20b may be short-circuited. Further, when the dielectric layer 50 is made thin, the withstand voltage is low even if short-circuiting does not occur, and the possibility of short-circuiting when voltage is applied is increased. When the dielectric layer 50 is made thicker, the withstand voltage becomes higher but the capacitance becomes smaller.

The dielectric layer 50 is provided with a plurality of through holes. The through-hole of the dielectric layer 50 is connected to the through-hole of the second conductive layer 20 b.

The capacitor 1A further includes the insulating layer 60 shown in fig. 1 to 6, the electrodes 70a and 70b shown in fig. 1, 2, 4, and 6, and the pads 70c and 70d shown in fig. 1.

The insulating layer 60 is opposed to the first main surface S1 with a part of the first conductive layer 20a, a part of the second conductive layer 20b, and a part of the dielectric layer 50 interposed therebetween. Specifically, the insulating layer 60 covers the fifth portion P5 and the seventh portion P7 of the second conductive layer 20 b.

The insulating layer 60 includes a first insulating layer 61 and a second insulating layer 62.

The first insulating layer 61 covers the fifth portion P5 and the seventh portion P7 of the second conductive layer 20 b. The first insulating layer 61 also covers the sidewalls of the through-hole provided in the second conductive layer 20b and the sidewalls of the through-hole provided in the dielectric layer 50. The first insulating layer 61 is made of an inorganic insulator such as silicon nitride.

The second insulating layer 62 covers the first insulating layer 61. The second insulating layer 62 is made of an organic insulator such as polyimide, for example.

The insulating layer 60 may have a multilayer structure or a single-layer structure.

The insulating layer 60 is provided with a plurality of through holes. A part of these through holes is connected to the through hole provided in the dielectric layer 50 through the through hole provided in the second conductive layer 20b, and forms a first contact hole together with them. The remaining part of the through hole provided in the insulating layer 60 is provided at the middle position of the first contact holes adjacent in the Y direction, and the second contact hole is formed.

The electrode 70a is disposed on the insulating layer 60. The electrode 70a is a comb-shaped electrode. The electrodes 70a have comb teeth extending in the X direction and arranged in the Y direction. The comb-teeth of the electrode 70b and the comb-teeth of the electrode 70a are alternately arranged in the Y direction. The electrode 70a is here a second electrode. The electrode 70a fills the second contact hole. The electrode 70a is electrically connected to the second conductive layer 20 b. Here, the electrode 70a is a comb-shaped electrode, but the electrode 70a may have another shape.

The electrode 70b is disposed on the insulating layer 60. The electrode 70b is a comb-shaped electrode. The electrodes 70b have comb teeth extending in the X direction and arranged in the Y direction. The electrode 70b is here a first electrode. The electrode 70b fills the first contact hole. The electrode 70b is electrically connected to the first conductive layer 20 a. Here, the electrode 70b is a comb-shaped electrode, and the electrode 70b may have another shape.

The pad 70c is disposed on the insulating layer 60. The pad 70c is electrically connected to the electrode 70 a.

The pad 70d is disposed on the insulating layer 60. The pad 70d is electrically connected to the electrode 70 b.

The electrodes 70a and 70b and the pads 70c and 70d have a laminated structure including a barrier layer, a first metal layer 71, and a second metal layer 72, which are not shown. The barrier layer is made of, for example, titanium. The first metal layer 71 is disposed on the barrier layer. First metal layer 71 is made of copper, for example. The second metal layer 72 covers the upper surface and the end surface of the first metal layer 71. The second metal layer 72 is formed of, for example, a laminated film of a nickel or nickel alloy layer and a gold layer. The barrier layer and the second metal layer 72 can be omitted.

The capacitor 1A is manufactured by, for example, the following method.

Fig. 7 is a sectional view schematically showing a first catalyst layer forming step in manufacturing the capacitor shown in fig. 1 to 6. Fig. 8 is a sectional view schematically showing a second catalyst layer forming step in manufacturing the capacitor shown in fig. 1 to 6. Fig. 9 is a sectional view schematically showing an etching step in manufacturing the capacitor shown in fig. 1 to 6. Fig. 10 is another sectional view schematically showing an etching step in manufacturing the capacitor shown in fig. 1 to 6. Fig. 11 is a cross-sectional view schematically showing an example of the structure obtained by the etching step shown in fig. 9 and 10. Fig. 12 is another cross-sectional view of the construction shown in fig. 11.

In this method, first, the substrate 10 shown in fig. 7 is prepared. Here, the substrate 10 is a silicon single crystal wafer, for example. The surface orientation of the single crystal silicon wafer is not particularly limited, and in this example, a silicon wafer having a (100) plane as the first main surface S1 is used. As the substrate 10, a silicon wafer having a (110) plane as the first main surface S1 can be used.

Next, a first through hole TH1 is formed in the substrate 10 by MacEtch (Metal-Assisted Chemical Etching: Metal-Assisted Chemical Etching).

That is, first, as shown in fig. 7 and 8, first catalyst layers 80a and 80b containing a first noble metal are formed on a substrate 10. The first catalyst layers 80a and 80b are formed so as to partially cover the first main surface S1 and the second main surface S2, respectively.

Specifically, first, the first mask layer 90a is formed on the first main surface S1 of the substrate 10.

The first mask layer 90a has an opening at a position corresponding to the first recess R1. The first mask layer 90a prevents the portion of the first main surface S1 covered with the first mask layer 90a from coming into contact with a noble metal, which will be described later.

Examples of the material of the first mask layer 90a include organic materials such as polyimide, fluororesin, phenol resin, acrylic resin, and phenol resin, and inorganic materials such as silicon oxide and silicon nitride.

The first mask layer 90a can be formed by an existing semiconductor process, for example. The first mask layer 90a made of an organic material can be formed by photolithography, for example. The first mask layer 90a made of an inorganic material can be formed by, for example, film formation of an inorganic material layer by a vapor deposition method, mask formation by photolithography, and patterning of an inorganic material layer by etching. Alternatively, the first mask layer 90a composed of an inorganic material can be formed by oxidation or nitridation of the surface region of the substrate 10, mask formation based on photolithography, and patterning of an oxide or nitride layer based on etching. The first mask layer 90a can be omitted.

Next, the catalyst layer 80a is formed on the region of the first main surface S1 not covered with the first mask layer 90 a. The catalyst layer 80a is, for example, a discontinuous layer containing a noble metal. Here, as an example, the catalyst layer 80a is a granular layer made of catalyst particles 81a containing a noble metal.

Examples of the noble metal include one or more of gold, silver, platinum, rhodium, palladium, and ruthenium. The catalyst layer 80a and the catalyst particles 81a may further contain a metal other than a noble metal such as titanium.

The catalyst layer 80a can be formed by electrolytic plating, reduction plating, or displacement plating, for example. The catalyst layer 80a may be formed by a vapor deposition method such as coating, vapor deposition, or sputtering of a dispersion containing noble metal particles. Among these methods, the displacement plating is particularly preferable because the noble metal can be directly and uniformly deposited on the region of the first main surface S1 not covered with the first mask layer 90 a.

Next, as shown in fig. 8, a second mask layer 90b is formed on the second main surface S2 of the substrate 10.

The second mask layer 90b has an opening at a position corresponding to the second recess R2. The second mask layer 90b prevents the portion of the second main face S2 covered by the second mask layer 90b from coming into contact with the noble metal.

As a material of the second mask layer 90b, for example, a material exemplified for the first mask layer 90a can be used. The second mask layer 90b can be formed, for example, by the same method as that already described with respect to the first mask layer 90 a.

Next, the catalyst layer 80b is formed on the region of the second main surface S2 not covered by the second mask layer 90 b. The catalyst layer 80b is, for example, a discontinuous layer containing a noble metal. Here, as an example, the catalyst layer 80b is a granular layer made of catalyst particles 81b containing a noble metal.

As the material of the catalyst layer 80b and the catalyst particles 81b, for example, the materials exemplified for the catalyst layer 80a and the catalyst particles 81a can be used. The catalyst layer 80b can be formed, for example, by the same method as that already described with respect to the catalyst layer 80 a.

Further, after the first mask layer 90a is formed on the first main surface S1, the second mask layer 90b is formed on the second main surface S2, the catalyst layer 80a and the catalyst particles 81a are formed, and then the catalyst layer 80b and the catalyst particles 81b are formed. Alternatively, the catalyst layer 80a and the catalyst particles 81a, and the catalyst layer 80b and the catalyst particles 81b may be formed simultaneously by forming the first mask layer 90a on the first main surface S1, then forming the second mask layer 90b on the second main surface S2, and then immersing the substrate in the plating liquid.

Next, the substrate 10 is etched by the action of the noble metal as a catalyst, and the first through holes TH1 shown in fig. 6 are formed in the substrate 10.

Specifically, as shown in fig. 9 and 10, the substrate 10 is etched with an etchant 100. For example, the substrate 10 is immersed in a liquid etchant 100, and the etchant 100 is brought into contact with the substrate 10.

The etchant 100 contains an oxidizing agent and hydrogen fluoride.

The concentration of hydrogen fluoride in the etchant 100 is preferably in the range of 1mol/L to 20mol/L, more preferably in the range of 5mol/L to 10mol/L, and further preferably in the range of 3mol/L to 7 mol/L. In the case where the hydrogen fluoride concentration is low, it is difficult to achieve a high etching rate. When the hydrogen fluoride concentration is high, excessive side etching may occur.

The oxidizing agent can be selected from hydrogen peroxide, nitric acid, AgNO₃、KAuCl₄、HAuCl₄、K₂PtCl₆、H₂PtCl₆、Fe(NO₃)₃、Ni(NO₃)₂、Mg(NO₃)₂、Na₂S₂O₈、K₂S₂O₈、KMnO₄And K₂Cr₂O₇To select. Hydrogen peroxide is preferred as the oxidizing agent because it does not produce harmful by-products and contamination of semiconductor elements.

The concentration of the oxidizing agent in the etchant 100 is preferably in the range of 0.2mol/L to 8mol/L, more preferably in the range of 2mol/L to 4mol/L, and further preferably in the range of 3mol/L to 4 mol/L.

The etchant 100 may also contain a buffer. The buffer contains, for example, at least one of ammonium fluoride and ammonia. According to one example, the buffer is ammonium fluoride. According to other examples, the buffer is a mixture of ammonium fluoride and ammonia.

The etchant 100 may further contain other components such as water.

When such an etchant 100 is used, silicon is oxidized as a material of the substrate 10 only in a region close to the first catalyst particles 81a or the second catalyst particles 82b in the substrate 10. Then, the oxide thus produced is dissolved and removed by hydrofluoric acid. Therefore, only a portion close to the first catalyst particle 81a or the second catalyst particle 82b is selectively etched.

The first catalyst particles 81a move to the second main surface S2 as etching progresses, and thus etching is performed in the same manner as described above. As a result, as shown in fig. 9, the etching proceeds from the first main surface S1 toward the second main surface S2 in the direction perpendicular to the first main surface S1 at the position of the first catalyst layer 80 a.

On the other hand, the second catalyst particles 81b move toward the first main surface S1 as etching progresses, and thus etching similar to that described above is performed. As a result, as shown in fig. 10, the etching proceeds from the second main surface S2 toward the first main surface S1 and in a direction perpendicular to the second main surface S2 at the position of the second catalyst layer 80 b.

As shown in fig. 11 and 12, the first concave portion R1 is formed on the first main surface S1, and the second concave portion R2 is formed on the second main surface S2. When the sum D1+ D2 of the depth D1 of the first recess R1 and the depth D2 of the second recess R2 is equal to or greater than the thickness T of the substrate 10, the first recess R1 and the second recess R2 are connected to each other at a position where they intersect, and the first through hole TH1 shown in fig. 6 is formed.

Thereafter, the first and second mask layers 90a and 90b and the catalyst layers 80a and 80b are removed from the substrate 10. One or more of the first and second mask layers 90a and 90b and the catalyst layers 80a and 80b may not be removed from the substrate 10.

Next, the first conductive layer 20a shown in fig. 2 to 6 is formed on the substrate 10. The first conductive layer 20a made of polysilicon can be formed by, for example, LPCVD (low pressure chemical vapor deposition). The first conductive layer 20a made of metal can be formed by, for example, electrolytic plating, reduction plating, or displacement plating.

The plating solution is a liquid containing a salt of a metal to be plated. As the plating solution, general plating solutions such as a copper sulfate plating solution containing copper sulfate pentahydrate and sulfuric acid, a copper pyrophosphate plating solution containing copper pyrophosphate and potassium pyrophosphate, and a nickel sulfamate plating solution containing nickel sulfamate and boron can be used.

The first conductive layer 20a is preferably formed by a plating method using a plating solution containing a salt to be plated, a surfactant, and carbon dioxide in a supercritical or subcritical state. In this plating method, a surfactant is interposed between particles made of supercritical carbon dioxide and a continuous phase made of a solution containing a metal to be plated salt. That is, in the plating liquid, the surfactant is formed into micelles (micelle), and the supercritical carbon dioxide is captured by these micelles.

In the normal plating method, the metal to be plated near the bottoms of the first concave portion R1 and the second concave portion R2 may not be sufficiently supplied. This is particularly significant in the case where the ratio of the depth D1 to the width or diameter W1, D1/W1, of the first concavity R1, and the ratio of the depth D2 to the width or diameter W2, D2/W2, of the second concavity R2 are large.

Even in a narrow gap, micelles that acquire supercritical carbon dioxide can easily enter. In addition, the solution containing the metal-plated salt moves with the movement of the micelles. Therefore, the first conductive layer 20a having a uniform thickness can be easily formed by a plating method using a plating solution containing a salt of a metal to be plated, a surfactant, and carbon dioxide in a supercritical or subcritical state.

Next, a dielectric layer 50 is formed on the first conductive layer 20 a. The dielectric layer 50 can be formed by CVD (chemical vapor deposition), for example. Alternatively, the dielectric layer 50 can be formed by oxidizing, nitriding, or oxynitriding the surface of the first conductive layer 20 a.

Next, a second conductive layer 20b is formed on the dielectric layer 50. The second conductive layer 20b can be formed by the same method as that described for the first conductive layer 20a, for example. The second conductive layer 20b is also preferably formed by a plating method using a plating solution containing a salt to be plated, a surfactant, and carbon dioxide in a supercritical or subcritical state.

Next, a plurality of through holes are formed in the laminate composed of the second conductive layer 20b and the dielectric layer 50. Here, the through holes are formed in the portion of the laminate that faces the first main surface with the first conductive layer 20a interposed therebetween, and at positions corresponding to intersections of the first concave portions R1 and the second concave portions R2. These through holes can be formed by, for example, formation of a mask by photolithography and patterning by etching.

Next, the first insulating layer 61 is formed on the fifth portion P5 and the seventh portion P7 of the second conductive layer 20 b. The first insulating layer 61 can be formed by CVD, for example.

After that, a second insulating layer 62 is formed on the first insulating layer 61. A through hole is provided in the second insulating layer 62 at a position of the through hole provided in the laminate. When a photosensitive resin is used as a material of the second insulating layer 62, the second insulating layer 62 having a through hole can be obtained by photolithography.

Next, the first insulating layer 61 is etched using the second insulating layer 62 as an etching mask. Thereby, a portion of the first insulating layer 61 covering the first conductive layer 20a is removed.

Next, the first metal layer 71 and the second metal layer 72 are formed in this order. The first metal layer 71 and the second metal layer 72 can be formed by a combination of film formation by sputtering or plating and photolithography, for example.

In the capacitor 1A, the laminated structure including the first conductive layer 20a, the dielectric layer 50, and the second conductive layer 20b is provided not only on the first main surface S1 but also on the second main surface S2 and in the first through hole TH 1. Therefore, the capacitor 1A can realize a large capacitance.

In the capacitor 1A, the first concave portion R1 and the second concave portion R2 are trenches. The above-described laminated structure is also provided on the side wall and the bottom surface of the trench. Therefore, the capacitor 1A can realize a large capacitance in particular.

For example, when the depth of the first concave portion R1 and the second concave portion R2 is 100 μm, the width thereof is 1 μm, the distance between the adjacent first concave portions R1 and the distance between the adjacent second concave portions R2 are both 1 μm, and a silicon oxide film having a thickness of 0.02 μm is used as the dielectric layer 50, the thickness of the capacitor 1A is set to about 0.2mm, about 650nF/mm can be realized²The capacitance density of (a).

In the capacitor 1A, the first concave portion R1 and the second concave portion R2 intersect with each other, and the sum D1+ D2 of the depths thereof is equal to or greater than the thickness T of the substrate 10. Therefore, when the first recess R1 and the second recess R2 are formed, the first through hole TH1 is generated at a position where they intersect. That is, unlike the case where the first recess R1 and the second recess R2, the sum of D1+ D2 of which is smaller than the thickness T, are simply formed on the first main surface S1 and the second main surface S2, a step of forming the first through hole TH1 is not required separately, except for the step of forming the first recess R1 and the second recess R2.

In the capacitor 1A, the first through hole TH1 electrically connects the portion located on the first main surface S1 and the portion located on the second main surface S2 in the laminated structure. Therefore, both the electrodes 70a and 70b can be disposed on one side of the capacitor 1A. That is, unlike the case where the first concave portion R1 and the second concave portion R2, the sum of D1+ D2 of which is smaller than the thickness T, are simply formed on the first main surface S1 and the second main surface S2, it is not necessary to form the electrodes 70a and 70b or wirings similar thereto on the second main surface S2, and therefore the number of steps can be greatly reduced. The capacitor 1A having such a configuration can be easily mounted on a wiring board or the like.

< second embodiment >

Fig. 13 is a sectional view schematically showing a capacitor according to a second embodiment.

The capacitor 1B shown in fig. 13 is the same as the capacitor 1A of the first embodiment except for the following configuration.

That is, the capacitor 1B includes the first dielectric layer 50a instead of the dielectric layer 50. The first dielectric layer 50a is the same as the dielectric layer 50 of the capacitor 1A of the first embodiment.

In the capacitor 1B, the second conductive layer 20B is a layer conforming to the first conductive layer 20 a.

The capacitor 1B further includes a second dielectric layer 50B and a third conductive layer 20 c.

A second dielectric layer 50b is disposed on the second conductive layer 20 b. The second dielectric layer 50b is a layer conformal to the first conductive layer 20 a. The second dielectric layer 50b can have, for example, the same configuration as the first dielectric layer 50 a.

The third conductive layer 20c is disposed on the second dielectric layer 50 b. The third conductive layer 20c can have the same configuration as the second conductive layer 20b, for example.

In the capacitor 1B, the electrodes 70a and 70B and the pads 70c and 70d shown in fig. 1 are formed of a laminate including a third metal layer 73 in addition to the first metal layer 71 and the second metal layer 72. The third metal layer 73 can have, for example, the same configuration as the first metal layer 71.

In the capacitor 1B, the electrode 70a is not in contact with the second conductive layer 20B, a part of the comb-teeth portion thereof is in contact with the first conductive layer 20a, and the other part of the comb-teeth portion thereof is in contact with the third conductive layer 20 c. That is, the first conductive layer 20a and the third conductive layer 20c are electrically connected to each other. In the capacitor 1B, the electrode 70B is not in contact with the first conductive layer 20a and the third conductive layer 20c, and the comb-teeth portion thereof is in contact with the second conductive layer 20B. That is, in the capacitor 1B, the electrode 70a is a first electrode, and the electrode 70B is a second electrode.

The capacitor 1B has the same effects as those described above with respect to the capacitor 1A.

In the capacitor 1B, the first conductive layer 20a, the first dielectric layer 50a, the second conductive layer 20B, the second dielectric layer 50B, and the third conductive layer 20c form a laminated structure. That is, in the capacitor 1B, more conductive layers are stacked with dielectric layers interposed therebetween than in the capacitor 1A. Therefore, the capacitor 1B can realize a larger capacitance.

For example, when the depth of the first concave portion R1 and the second concave portion R2 is 100 μm, the width thereof is 1 μm, the distance between the adjacent first concave portions R1 and the distance between the adjacent second concave portions R2 are both 1 μm, and a silicon oxide film having a thickness of 0.02 μm is used as the first dielectric layer 50a and the second dielectric layer 50B, it is possible to realize about 1300nF/mm if the thickness of the capacitor 1B is about 0.2mm²The capacitance density of (a).

< third embodiment >

Fig. 14 is a sectional view schematically showing a capacitor according to a third embodiment. Fig. 15 is a perspective view schematically showing a part of the capacitor shown in fig. 14. Fig. 15 shows a structure in which the electrode 70b, the electrode 70a, the insulating layer 60, and the second conductive layer 20b are omitted from the capacitor 1C shown in fig. 14.

The capacitor 1C shown in fig. 14 is the same as the capacitor 1A of the first embodiment except for the following configuration.

That is, in the capacitor 1C, the second concave portion R2 is omitted. That is, the capacitor 1C does not have the first through hole TH1 shown in fig. 6.

Instead, in the capacitor 1C, as shown in fig. 15, one or more second through holes TH2 that connect one and the other of the two adjacent first concave portions R1 are provided in one or more portions of the substrate 10 that are sandwiched between the two adjacent first concave portions R1. That is, in the capacitor 1C, the side wall of one first recess R1 of the two adjacent first recesses R1 corresponds to the first surface, and the side wall of the other first recess R1 corresponds to the second surface.

In the capacitor 1C, the stacked structure including the first conductive layer 20a, the dielectric layer 50, and the second conductive layer 20b is provided not only on the side walls and the bottom surface of the first main surface S1 and the first recess R1 but also on the side walls of the second through holes TH 2. That is, the first conductive layer 20a covers the side walls of the second through holes TH2 in addition to the side walls and the bottom surfaces of the first main surface S1 and the first recess R1. The second conductive layer 20b faces the side walls and the bottom surfaces of the first main surface S1 and the first recess R1 through the first conductive layer 20a, and also faces the side walls of the second through holes TH 2.

The average diameter of the second through holes TH2 is preferably 0.3 μm or more. When the diameter of the second through holes TH2 is reduced, more second through holes TH2 can be arranged, and thus, a larger capacitance can be realized. However, if the diameter of the second through holes TH2 is excessively reduced, it may be difficult to form a laminated structure of the first conductive layer 20a, the dielectric layer 50, and the second conductive layer 20b in the second through holes TH 2.

The ratio of the total area of the openings of the second through holes TH2 to the area of the side walls of the first recess R1 (hereinafter referred to as the aperture ratio) is preferably in the range of 30% to 90%, and preferably in the range of 50% to 90%. Further, the ratio of the number of second through holes TH2 provided in the side wall of the first recess R1 to the area of the side wall (hereinafter referred to as the hole density) is preferably 0.4 pieces/μm²To 20 pieces/. mu.m²More preferably 2 pieces/. mu.m²To 8 pieces/. mu.m²Within the range of (1).

If the aperture ratio and the hole density are increased, a larger capacitance can be realized. However, if the aperture ratio and the hole density are excessively increased, it may be difficult to form a laminated structure of the first conductive layer 20a, the dielectric layer 50, and the second conductive layer 20b in the second through holes TH 2.

The distance between adjacent first recesses R1 is preferably 0.1 μm or more, and more preferably 2 μm or more. If the distance is increased, a larger capacitance can be realized. However, since the rate of increase in capacitance with respect to the distance gradually decreases with an increase in distance, it is not effective to excessively increase the distance. When the distance is increased, it may be difficult to form a stacked structure of the first conductive layer 20a, the dielectric layer 50, and the second conductive layer 20b in the second through holes TH 2.

The capacitor 1C is manufactured by, for example, the following method.

Fig. 16 is a perspective view schematically showing an example of a substrate provided with a groove used for manufacturing the capacitor shown in fig. 14. Fig. 17 is a perspective view schematically showing a catalyst layer forming step in manufacturing the capacitor shown in fig. 14. Fig. 18 is a perspective view schematically showing an example of a structure obtained by an etching step in the manufacture of the capacitor shown in fig. 14.

In this method, as shown in fig. 16, a substrate 10 having a plurality of first concave portions R1 provided on the first main surface S1 is prepared. The first recess R1 is formed by, for example, MacEtch described with reference to fig. 7 to 12.

Next, the second through holes TH2 are formed in the substrate 10 by MacEtch.

That is, as shown in fig. 17, first, the catalyst particles 81a are deposited on the side walls of the first concave portions R1. The catalyst particles 81a are deposited so that gaps of a sufficient size are formed between the catalyst particles 81 a.

The catalyst particles 81a may be deposited on the bottom surface and the first main surface of the first recessed portion R1, but it is not necessarily required to be deposited. Therefore, a mask layer, not shown, may be formed so as to cover the bottom surface and the first main surface of the first concave portion R1 before the deposition of the catalyst particles 81 a.

Next, the substrate 10 is etched by the action of the noble metal as a catalyst, and the second through holes TH2 shown in fig. 18 are formed in the substrate 10. Specifically, the substrate 10 is etched with an etchant. For example, the substrate 10 is immersed in a liquid etchant, and the etchant is brought into contact with the substrate 10. As the etchant, the etchant described in the first embodiment can be used.

Since the catalyst particles 81a are deposited so as to form a gap of a sufficient size therebetween, a plurality of concave portions are formed in the side wall of the first concave portion R1. These recesses increase in depth as the etching progresses, and finally become the second through holes TH 2. As described above, the configuration shown in fig. 18 is obtained.

If a laminated structure of the first conductive layer 20a, the dielectric layer 50, and the second conductive layer 20b can be formed later on the side walls of the first recessed portion R1 in the recessed portion formed on the side walls thereof, the laminated structure constitutes a capacitor in the recessed portion formed on the side walls of the first recessed portion R1. Therefore, one or more of the recesses formed in the side wall of the first recess R1 may not necessarily be a through hole.

Thereafter, the first conductive layer 20a, the dielectric layer 50, the second conductive layer 20b, the insulating layer 60, the electrodes 70a and 70b, and the like are formed by the same method as that described in the first embodiment. Thus, the capacitor 1C is obtained.

In the capacitor 1C, a first recess R1 is provided, and a second through hole TH2 is provided in a side wall of the first recess R1. The laminated structure of the first conductive layer 20a, the dielectric layer 50, and the second conductive layer 20b is provided not only on the side walls and the bottom surfaces of the first main surface S1 and the first recess R1, but also on the side walls of the second through holes TH 2. Therefore, the capacitor 1C can realize a large capacitance.

For example, the depth of the first recessed portion R1 was 100 μm, the width was 1 μm, the distance between adjacent first recessed portions R1 was 1 μm, the aperture ratio in the side wall of the first recessed portion R1 was 30%, and the hole density was 2 pieces/μm²When a silicon oxide film having a thickness of 0.02 μm is used as the dielectric layer 50, the dielectric layer is electrically connected to the silicon oxide filmThe thickness of the vessel 1C is about 0.2mm, about 500nF/mm can be achieved²The capacitance density of (a).

< fourth embodiment >

Fig. 19 is a perspective view schematically showing a part of a capacitor according to a fourth embodiment.

The capacitor of the fourth embodiment is the same as the capacitor 1A of the first embodiment except for the following configuration.

That is, in this capacitor, one or more second through holes TH2 that connect one and the other of the two adjacent first concave portions R1 are provided in one or more portions of the substrate 10 that are sandwiched between the two adjacent first concave portions R1. That is, in this capacitor, the side wall of one first recess R1 of the two adjacent first recesses R1 corresponds to the first surface, and the side wall of the other first recess R1 corresponds to the second surface.

In the capacitor, one or more third through holes TH3 are provided in one or more portions of the substrate 10 sandwiched between the two adjacent second concave portions R2, respectively, to connect one of the two adjacent second concave portions R2 to the other. That is, in this capacitor, the side wall of one second recess R2 of the two adjacent second recesses R2 also corresponds to the first surface, and the side wall of the other second recess R2 also corresponds to the second surface.

In this capacitor, the stacked structure including the first conductive layer 20a, the dielectric layer 50, and the second conductive layer 20b is provided not only on the first main surface S1, the second main surface S2, the side walls and the bottom surface of the first recess R1, and the side walls and the bottom surface of the second recess R2, but also on the side walls of the second through-holes TH2 and the side walls of the third through-holes TH 3. That is, the first conductive layer 20a covers the side walls of the second through holes TH2 and the side walls of the third through holes TH3 in addition to the first main surface S1, the second main surface S2, the side walls and the bottom surfaces of the first recess R1, and the side walls and the bottom surfaces of the second recess R2. The second conductive layer 20b faces the side walls of the second through holes TH2 and the side walls of the third through holes TH3, in addition to the side walls and the bottom surfaces of the first main surface S1, the second main surface S2, and the first recess R1 through the first conductive layer 20 a.

The average diameter of the second through holes TH2 and the average diameter of the third through holes TH3 are preferably within the ranges described for the second through holes TH2 in the third embodiment.

The ratio of the total area of the openings of the second through holes TH2 to the area of the side walls of the first recess R1 is preferably within the range of the aperture ratio described with respect to the side walls of the first recess R1 in the third embodiment. Further, the ratio of the total area of the openings of the third through holes TH3 to the area of the side walls of the second recess R2 is preferably within the range of the aperture ratio described with respect to the side walls of the first recess R1 in the third embodiment.

The ratio of the number of the second through holes TH2 provided in the side wall of the first recess R1 to the area of the side wall is preferably within the range of the hole density described in the third embodiment. Further, the ratio of the number of the third through holes TH3 provided in the side wall of the second recess R2 to the area of the side wall is also preferably within the range of the hole density described in the third embodiment.

The distance between the adjacent first recesses R1 and the distance between the adjacent second recesses R2 are preferably within the ranges described in the third embodiment with respect to the distance between the adjacent first recesses R1.

The capacitor of the fourth embodiment can be obtained by, for example, performing the steps for forming the second through holes TH2 and the third through holes TH3 in the manufacture of the capacitor 1A of the first embodiment. The second through holes TH2 and the third through holes TH3 can be formed by the method described in the third embodiment, for example.

That is, first, a plurality of first concave portions R1 are formed on the first main surface S1 of the substrate 10, and a plurality of second concave portions R2 are formed on the second main surface S2 of the substrate 10. The first recess R1 and the second recess R2 are formed by, for example, MacEtch described in the first embodiment.

Next, a second catalyst layer containing a second noble metal is formed on the substrate 10 so as to partially cover the side walls of the first recess R1 and the side walls of the second recess R2.

Next, the substrate 10 is etched by the action of the second noble metal as a catalyst, and second through holes TH2 are formed in one or more portions of the substrate 10 sandwiched by the two adjacent first recesses R1, respectively, and third through holes TH3 are formed in one or more portions of the substrate 10 sandwiched by the two adjacent second recesses R2, respectively.

In the process of forming the second through holes TH2 and the third through holes TH3, holes or non-through holes having a smaller diameter than a preferred diameter may be formed. These layers are then buried in the first conductive layer 20a, the dielectric layer 50, and the second conductive layer 20b, or the first conductive layer 20a, the dielectric layer 50, and the second conductive layer 20b are conformally formed at these positions.

Thereafter, the first conductive layer 20a, the dielectric layer 50, the second conductive layer 20b, the insulating layer 60, the electrodes 70a and 70b, and the like are formed by the same method as that described in the first embodiment. Thus, the capacitor of the fourth embodiment is obtained.

In this capacitor, the first recess R1 and the second recess R2 are provided, and the second through hole TH2 and the third through hole TH3 are provided on the side wall of the first recess R1 and the side wall of the second recess R2, respectively. The laminated structure of the first conductive layer 20a, the dielectric layer 50, and the second conductive layer 20b is provided not only on the first main surface S1, the second main surface, the side walls and the bottom surface of the first recess R1, and the side walls and the bottom surface of the second recess R2, but also on the side walls of the second through-holes TH2 and the side walls of the third through-holes TH 3. Therefore, the capacitor 1C can realize a large capacitance.

In this capacitor, the first recess R1 and the second recess R2 are trenches. The above-described laminated structure is also provided on the side wall and the bottom surface of the trench. Therefore, the capacitor can realize a large capacitance in particular.

For example, the depth of the first recess R1 and the second recess R2 is 100 μm, the width thereof is 1 μm, the distance between the adjacent first recesses R1 and the distance between the adjacent second recesses R2 are both 1 μm, and the second through holes TH2 and the third through holes TH3 are formed on the side wall of the first recess R1And the opening ratio of each of the side walls of the second recessed portion R2 was 30%, and the hole density was 2 pieces/μm²When a silicon oxide film having a thickness of 0.02 μm is used as the dielectric layer 50, the capacitor can have a thickness of about 1000nF/mm by making the thickness of the capacitor about 0.2mm²The capacitance density of (a).

In the capacitor, the first concave portion R1 and the second concave portion R2 intersect with each other, and the sum D1+ D2 of the depths thereof is equal to or greater than the thickness T of the substrate 10. Therefore, if the first recess R1 and the second recess R2 are formed, the first through hole TH1 is generated at a position where they intersect. That is, unlike the case where the first recess R1 and the second recess R2, the sum of D1+ D2 of which is smaller than the thickness T, are simply formed on the first main surface S1 and the second main surface S2, a step of forming the first through hole TH1 is not required separately, except for the step of forming the first recess R1 and the second recess R2.

In this capacitor, the first through hole TH1 electrically connects the portion on the first main surface S1 and the portion on the second main surface S2 in the laminated structure. Therefore, both of the electrodes 70a and 70b shown in fig. 1 can be arranged on one side of the capacitor. That is, unlike the case where the first concave portion R1 and the second concave portion R2, the sum of D1+ D2 of which is smaller than the thickness T, are simply formed on the first main surface S1 and the second main surface S2, it is not necessary to form the electrodes 70a and 70b or wirings similar thereto on the second main surface S2, and therefore the number of steps can be greatly reduced. Further, the capacitor having such a configuration can be easily mounted on a wiring board or the like.

< fifth embodiment >

Fig. 20 is a sectional view schematically showing a capacitor according to a fifth embodiment. Fig. 21 is a perspective view schematically showing a part of the capacitor shown in fig. 20. Fig. 22 is a cross-sectional view taken along line XXII-XXII of the capacitor shown in fig. 21. Fig. 21 shows a structure in which the electrode 70b, the electrode 70a, the insulating layer 60, and the second conductive layer 20b are omitted from the capacitor 1D shown in fig. 20.

The capacitor 1D shown in fig. 20 is the same as the capacitor 1C of the third embodiment except for the following configuration.

That is, in the capacitor 1D, as shown in fig. 21, a plurality of first holes H1 and a plurality of second holes H2 are provided on the side wall of the first recess R1 instead of the plurality of second through holes TH 2.

As shown in fig. 22, the first holes H1 extend in the first direction D1, respectively, which is inclined with respect to the side walls of the first recess R1. That is, the longitudinal direction or the depth direction of the first hole H1 is parallel to each other, and is inclined with respect to the side wall of the first recess R1.

Each of the first holes H1 may be a blind hole that extends from one of two adjacent first recesses R1 and does not reach the other. Alternatively, each of the first holes H1 may be a through hole that connects one and the other of two adjacent ones of the two or more first recesses R1. Alternatively, one or more of the first holes H1 may be blind holes, and the remaining first holes H1 may be through holes.

The second holes H2 extend in the second direction D2 crossing the first direction D1, respectively. That is, the longitudinal direction or the depth direction of the second hole H2 is parallel to each other, and is inclined with respect to the side wall of the first recess R1. Each of the second holes H2 may or may not be connected to more than one of the first holes H1. Each of the second holes H2 may or may not intersect at least one of the first holes H1.

Each of the second holes H2 may be a blind hole that extends from one of two adjacent ones of the two or more first recesses R1 and does not reach the other. Alternatively, each of the second holes H2 may be a through hole that connects one and the other of two adjacent ones of the two or more first recesses R1. Alternatively, one or more of the second holes H2 may be blind holes, and the remaining second holes H2 may be through holes.

As shown in fig. 20 to 22, in the capacitor 1D, the stacked structure including the first conductive layer 20a, the dielectric layer 50, and the second conductive layer 20b is provided not only on the side walls and the bottom surface of the first main surface S1 and the first recess R1 but also on the side walls of the first hole H1 and the side walls of the second hole H2. That is, the first conductive layer 20a covers the side walls of the first hole H1 and the side walls of the second hole H2 in addition to the side walls and the bottom surface of the first main surface S1 and the first recess R1. The second conductive layer 20b faces the side walls and the bottom surface of the first main surface S1 and the first recess R1, and also faces the side walls of the first hole H1 and the side walls of the second hole H2 through the first conductive layer 20 a.

In the capacitor 1D, a first hole H1 is provided in a side wall of the first recess R1. Therefore, the substrate 10 of the capacitor 1D has a larger surface area than a substrate in which no hole is provided in the sidewall of the first recess R1.

In addition, the first holes H1 extend in the first direction D1 inclined with respect to the side wall of the first recess R1, respectively. Therefore, the substrate 10 of the capacitor 1D has a larger surface area than a substrate in which a hole extending in a direction perpendicular to the side wall of the first recess R1 is provided in the side wall of the first recess R1.

In the capacitor 1D, the stacked structure of the first conductive layer 20a, the dielectric layer 50, and the second conductive layer 20b is provided not only on the side walls and the bottom surface of the first main surface S1 and the first recess R1, but also on the side walls of the first hole H1.

Therefore, the capacitor 1D can realize a larger capacitance than a capacitor in which no hole is provided in the side wall of the first recess R1. In addition, the capacitor 1D can realize a larger capacitance than a capacitor provided with a hole extending in a direction perpendicular to the side wall of the first concave portion R1.

For example, the aperture ratio of the side wall of the first recess R1 was 80%, the thickness of the first conductive layer 20a was 100nm, and the thickness was 1 μm²When the number of the first holes H1 is about several, the surface area of the first conductive layer 20a when the angle formed by the first direction D1 and the side wall of the first recess R1 is 45 ° can be made about 1.36 times the surface area of the first conductive layer 20a when the angle is 90 °. From this, it is understood that the capacitor in which the first direction D1 is inclined with respect to the side wall of the first recess R1 can realize a larger capacitance than the capacitor in which the first direction D1 is perpendicular with respect to the side wall of the first recess R1.

In the capacitor 1D, a second hole H2 is provided in a side wall of the first recess R1. If the second hole H2 is provided in addition to the first hole H1, a larger capacitance can be achieved.

In the capacitor 1D, the longitudinal directions of the first holes H1 are parallel to each other, and the longitudinal directions of the second holes H2 are also parallel to each other. Therefore, it is difficult to cause a decrease in mechanical strength caused by the connection of the first holes H1 and the connection of the second holes H2.

Therefore, according to this configuration, a large capacitance and a high mechanical strength can be achieved.

The angle formed by the first direction D1 and the side wall of the first recess R1 and the angle formed by the second direction D2 and the side wall of the first recess R1 are each preferably in the range of 10 ° to 80 °, more preferably in the range of 30 ° to 60 °. If this angle is reduced, the mechanical strength of the capacitor 1D is reduced. When the angle is increased, the capacitance increases less as the first direction D1 and the second direction D2 are tilted.

The angle formed by the first direction D1 and the second direction D2 is preferably in the range of 20 ° to 160 °, more preferably in the range of 60 ° to 120 °. It is particularly preferred that the first direction D1 is orthogonal to the second direction D2. If the angle is excessively decreased or increased, the mechanical strength of the capacitor 1D becomes low.

The side wall of the first recess R1 may be provided with another hole, in addition to the first hole H1 and the second hole H2, which extends in one direction and has a longitudinal direction different from the first direction D1 and the second direction D2. For example, as such other holes, a plurality of holes whose longitudinal directions are parallel to each other and which intersect the first direction D1 and the second direction D2, and a plurality of holes whose longitudinal directions are parallel to each other and which intersect the first direction D1, may be further provided on the side wall of the first recess R1,

A plurality of holes intersecting the second direction D2 and the length direction of the previous hole.

Fig. 23 is a photomicrograph showing a cross section of the capacitor shown in fig. 21. The photomicrograph of fig. 23 is a photomicrograph of a cross-section corresponding to fig. 22. In fig. 23, the longitudinal direction is the X direction and the lateral direction is the Y direction.

The photomicrograph of fig. 23 has the (001) plane as the main surface, and shows a cross section parallel to the (001) plane of the single crystal silicon wafer in which the first recesses R1, the longitudinal direction of which is parallel to the < 100 > axis, were provided on the preceding main surface. The first direction D1 and the second direction D2 are directions parallel to the < 110 > axis and the < -110 > axis in FIG. 23, respectively. Thus, the structure in which the first direction D1 and the second direction D2 are orthogonal is particularly advantageous in terms of achieving a large capacitance and high mechanical strength.

The average diameter of the first holes H1 and the average diameter of the second holes H2 are preferably within the ranges described in the third embodiment for the second through holes TH 2. When the diameter of the first hole H1 and the diameter of the second hole H2 are reduced, more of the first hole H1 and the second hole H2 can be arranged, and thus, a larger capacitance can be realized. However, if the diameter of the first hole H1 and the diameter of the second hole H2 are excessively reduced, it may be difficult to form a stacked structure of the first conductive layer 20a, the dielectric layer 50, and the second conductive layer 20b in the first hole H1 and the second hole H2.

The ratio of the sum of the total area of the openings of the first holes H1 and the total area of the openings of the second holes H2 to the area of the side wall of the first recess R1 (hereinafter referred to as the aperture ratio) is preferably within the range of the aperture ratio described for the side wall of the first recess R1 in the third embodiment. The ratio of the total number of the first holes H1 and the second holes H2 provided on the side wall of the first recess R1 to the area of the side wall (hereinafter referred to as the hole density) is preferably within the range of the hole density described in the third embodiment.

If the aperture ratio and the hole density are increased, a larger capacitance can be realized. However, if the aperture ratio and the hole density are excessively increased, it may be difficult to form a stacked structure of the first conductive layer 20a, the dielectric layer 50, and the second conductive layer 20b in the first hole H1 and the second hole H2. Further, if the hole density is excessively increased, the surface area of the side wall of the first concave portion R1 tends to be reduced as the holes and the holes are easily connected. Thus, it may also be difficult to achieve a large capacitance.

In the capacitor 1D, the second hole H2 may be omitted.

The portion of the substrate 10 adjacent to the first recess R1 is preferably made of a crystal having a face-centered cubic structure. In this case, the main surface of the substrate 10 is preferably a (001) surface. In this case, the longitudinal direction of the first concave portion R1 is preferably inclined with respect to the < 110 > axis. In this way, the first hole H1 and the second hole H2 can be formed by the method described below. Here, as an example, a single crystal silicon wafer is used as the substrate 10 having a crystal structure of a face-centered cubic structure and having a (001) plane as a main surface.

First, a first concave portion R1 whose longitudinal direction is inclined with respect to the < 110 > axis is formed on the main surface of the substrate 10. For example, the first concave portion R1 is formed with its longitudinal direction parallel to the < 100 > axis. The first recessed portion R1 can be formed by the method described with reference to fig. 7 to 12, for example.

Next, catalyst particles are deposited on the side walls of the first concave portion R1. The deposit of the catalyst particles can be formed by the method described with reference to fig. 17, for example.

Next, the substrate 10 is etched under the action of a noble metal as a catalyst, and the first hole H1 and the second hole H2 are formed. Specifically, the substrate 10 is immersed in an etchant, and the etchant is brought into contact with the substrate 10. As the etchant, the etchant described in the first embodiment can be used.

In the case where the catalyst particles are integrally formed by contacting each other, etching proceeds in the thickness direction of the catalyst layer.

On the other hand, when the catalyst particles are separated from each other, the orientation of the crystal constituting the substrate is affected in the traveling direction of etching. For example, in the example described here, the etching easily progresses in a direction parallel to the < 110 > axis, or in a direction parallel to an equivalent axis, for example, the < -110 > axis.

Thus, according to the above-described method, the configuration shown in fig. 20 to 23 can be obtained.

< sixth embodiment >

Fig. 24 is a perspective view schematically showing a part of a capacitor according to a sixth embodiment.

The capacitor of the sixth embodiment is the same as the capacitor of the fourth embodiment except for the following configuration.

That is, as shown in fig. 24, in the capacitor, a plurality of first holes H1 and a plurality of second holes H2 are provided on the side wall of the first recess R1 instead of the plurality of second through holes TH 2. In addition, a plurality of third holes H3 and a plurality of fourth holes H4 are provided in the side wall of the second recess R2 instead of the plurality of third through holes TH 3.

The first hole H1 and the second hole H2 in this capacitor are the same as the first hole H1 and the second hole H2 in the capacitor 1D of the fifth embodiment.

The third holes H3 extend in third directions inclined with respect to the side walls of the second recess R2, respectively. That is, the longitudinal direction or the depth direction of the third hole H3 is parallel to each other and is inclined with respect to the side wall of the second recess R2.

Each of the third holes H3 may be a blind hole that extends from one of two adjacent ones of the two or more second recesses R2 and does not reach the other. Alternatively, each of the third holes H3 may be a through hole that connects one and the other of two adjacent ones of the two or more second recesses R2. Alternatively, one or more of the third holes H3 may be blind holes, and the remaining third holes H3 may be through holes.

The fourth holes H4 extend in fourth directions intersecting the third directions, respectively. That is, the longitudinal direction or the depth direction of the fourth hole H4 is parallel to each other, and is inclined with respect to the side wall of the second recess R2. Each of the fourth holes H4 may or may not be connected to more than one of the third holes H3. Each of the fourth holes H4 may or may not intersect at least one of the third holes H3.

Each of the fourth holes H4 may be a blind hole that extends from one of two adjacent ones of the two or more second recesses R2 and does not reach the other. Alternatively, each of the fourth holes H4 may be a through hole that connects one and the other of two adjacent ones of the two or more second recesses R2. Alternatively, one or more of the fourth holes H4 may be blind holes, and the remaining fourth holes H4 may be through holes.

In this capacitor, the stacked structure including the first conductive layer 20a, the dielectric layer 50, and the second conductive layer 20b is provided not only on the side walls and the bottom surfaces of the first main surface S1, the second main surface S2, the first recess R1, and the second recess R2, but also on the side walls of the first hole H1, the second hole H2, the third hole H3, and the fourth hole H4. That is, the first conductive layer 20a covers the side walls of the first hole H1, the side walls of the second hole H2, the side walls of the third hole H3, and the side walls of the fourth hole H4 in addition to the side walls and the bottom surfaces of the first main surface S1, the second main surface S2, the first recess R1, and the second recess R2. The second conductive layer 20b faces the side walls and the bottom surface of the first main surface S1, the second main surface S2, and the first recess R1 through the first conductive layer 20a, and also faces the side walls of the first hole H1, the second hole H2, the third hole H3, and the fourth hole H4.

As described above, the capacitor is the same as the capacitor of the fourth embodiment except that the first hole H1 and the second hole H2 are provided instead of the second through hole TH2, and the third hole H3 and the fourth hole H4 are provided instead of the third through hole TH 3. Therefore, the capacitor has the same effects as those of the capacitor according to the fourth embodiment except for the features described with respect to the second through holes TH2 and the third through holes TH 3.

In addition, in the capacitor, a first hole H1, a second hole H2, a third hole H3, and a fourth hole H4 are provided. Therefore, the substrate 10 of the capacitor has a larger surface area than a substrate in which no hole is provided in any of the side walls of the first concave portion R1 and the second concave portion R2.

The first hole H1 and the second hole H2 each extend in a direction inclined with respect to the side wall of the first recess R1, and the third hole H3 and the fourth hole H4 each extend in a direction inclined with respect to the side wall of the second recess R2. Therefore, the substrate 10 of the capacitor has a larger surface area than a substrate in which a hole extending in a direction perpendicular to the side walls is provided in the side walls of the first concave portion R1 and a hole extending in a direction perpendicular to the side walls is provided in the side walls of the second concave portion R2.

The laminated structure of the first conductive layer 20a, the dielectric layer 50, and the second conductive layer 20b is provided not only on the side walls and the bottom surfaces of the first main surface S1, the second main surface S2, the first recess R1, and the second recess R2, but also on the side walls of the first hole H1, the second hole H2, the third hole H3, and the fourth hole H4.

Therefore, this capacitor can realize a larger capacitance than a capacitor in which no hole is provided in any of the side walls of the first concave portion R1 and the second concave portion R2. In addition, this capacitor can realize a larger capacitance than a capacitor in which a hole extending in a direction perpendicular to the side walls is provided in the side walls of the first concave portion R1 and a hole extending in a direction perpendicular to the side walls is provided in the side walls of the second concave portion R2.

Each of the angle formed by the first direction D1 and the side wall of the first recess R1, the angle formed by the second direction D2 and the side wall of the first recess R1, the angle formed by the third direction and the side wall of the second recess R2, and the angle formed by the fourth direction and the side wall of the second recess R2 is preferably within the range described in the fifth embodiment with respect to the angles formed by the first direction D1 and the second direction D2 and the side wall of the first recess R1.

The angle formed between the first direction D1 and the second direction D2 and the angle formed between the third direction and the fourth direction are preferably within the ranges described in the fifth embodiment with respect to the angle formed between the first direction D1 and the second direction D2.

One of the first direction D1 and the second direction D2 is preferably parallel to or orthogonal to one of the third direction and the fourth direction. In this case, the hole is easily formed.

The average diameter of the first holes H1, the average diameter of the second holes H2, the average diameter of the third holes H3, and the average diameter of the fourth holes H4 are preferably within the ranges described for the second through holes TH2 in the third embodiment.

The ratio of the aperture ratio of the side walls of the first recess R1, i.e., the sum of the total area of the openings of the first holes H1 and the total area of the openings of the second holes H2, to the area of the side walls is preferably within the range of the aperture ratio described for the side walls of the first recess R1 in the third embodiment. The ratio of the opening ratio of the side wall of the second recess R2, i.e., the sum of the total area of the openings of the third holes H3 and the total area of the openings of the fourth holes H4 to the area of the side wall, is also preferably within the range of the opening ratio described for the side wall of the first recess R1 in the third embodiment.

The hole density in the side wall of the first recess R1, that is, the ratio of the total number of the first holes H1 and the second holes H2 provided in the side wall to the area of the side wall, is preferably within the range of the hole density described in the third embodiment. Further, the hole density in the side wall of the second recess R2, that is, the ratio of the total number of the third holes H3 and the fourth holes H4 provided in the side wall to the area of the side wall is also preferably within the range of the hole density described in the third embodiment.

If the aperture ratio and the hole density are increased, a larger capacitance can be realized. However, if the aperture ratio and the hole density are excessively increased, it may be difficult to form a stacked structure of the first conductive layer 20a, the dielectric layer 50, and the second conductive layer 20b in the first hole H1, the second hole H2, the third hole H3, and the fourth hole H4. Further, if the hole density is excessively increased, the surface area of the side wall of the first concave portion R1 and the second concave portion R2 is easily reduced along with the connection between the holes. Thus, it may also be difficult to achieve a large capacitance.

In this capacitor, if one or more first hole H1, second hole H2, third hole H3, and fourth hole H4 are provided, the rest may be omitted.

The portion of the substrate 10 adjacent to the first recess R1 and the portion adjacent to the second recess R2 are preferably made of crystals having a face-centered cubic structure. In this case, the first main surface S1 is preferably a (001) surface, and the second main surface S2 is preferably a surface parallel to the first main surface S1. In this case, the longitudinal direction of the first concave portion R1 and the second concave portion R2 is preferably inclined with respect to the < 110 > axis. In this manner, the first hole H1, the second hole H2, the third hole H3, and the fourth hole H4 can be formed by the method described below. Here, as an example, a single crystal silicon wafer is used as the substrate 10 which is composed of a crystal having a face-centered cubic structure, and has the first main surface S1 as a (001) plane and the second main surface S2 as a plane parallel to the first main surface S1.

First, a first concave portion R1 whose longitudinal direction is inclined with respect to the < 110 > axis is formed on the first main surface S1 of the substrate 10, and a second concave portion R2 whose longitudinal direction is inclined with respect to the < 110 > axis is formed on the second main surface S2 of the substrate 10. The first recess R1 and the second recess R are formed by, for example, the MacEtch described in the first embodiment.

Next, a second catalyst layer containing a second noble metal is formed on the substrate 10 so as to partially cover the side walls of the first recess R1 and the side walls of the second recess R2.

Next, the substrate 10 is etched by using the second noble metal as a catalyst, so that the first hole H1 and the second hole H2 are formed in the sidewall of the first recess R1, and the third hole H3 and the fourth hole H4 are formed in the sidewall of the second recess R2.

As described in the fifth embodiment, when the catalyst particles are separated from each other, the orientation of the crystal constituting the substrate is affected in the traveling direction of etching. For example, in the example described here, the etching easily progresses in a direction parallel to the < 110 > axis, or in a direction parallel to an equivalent axis, for example, the < -110 > axis. Thus, by the above-described method, the configuration shown in fig. 24 can be obtained.

Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.

For example, the capacitors of the third to sixth embodiments may have a laminated structure of the first conductive layer 20a, the first dielectric layer 50a, the second conductive layer 20B, the second dielectric layer 50B, and the third conductive layer 20c, instead of the laminated structure of the first conductive layer 20a, the dielectric layer 50, and the second conductive layer 20B, as in the capacitor 1B of the second embodiment.

In addition, the second through holes TH2 or the third through holes TH3 may be omitted from the capacitor of the fourth embodiment.