阅读说明：本技术 比较电路、半导体装置、电子构件以及电子设备 (Comparator circuit, semiconductor device, electronic component, and electronic apparatus ) 是由 松嵜隆德 加藤清 于 2018-05-22 设计创作，主要内容包括：提供一种能够直接输入要比较的负电压的比较电路。该比较电路包括第一输入端子、第二输入端子、第一输出端子以及差分对。该比较电路对负电压与负参考电压进行比较,根据比较结果从第一输出端子输出第一输出电压。第一输入端子被输入负电压。第二输入端子被输入正参考电压。以进行比较的方式设定正参考电压。差分对包括分别包括背栅极的第一n沟道晶体管及第二n沟道晶体管。第一输入端子与第一n沟道晶体管的背栅极电连接。第二输入端子与第二n沟道晶体管的栅极电连接。(Provided is a comparator circuit capable of directly inputting a negative voltage to be compared. The comparison circuit includes a first input terminal, a second input terminal, a first output terminal, and a differential pair. The comparison circuit compares the negative voltage with a negative reference voltage, and outputs a first output voltage from the first output terminal according to the comparison result. The first input terminal is inputted with a negative voltage. The second input terminal is inputted with a positive reference voltage. The positive reference voltage is set in a manner to make a comparison. The differential pair includes a first n-channel transistor and a second n-channel transistor that each include a back gate. The first input terminal is electrically connected to the back gate of the first n-channel transistor. The second input terminal is electrically connected to a gate of the second n-channel transistor.)

1. A comparison circuit, comprising:

a first input terminal;

a second input terminal;

a first output terminal; and

a differential input circuit comprising a differential pair of a first n-channel transistor and a second n-channel transistor, both comprising a gate and a back-gate,

wherein the comparison circuit compares the negative voltage with a negative reference voltage and outputs a first output voltage from the first output terminal according to a comparison result,

the first input terminal is inputted with the negative voltage,

the second input terminal is inputted with a positive reference voltage,

the positive reference voltage is set in a comparative manner,

one of the gate and the back gate of the first n-channel transistor is input with a first bias voltage,

the other of the gate and the back gate of the first n-channel transistor is electrically connected to the first input terminal,

one of the gate and the back gate of the second n-channel transistor is electrically connected to the second input terminal,

and the other of the gate and the back gate of the second n-channel transistor is input with a second bias voltage.

2. The comparison circuit as set forth in claim 1,

wherein the back gate of the first n-channel transistor is input with the first bias voltage,

and the gate of the first n-channel transistor is input with the first negative voltage.

3. The comparison circuit according to claim 1 or 2,

wherein the back gate of the second n-channel transistor is input with the positive reference voltage,

and the gate of the second n-channel transistor is input with the second bias voltage.

4. The comparison circuit as set forth in claim 1,

wherein the first bias voltage is a high-level side power supply voltage of the comparison circuit.

5. The comparison circuit as set forth in claim 1,

wherein the second bias voltage is a low-level side power supply voltage of the comparison circuit.

6. The comparison circuit as set forth in claim 1,

wherein a channel formation region of the first n-channel transistor and a channel formation region of the second n-channel transistor comprise a metal oxide.

7. The comparison circuit as set forth in claim 1,

wherein the comparison circuit is a dynamic comparison circuit,

and the differential input circuit includes a latch circuit electrically connected to the differential pair.

8. A semiconductor device, comprising:

a charge pump circuit;

a drive circuit; and

the comparison circuit as set forth in claim 1,

wherein an output terminal of the charge pump circuit is electrically connected with the first input terminal of the comparison circuit,

the drive circuit is inputted with the first output voltage from the comparison circuit,

and the driving circuit generates a clock signal for driving the charge pump circuit according to the first output voltage.

9. The semiconductor device as set forth in claim 8,

wherein a plurality of n-channel transistors electrically connected in series are provided in a charge transfer path of the charge pump circuit,

the plurality of n-channel transistors includes a back gate electrically connected to the gate,

and the channel formation regions of the plurality of n-channel transistors include a metal oxide.

10. A semiconductor device, comprising:

first to Nth voltage output terminals, N being an integer of 2 or more;

a negative voltage generating circuit;

a control circuit;

first to Nth charge pump circuits;

first to Nth monitor circuits; and

a first to an Nth driving circuits for driving the first and the Nth driving circuits,

wherein the control circuit generates a first clock signal for driving the negative voltage generation circuit,

an output terminal of the negative voltage generation circuit is electrically connected to input terminals of the first to Nth charge pump circuits,

an output terminal of the jth charge pump circuit is electrically connected to a jth voltage output terminal, j is an integer from 1 to N,

the jth monitor circuit includes a comparison circuit [ j ],

the comparison circuit [ j ] is the comparison circuit of claim 1,

the first input terminal of the comparison circuit [ j ] is electrically connected to the jth voltage output terminal,

the first output terminal of the comparison circuit [ j ] is electrically connected to an input terminal of a j-th drive circuit,

the jth drive circuit generates a second clock signal for driving the jth charge pump circuit based on the first clock signal and a first output voltage output from the comparison circuit [ j ].

11. A semiconductor device, comprising:

first to Nth voltage output terminals, N being an integer of 2 or more;

a negative voltage generating circuit;

a control circuit;

a frequency dividing circuit;

first to Nth charge pump circuits;

first to Nth monitor circuits; and

a first to an Nth driving circuits for driving the first and the Nth driving circuits,

wherein the control circuit generates a first clock signal for driving the negative voltage generation circuit,

the frequency dividing circuit divides the first clock signal to generate a second clock signal,

an output terminal of the negative voltage generation circuit is electrically connected to input terminals of the first to Nth charge pump circuits,

an output terminal of the jth charge pump circuit is electrically connected to a jth voltage output terminal, j is an integer from 1 to N,

the jth monitor circuit includes a comparison circuit [ j ],

the comparison circuit [ j ] is the comparison circuit of claim 7,

the first input terminal of the comparison circuit [ j ] is electrically connected to the jth voltage output terminal,

the first output terminal of the comparison circuit [ j ] is electrically connected to an input terminal of the j-th drive circuit,

the jth drive circuit generates a third clock signal for driving the jth charge pump circuit based on the second clock signal and the first output voltage output from the comparison circuit [ j ].

12. The semiconductor device as set forth in claim 11,

wherein the jth monitor circuit further includes a latch circuit [ j ] and a circuit [ j ],

the jth latch circuit is located between the first output terminal of the comparison circuit [ j ] and the jth voltage output terminal,

and the circuit [ j ] inputs a voltage lower than the positive reference voltage to the second input terminal of the comparison circuit [ j ] according to an output of the jth latch circuit.

13. The semiconductor device as set forth in claim 11,

wherein the jth monitor circuit further includes a selection circuit [ j ],

and the selection circuit [ j ] inputs a low-level side power supply voltage to the differential input circuit of the comparison circuit [ j ] in accordance with the first output voltage from the first output terminal of the comparison circuit [ j ].

14. An electronic component on which a chip is mounted,

wherein the chip comprises the semiconductor device of any one of claims 8 to 13.

15. An electronic device, comprising:

the electronic component of claim 14; and

at least one of a display section, a microphone, a speaker, an operation key, and a housing.

Technical Field

One embodiment of the present invention disclosed in the specification, drawings, and claims of the present application (hereinafter, referred to as the present specification and the like) relates to a semiconductor device, an operating method thereof, a using method thereof, a manufacturing method thereof, and the like. Note that one embodiment of the present invention is not limited to the above-described technical field.

Background

Semiconductor devices using negative voltages are known. For example, in order to reduce the threshold leakage current, the substrate bias voltage of the n-channel MOS transistor is a negative voltage, and the substrate bias voltage of the p-channel MOS transistor is a positive voltage (for example, patent document 1). In the flash memory, a negative voltage is used according to the operation (for example, patent document 2).

The negative voltage may be generated using a charge pump circuit. Patent documents 2 and 3 disclose techniques for generating a negative voltage with high accuracy. In patent documents 2 and 3, a negative voltage output from a charge pump circuit is converted into a positive voltage, a difference between the positive voltage and a positive reference voltage is detected by a comparator circuit, and the operation of the charge pump circuit is controlled based on the detection result.

In this specification and the like, the ground voltage (GND) is regarded as 0V, and positive and negative voltages are defined with reference to the ground voltage.

A transistor including a metal oxide in a channel formation region (hereinafter, such a transistor is also referred to as an oxide semiconductor transistor or an OS transistor) is known. Various semiconductor devices are manufactured by a hybrid CMOS process of an OS transistor and an Si transistor (for example, non-patent document 1). As shown in non-patent document 1, an OS transistor can be stacked on an Si transistor.

The Si transistor can control a threshold voltage (hereinafter, also referred to as Vt) by introducing an impurity. However, reliable techniques for controlling the threshold voltage of OS transistors have not been established. For example, in patent document 4, the threshold voltage of an OS transistor including a first gate electrode (also referred to as a gate or a front gate) and a second gate electrode (also referred to as a back gate) is controlled by controlling the voltage of the second gate electrode. The threshold voltage of the OS transistor of the n-channel transistor shifts to the positive side when a negative voltage is input to the second gate electrode.

[ reference documents ]

[ patent document ]

[ patent document 1] Japanese patent application laid-open No. Hei 11-191611

[ patent document 2] Japanese patent application laid-open No. Hei 7-231647

[ patent document 3] Japanese patent application laid-open No. Hei 11-150230

[ patent document 4] Japanese patent application laid-open No. 2012 and 069932

[ non-patent document 1] T.Onkki et al, "Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide field with 65-nm Si CMOS," Symp.VLSI Circuits dig.Tech.papers, pp.124-125, Jun.2016.

Disclosure of Invention

An object of an embodiment of the present invention is: providing a comparison circuit capable of directly inputting a negative voltage to be compared; generating high-precision negative voltage; and reduce power consumption, etc.

Note that one embodiment of the present invention need not achieve all of the above-described objects. The description of multiple purposes does not preclude the existence of such purposes. Other objects can be naturally found from the description of the present specification and the like, and such an object may be an object of one embodiment of the present invention.

(1) One embodiment of the present invention is a comparison circuit including a first input terminal, a second input terminal, a first output terminal, and a differential input circuit. The comparison circuit compares the negative voltage with a negative reference voltage, and outputs a first output voltage from the first output terminal according to the comparison result. The first input terminal is inputted with a negative voltage. The second input terminal is inputted with a positive reference voltage. The positive reference voltage is set in a manner to make a comparison. The differential input circuit includes a differential pair of a first n-channel transistor and a second n-channel transistor. The first n-channel transistor and the second n-channel transistor both include a gate and a back gate. The gate of the first n-channel transistor is input with a first bias voltage. The back gate of the first n-channel transistor is electrically connected to the first input terminal. The gate of the second n-channel transistor is electrically connected to the second input terminal. The back gate of the second n-channel transistor is input with a second bias voltage.

(2) In embodiment mode (1), the channel formation regions of the first n-channel transistor and the second n-channel transistor include a metal oxide.

(3) The comparison circuit according to the above embodiment (1) or (2) is a dynamic comparison circuit. The differential input circuit includes a latch circuit electrically connected to the differential pair.

(4) One embodiment of the present invention is a semiconductor device including: a buck charge pump circuit; a drive circuit; and the comparison circuit according to any one of the above embodiments (1) to (3). The output terminal of the step-down charge pump is electrically connected to the first input terminal of the comparison circuit. The first output voltage is input from the comparison circuit to the drive circuit. The driving circuit generates a clock signal for driving the buck charge pump according to the first output voltage.

According to one embodiment of the present invention, a comparison circuit capable of directly inputting a negative voltage to be compared can be provided. Further, a negative voltage with high accuracy can be generated. In addition, power consumption can be reduced.

In one embodiment of the present invention, all of the above effects need not be obtained. The description of the multiple effects does not hinder the existence of other effects. In one embodiment of the present invention, objects other than the above objects, effects other than the above effects, and novel features can be naturally understood from the description and drawings in the present specification.

Drawings

Fig. 1A and 1B are circuit diagrams showing a configuration example of a comparison circuit, and fig. 1C is a diagram schematically showing drain current-gate voltage characteristics of a transistor.

Fig. 2 is a circuit diagram showing a configuration example of the comparison circuit.

Fig. 3A and 3B are circuit diagrams showing a configuration example of the comparison circuit.

Fig. 4A to 4C are circuit diagrams showing a configuration example of the comparison circuit.

Fig. 5 is a circuit diagram showing a configuration example of the comparison circuit.

Fig. 6 is a block diagram showing a structural example of the negative voltage supply device.

Fig. 7 is a circuit diagram showing a configuration example of the charge pump circuit.

Fig. 8A to 8C are circuit diagrams showing a configuration example of the charge pump circuit.

Fig. 9A is a circuit diagram showing a configuration example of the negative voltage holding circuit, and fig. 9B is a truth table of the drive circuit.

Fig. 10 is a timing chart showing an example of the operation of the negative voltage supply device.

Fig. 11 is a block diagram showing a structural example of the negative voltage supply device.

Fig. 12 is a circuit diagram showing a configuration example of the negative voltage holding circuit.

Fig. 13A and 13B are circuit diagrams showing a configuration example of the negative voltage holding circuit.

Fig. 14A is a block diagram showing a configuration example of the memory device, and fig. 14B is a circuit diagram showing a configuration example of the memory cell.

Fig. 15A to 15F are circuit diagrams showing a structural example of a memory cell.

Fig. 16A is a circuit diagram showing a configuration example of a memory cell, and fig. 16B is a timing chart showing an operation example of the memory cell.

Fig. 17A is a circuit diagram showing a configuration example of a memory cell, and fig. 17B is a timing chart showing an operation example of the memory cell.

Fig. 18 is a block diagram showing a structural example of the microcontroller unit.

Fig. 19 is a circuit diagram showing a configuration example of the flip-flop.

Fig. 20 is a block diagram showing a configuration example of the FPGA.

Fig. 21A is a circuit diagram showing a configuration example of the wiring switch, and fig. 21B is a circuit diagram showing a configuration example of the configuration memory.

Fig. 22A is a block diagram showing a configuration example of the image pickup apparatus, and fig. 22B is a circuit diagram showing a configuration example of the pixel.

Fig. 23A and 23B are perspective views of the electronic component.

Fig. 24A to 24D are diagrams illustrating a configuration example of an electronic apparatus.

Fig. 25 is a sectional view showing an example of a laminated structure of a circuit portion of an electronic component.

Fig. 26A and 26B are sectional views showing a structural example of the OS transistor.

Detailed Description

The following describes embodiments of the present invention. Note that one embodiment of the present invention is not limited to the following description. Those skilled in the art will readily appreciate that the invention may be modified in numerous forms and details without departing from the spirit and scope thereof. Therefore, one embodiment of the present invention should not be construed as being limited to only the contents of the embodiments shown below.

The embodiments shown below may be combined as appropriate. When a plurality of configuration examples (including a manufacturing method example, an operation method example, and the like) are shown in one embodiment, the plurality of configuration examples may be appropriately combined, or may be appropriately combined with one or more configuration examples described in other embodiments.

In the present specification and the like, ordinal numbers such as "first", "second", and "third" are attached to avoid confusion of constituent elements, and the ordinal numbers do not limit the number of the constituent elements or the order thereof.

The same elements, elements having the same function, elements formed using the same material, elements formed simultaneously, and the like in the drawings are denoted by the same reference numerals, and overlapping description may be omitted.

When it is necessary to distinguish a plurality of components indicated by the same reference numeral, the reference numeral may be denoted by "_ 1", "_ 2", "[ n ]", "[ m, n ]", or the like.

In this specification, for example, the power supply voltage VDD is sometimes simply referred to as "voltage VDD" or "VDD". The same applies to other constituent elements (for example, signals, voltages, circuits, elements, electrodes, and wirings).

In the drawings, the size, the thickness of layers, regions, and the like may be exaggerated for clarity. Accordingly, the size, thickness of layers, or area is not necessarily limited to the dimensions shown. The drawings are schematic views showing ideal examples, so that the embodiments of the present invention are not limited to the shapes or numerical values shown in the drawings. For example, non-uniformities in signal, voltage, or current due to noise or timing skew may be included.

In the present specification, for convenience, positional relationships of components will be described with reference to drawings by using terms such as "upper", "lower", and the like to indicate arrangement. In addition, the positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words used in the present specification are not limited, and the description thereof will be appropriately made depending on the case.

The transistor includes three terminals, i.e., a gate terminal, a source terminal, and a drain terminal. The gate is used as a control terminal for controlling the conduction state of the transistor. One of the two input-output terminals is used as a source and the other is used as a drain according to the type of transistor or the potential level supplied to each terminal. Therefore, in this specification and the like, "source" and "drain" may be interchanged with each other. In this specification and the like, two terminals other than the gate are sometimes referred to as a first terminal and a second terminal.

The node may be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, or the like depending on a circuit structure, a device structure, or the like. In addition, a terminal, a wiring, or the like may be referred to as a node.

In this specification and the like, "film" and "layer" may be interchanged with each other according to the situation or condition. For example, the "conductive layer" may be sometimes changed to a "conductive film". For example, the "insulating film" may be sometimes replaced with an "insulating layer".

In this specification and the like, a semiconductor device refers to a device utilizing semiconductor characteristics, and means a circuit including a semiconductor element (for example, a transistor or a diode), a device including the circuit, and the like. A semiconductor device also means all devices that can operate by utilizing semiconductor characteristics. For example, an integrated circuit and a chip including the integrated circuit are examples of a semiconductor device. In addition, a memory device, a display device, a light-emitting device, a lighting device, an electronic device, or the like may be a semiconductor device itself or include a semiconductor device.

[ embodiment 1]

In this embodiment, a comparison circuit capable of directly inputting a negative voltage to be compared and a semiconductor device including the comparison circuit will be described.

Comparison Circuit

Here, a configuration example of a comparison circuit using a differential amplification circuit is explained.

Fig. 1A shows an example of a comparison circuit. The comparison circuit 10 shown in fig. 1A includes terminals INN, INP, OCM. The terminals INN, INP, OCM are an inverting input terminal, a non-inverting input terminal, and an output terminal, respectively.

The voltages Vdda and Vssa are input to the comparison circuit 10. The voltage Vdda is a high-side power supply voltage. The voltage Vssa is a low-side power supply voltage, and is, for example, 0V (GND: ground voltage).

The comparison circuit 10 has a function of comparing the negative voltage Vnin with the negative reference voltage Vnref and outputting a voltage Vcmp corresponding to the comparison result from the terminal OCM. The negative voltage Vnin is input to the terminal INP. The terminal INN is inputted with the positive reference voltage Vpref instead of the negative reference voltage Vnref. The positive reference voltage Vpref corresponds to the negative reference voltage Vnref converted into a positive voltage. The value of the positive reference voltage Vpref is set in such a manner that the comparison circuit 10 can perform the above-described comparison.

Fig. 1B shows an example of the circuit configuration of the comparison circuit 10. The comparison circuit 10 is constituted by a differential circuit, and includes a differential pair 14, a current source 17, and a load circuit 18.

The differential pair 14 includes transistors MO11, MO 12. Both transistors MO11, MO12 are OS transistors comprising a back gate. The back gate of the transistor MO11 is electrically connected to the terminal INP, and the gate is input with the voltage Vdda. The gate of the transistor MO12 is electrically connected to the terminal INN, and the back gate is supplied with the input voltage Vssa.

Here, a connection node of the transistor MO11 and the load circuit 18 is referred to as a node X11, a connection node of the transistor MO12 and the load circuit 18 is referred to as a node X12, and a connection node of the transistor MO11 and the transistor MO12 is referred to as a node X13. The current source 17 supplies a current Iss to the node X13. The load circuit 18 supplies loads Rd1, Rd2 to nodes X11, X12, respectively.

Note that, in the drawings, n-channel transistors including a back gate are OS transistors, and p-channel transistors and n-channel transistors without a back gate are Si transistors, unless otherwise specified.

The voltages at nodes X12, X11 depend on the difference between the drain current (Imo1) of transistor MO11 and the drain current (Imo2) of transistor MO 12. In the example of FIG. 1B, where terminal OCM is electrically connected to node X12, voltage Vcmp is high ("H") at Imo1> Imo2 and low ("L") at Imo1< Imo 2.

(setting example of Positive reference Voltage Vpref)

The difference between current Imo1 and current Imo2 flowing through differential pair 14 may be scaled to the voltage difference between terminal INP and terminal INN. Therefore, the positive reference voltage Vpref can be set according to the voltage difference. Specifically, when the voltage at the terminal INP, the gate voltage of the transistor MO11, and the back gate voltage of the transistor MO12 are Vnref, Vdda, and Vssa, respectively, the voltage difference between the terminal INP and the terminal INN when the difference between Imo1 and Imo2 is 0 ampere is estimated. The value of the positive reference voltage Vpref may be set according to the estimated voltage difference.

By setting the positive reference voltage Vpref in this manner, the terminal OCM outputs the voltage Vcmp of "H" when Vnin > Vnref, and outputs the voltage Vcmp of "L" when Vnin < Vnref.

The operating principle of the comparison circuit 10 is explained with reference to fig. 1C. Fig. 1C schematically shows the drain current-gate voltage (Id-Vg) characteristic of the transistor MO 11. The curve 9A is an Id-Vg curve when Vnin > Vnref. Curve 9B is the Id-Vg curve for Vnin < Vnref.

Since Imo1> Imo2 indicates that Vnin > Vnref, voltage Vcmp is "H".

The decrease in the back gate voltage shifts Vt of the transistor MO11 to the positive side. That is, the decrease in the negative voltage Vnin decreases the current Imo 1. When Vnin < Vnref, Imo1< Imo2 indicates that voltage Vcmp is "L".

Next, a modified example of the differential pair will be described. In the example of fig. 1A, the voltages Vdda, Vssa are used as the bias voltages of the differential pair 14, but the bias voltages are not limited to them. By using the voltages Vdda and Vssa as the bias voltages of the differential pair 14, the kinds of voltages used in the comparison circuit 10 can be reduced.

Alternatively, the back gate of the transistor MO12 may be electrically connected to the terminal INP, and the gate may be biased by a bias voltage such as the input voltage Vssa.

The comparison circuit 11 shown in fig. 2 includes a differential pair 15 instead of the differential pair 14. Differential pair 15 includes transistors MO13, MO 14. Terminal INN is electrically connected to the gate of transistor MO 13. Terminal INP is electrically connected to the gate of transistor MO 14. The back gate of the transistor MO13 is input with a bias voltage (here, Vdda). The back gate of the transistor MO14 is input with a bias voltage (here, Vssa).

The back gate of transistor MO14 may also be electrically connected to terminal INP, with the gate being input with a bias voltage (e.g., Vssa).

The comparator circuit 10 does not have a complicated circuit configuration, and can directly input a negative voltage to be compared. By replacing the negative reference voltage with the positive reference voltage, the comparator circuit 10 is inputted with only 0V or a positive voltage in addition to the negative voltage (Vnin) to be compared, and therefore, the operation of the comparator circuit 10 can be stabilized. The same applies to the comparator circuit 11.

< comparison circuits 20 to 25>

Next, a specific example of the circuit configuration of the comparison circuit is explained.

The comparison circuit 20 shown in fig. 3A includes terminals INN, INP, OCM, a differential input circuit 30, and an output circuit 40.

The differential input circuit 30 is a one-stage differential amplification circuit, and includes a differential pair 34 and transistors MN1, MP1, MP 2.

The differential pair 34 has the same circuit configuration as the differential pair 14 and includes transistors MO1, MO 2. The connection node of the transistors MO1 and MP1 is referred to as node X1. The connection node of the transistors MO2 and MP2 is referred to as node X2.

Terminal INP is electrically connected to the back gate of transistor MO 1. Terminal INN is electrically connected to the gate of transistor MO 2. The gate of the transistor MO1 is inputted with the voltage Vdda. The back gate of the transistor MO2 is inputted with the voltage Vssa.

Transistor MN1 is used as a current source. The gate of the transistor MN1 is input with a voltage Vb 1. The voltage Vb1 is a positive voltage.

The current mirror circuit is composed of transistors MP1 and MP 2. A current mirror circuit is used as the load circuit. The load circuit may be formed of diode-connected transistors MP1 and MP 2. Alternatively, two resistors may be provided instead of the transistors MP1, MP 2.

Output circuit 40 is electrically connected to node X2. The output circuit 40 is constituted by a two-stage CMOS inverter circuit. The CMOS inverter circuit is constituted by Si transistors.

The comparison circuit 21 shown in fig. 3B is a modification of the comparison circuit 20. The output circuit 41 is constituted by a one-stage CMOS inverter circuit. The input node of the CMOS inverter circuit is electrically connected to the node X1.

The comparator circuit 22 shown in fig. 4A is a modification of the comparator circuit 20. The output circuit 42 of the comparison circuit 22 is constituted by a two-stage source follower circuit. The comparison circuit 23 shown in fig. 4B is a modification of the comparison circuit 22. The output circuit 43 of the comparison circuit 23 is constituted by a one-stage source follower circuit. The input node of the source follower circuit is electrically connected to the node X1.

The comparator circuit 24 shown in fig. 4C is a modification of the comparator circuit 21, and includes a differential input circuit 31. The differential input circuit 31 is a modification of the differential input circuit 30, and includes a transistor MO3 instead of the transistor MN 1. The gate of the transistor MO3 is input with a voltage Vb1, and the back gate is electrically connected to the gate. Note that the back gate of the transistor MO3 may also be input with a bias voltage (e.g., voltage Vssa), and the back gate may also be electrically connected to the drain.

The comparator circuits 20 to 24 output the voltage Vcmp of "H" when Vnin > Vnref, and output the voltage Vcmp of "L" when Vnin < Vnref. The relationship between the magnitude relationship between Vnin and Vnref and the level of the voltage Vcmp is appropriately changed according to the circuit configuration of the output circuit or the like.

In the comparison circuit 20, the gate of the transistor MO1 may be electrically connected to the terminal INP, and the back gate of the transistor MO1 may be input with a bias voltage (e.g., Vdda). The back gate of transistor MO2 may also be electrically connected to terminal INN, and the gate of transistor MO2 may be input with a bias voltage (e.g., Vssa). The same applies to the comparison circuits 21 to 24.

Dynamic comparison circuit

A configuration example of the dynamic comparison circuit is explained with reference to fig. 5. The comparison circuit 25 shown in fig. 5 includes a differential input circuit 32, an output circuit 45, terminals INN, INP, OCM, and a terminal OCMB. The comparator circuit 25 receives the voltages Vdda and Vssa and a clock signal CLK (hereinafter, referred to as a signal CLK).

The comparison circuit 25 compares the negative voltage Vnin with a negative reference voltage Vnref and outputs a voltage Vcmp and a voltage VcmpB corresponding to the comparison result from the terminals OCM and OCMB. The negative voltage Vnin and the positive reference voltage Vpref are input to the terminals INN and INP, respectively. The positive reference voltage Vpref is set in the same manner as the comparator circuit 10 described above.

Currents Imo5, Imo6 in the drawing represent drain currents of transistors MO5, MO6, respectively.

In the comparison circuit 25, a negative voltage (Vnin) to be compared may be input to the terminal INN, and a voltage of 0V or less may be used.

The differential input circuit 32 includes transistors MO5, MO6, transistors MN5, MN6, MN7, MP5, MP6, MP7, MP 8.

The differential pair of the differential input circuit 32 has the same circuit configuration as the differential pair 34, and includes transistors MO5, MO 6. Transistor MN7 is used as a current source. The gate of the transistor MN7 is input with the signal CLK.

Here, a connection node of the transistors MN5 and MP5 is referred to as a node X5. The connection node of the transistors MN6 and MP6 is referred to as node X6. The latch circuit is composed of transistors MN5, MP5, MN6, and MP 6. The latch circuit sets the voltage levels of nodes X5 and X6 according to the magnitude relationship of currents Imo5 and Imo 6.

The transistors MP7, MP8 are reset transistors. The on/off of the transistors MP7, MP8 is controlled by the signal CLK. When the transistors MP7, MP8 are turned on, the voltages at the nodes X5, X6 are fixed to Vdda ("H").

The output circuit 45 includes inverter circuits 38, 39. The input terminals of the inverter circuits 38 and 39 are electrically connected to the nodes X5 and X6, respectively. Output terminals of the inverter circuits 38 and 39 are electrically connected to the terminals OCM and OCMB, respectively.

During the period in which the signal CLK is "L", the comparator circuit 25 precharges. Since the transistors MP7 and MP8 are turned on, the nodes X5 and X6 are fixed to "H" and the terminals OCM and OCMB are fixed to "L".

While the signal CLK is "H", the comparison circuit 25 evaluates. When a difference is generated between the currents Imo5 and Imo6, a difference is generated between the driving capabilities of the two inverter circuits included in the latch circuit, thereby generating a voltage difference between the nodes X5 and X6.

When Vnin > Vnref, current Imo5> current Imo 6. Therefore, the voltage at the node X5 is lower than the voltage at the node X6, and the terminal OCM and the terminal OCMB are "H" and "L", respectively. On the other hand, when Vnin < Vnref, current Imo5< current Imo 6. Therefore, the voltage at the node X5 is higher than the voltage at the node X6, and the terminal OCM and the terminal OCMB become "L" and "H", respectively.

Since the differential pair in the comparison circuit 20 shown in fig. 3A is formed of two OS transistors including a back gate, the voltage Vssa may be a ground voltage. Therefore, it is not necessary to input a negative voltage to the source of the transistor MN 1.

When a negative voltage is input to the source of the n-channel Si transistor, a forward bias voltage is applied to a parasitic diode (pn junction diode) between the p-type well and the source region. Therefore, a large current reverse flow from the substrate to the source region occurs. In order to prevent a large current from flowing backward, a triple well structure in which an n-channel transistor is surrounded by an n-type well is generally employed (see, for example, fig. 3b and 6 of patent document 3). However, the circuit area increases due to the n-channel transistor of the triple well structure.

Since the comparator circuit 20 can be formed without using an n-channel Si transistor having a triple-well structure, the circuit area can be reduced. The same applies to the comparison circuits 21 to 25.

As described above, by employing a differential pair formed of two n-channel transistors including a back gate, the comparison circuit of this embodiment can be supplied with a negative voltage to be compared, can use a reference voltage obtained by converting a negative reference voltage into a positive voltage, and can set a low-level-side power supply voltage to 0V (ground voltage) without having a complicated circuit configuration. Therefore, the comparison circuit of the present embodiment can realize highly accurate comparison and stable operation of the negative voltage and the negative reference voltage.

[ embodiment 2]

In this embodiment, a semiconductor device including the comparator circuit described in embodiment 1 will be described. As an example, a device for supplying a negative voltage to a semiconductor device is described.

Negative voltage supply device 100

Fig. 6 is a block diagram showing a structural example of the negative voltage supply device. The negative voltage supply device 100 shown in fig. 6 generates a negative voltage inside thereof and outputs the generated negative voltage to a plurality of power supply terminals. The negative voltage supply apparatus 100 includes a control circuit 111, a charge pump circuit 112, a bias voltage generation circuit 114, an output voltage regulator 120, and a plurality of terminals OB. The terminal OB is an output terminal for negative voltage. In the present example, the number of the terminals OB is 4, but is not limited thereto.

To distinguish the 4 terminals OB, reference numerals [1] to [4] are used. When any one of the plurality of terminals OB needs to be designated, the one terminal OB is described as a terminal OB [1], for example. "terminal OB" refers to an arbitrary terminal OB. The same applies to other constituent elements.

The negative voltage supply device 100 is inputted with voltages Vdda, Vddd, GND, a positive reference voltage Vpref, a clock signal CK1, and a signal WAKE. The voltage GND is 0V (ground voltage), and is used as the low-level-side power supply voltage of the negative voltage supply device 100. The voltage Vddd is a high-side power supply voltage and is smaller than the voltage Vdda. The voltage Vddd is used in the control circuit 111.

< control Circuit 111>

The signal WAKE is used as an enable signal of the negative voltage supply apparatus 100. The control circuit 111 controls the charge pump circuit 112 and the output voltage regulator 120 according to the signal WAKE. Here, the control circuit 111 is used as a clock gating buffer. The control circuit 111 generates a gated clock signal GCK1 (hereinafter, referred to as a clock signal GCK1) from the clock signal CK1 in accordance with the signal WAKE. The low-level voltage and the high-level voltage of the clock signal CK1 are GND and Vdda, respectively.

The clock signal GCK1 is input to the charge pump circuit 112 and the output voltage regulator 120.

< Charge Pump Circuit 112>

The charge pump circuit 112 is used as a negative voltage generation circuit. Fig. 7 shows an example of the circuit configuration of the charge pump circuit 112, which is a four-stage step-down type charge pump circuit. The charge pump circuit 112 includes terminals IN _ cp, OUT _ cp, 2 inverter circuits, 4 OS transistors, and 4 capacitors. When the clock signal GCK1 is IN an active state, the charge pump circuit 112 generates a negative voltage Vcp from the voltage GND input to the terminal IN _ cp and outputs the negative voltage Vcp from the terminal OUT _ cp.

IN the example of fig. 7, 4 transistors are provided IN the charge transfer path between the terminal IN _ cp and the terminal OUT _ cp, but the number of transistors is not limited to this. Further, the transistor provided in the charge transfer path is not limited to the OS transistor. Fig. 8A to 8C show other examples of the step-down type charge pump circuit that can be used as the charge pump circuit 112.

The charge pump circuit 113A of fig. 8A includes 2 inverter circuits, 4 n-channel Si transistors, and 4 capacitors. The charge pump circuit 113B of fig. 8B includes 3 n-channel Si transistors and 1 OS transistor. The charge pump circuit 113C of fig. 8C includes 2 inverter circuits, 4 p-channel Si transistors, and 4 capacitors.

< bias voltage generating circuit 114>

The bias voltage generating circuit 114 generates a voltage Vb 1. The voltage Vb1 is input to the output voltage regulator 120. Further, the voltage Vb1 may be inputted from the outside without providing the bias voltage generation circuit 114.

< output Voltage regulator 120>

The output voltage regulator 120 is provided to stably output a negative voltage from each terminal OB. The output voltage regulator 120 includes 4 negative voltage holding circuits 122. The negative voltage holding circuit 122 includes a charge pump circuit 123, a drive circuit 127, and a monitor circuit 128. The negative voltage holding circuit 122[ j ] (j is an integer of 1 to 4) controls the output voltage of the terminal OB [ j ]. Fig. 9A shows a circuit configuration example of the negative voltage holding circuit 122.

< negative voltage holding Circuit 122>

The charge pump circuit 123 includes transistors MO21, MO22 and capacitors C21, C22. The charge pump circuit 123 steps down the voltage Vcp to generate a voltage Vob. The voltage Vob is held by the capacitor C22. The voltage Vob is output from the terminal OB.

The capacitance of the capacitor C22 is preferably greater than the capacitance of the capacitor C21. For example, the capacitance of the capacitor C22 is 2 to 10 times the capacitance of the capacitor C22. The capacitor C21 may be formed of a parasitic capacitance of the transistor MO21, a parasitic capacitance between the transistor MO21 and a wiring, or the like, according to a capacitance required for the capacitor C21.

Since the bandgap of the metal oxide semiconductor is 2.5eV or more, the off-state current (off-state current) of the OS transistor is extremely small. For example, the off-state current with a voltage between the source and drain of 3.5V and a channel width of 1 μm at room temperature (25 deg.C) may be less than 1X 10^-20A. Less than 1X 10^-22A. Or less than 1X 10^-24A. That is, the on/off ratio of the drain current may be 20 bits or more and 150 bits or less.

A metal oxide semiconductor has a large energy gap, is not easily excited by electrons, and has a large effective mass of holes. Therefore, avalanche breakdown (avalanche breakdown) or the like is less likely to occur in the OS transistor than in the Si transistor. Since hot carrier deterioration or the like due to avalanche breakdown is suppressed, the insulation withstand voltage between the source and the drain of the OS transistor is high.

As examples of the metal oxide which can be used for the channel forming region, there are Zn oxide, Zn-Sn oxide, Ga-Sn oxide, In-Ga oxide, In-Zn oxide, In-M-Zn oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf). Further, the oxide containing indium and zinc may also contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

The gate of the transistor MO22 is applied with a negative voltage, so the off-current of the transistor MO22 can be effectively reduced by electrically connecting the back gate of the transistor MO22 to the gate. This is because the threshold voltage of the transistor MO22 shifts to the positive side by electrically connecting the back gate and the gate of the transistor MO 22. Here, the off current is a drain current when a gate-source voltage of the transistor is 0V.

Therefore, the structure in which the transistors MO21, MO22 are OS transistors including a back gate contributes to stably supplying a negative voltage for a long time.

Since the OS transistor can be stacked on the Si transistor, the transistors MO21, MO22 of the OS transistor contribute to miniaturization of the negative voltage supply device 100.

The monitoring circuit 128 monitors the voltage Vob of the terminal OB. The monitor circuit 128 is constituted by a comparator circuit using a differential amplifier circuit. The comparison circuit shown in fig. 9A is a modification of the comparison circuit 20 (see fig. 3A). Here, the output circuit includes 1 CMOS inverter circuit.

The terminal INP is electrically connected to the terminal OB. The terminal INN is input with a positive reference voltage Vpref. The terminal OCM is electrically connected to an input terminal of the drive circuit 127. The signal MON is the output of the terminal OCM.

The output voltage of the negative voltage supply device 100 is set to the negative voltage VBG. The monitoring circuit 128 compares the voltage Vob with the negative voltage VBG as a reference. The value of the positive reference voltage Vpref is set in such a way that the monitoring circuit 128 is able to make this comparison.

Here, the monitoring circuit 128 monitors the drop of the voltage Vob. When the voltage Vob is higher than the negative voltage VBG, the monitor circuit 128 outputs the signal MON of "L". When the voltage Vob is lower than the negative voltage VBG, the monitor circuit 128 outputs the signal MON of "H".

A plurality of positive reference voltages may also be used depending on the deviation of characteristics (e.g., bias voltages) among the plurality of monitor circuits 128. For example, two positive reference voltages Vpref1, Vpref2 of different values are input to the negative voltage supply device 100. The positive reference voltage Vpref1 is input to the monitor circuits 128[1], 128[2 ]. The positive reference voltage Vpref2 is input to the monitor circuits 128[3], 128[4 ].

The driver circuit 127 performs a logical operation of the signal MON and the clock signal GCK1 to generate a clock signal GCK2 for driving the charge pump circuit 123. The drive circuit 127 has the following circuit configuration: when the signal MON is "L", the clock signal GCK2 is active; during other periods, the clock signal GCK2 is inactive. Fig. 9B shows an example of a truth table of the drive circuit 127.

Working examples

An operation example of the negative voltage supply device 100 is explained with reference to fig. 10. Fig. 10 is a timing chart showing an example of the operation of the negative voltage supply device 100. t0, etc. represents the time. Here, at time t0, the output voltage Vcp of the charge pump circuit 112, and the voltages Vob [1] to Vob [4] of the terminals OB [1] to OB [4] are 0v (gnd).

The period Tc1 in fig. 10 is a 1-cycle period of the operation of the negative voltage supply device 100. The signal WAKE is used as a chip enable signal of the negative voltage supply apparatus 100. During the period when the signal WAKE is "H", the negative voltage supply apparatus 100 is in an active state.

While the signal WAKE is "H", the charge pump circuit 112 performs a step-down operation because the clock signal GCK1 output from the control circuit 111 is in an active state. Here, the output voltage Vcp of the charge pump circuit 112 is saturated at the negative voltage VBG between time t0 and time t 1.

At time t0, since the voltage Vob [1] is GND, the signal MON [1] of "L" is output from the monitoring circuit 128[1 ]. The signals MON 2 to MON 4 are also "L". Thus, the driving circuits 127[1] to 127[4] output the active state clock signals GCK2[1] to GCK2[4], respectively.

Since the charge pump circuit 123[1] performs the step-down operation, the voltage Vob [1] falls. The charge pump circuits 123[2] to 123[4] also perform a step-down operation.

Deviations in the electrical characteristics (e.g., threshold voltages) of the transistors MO21, MO22 between the charge pump circuits 123[1] to 123[4] cause differences in current drive capability between the charge pump circuits 123[1] to 123[4 ]. Therefore, the timing at which the terminals OB [1] to OB [4] reach the negative voltage VBG is different. In the present embodiment, the monitor circuits 128[1] to 128[4] independently monitor the voltages of the terminals OB [1] to OB [4], thereby making it possible to reduce the variation in the reached voltages (residual voltages) of the terminals OB [1] to OB [4] and make these voltages substantially equal to the negative voltage VBG.

For example, the negative voltage holding circuit 122[1] is explained. When detecting that the voltage Vob [1] reaches the negative voltage VBG, the monitor circuit 128[1] outputs a signal MON [1] of "H" to the drive circuit 127[1 ]. The driver circuit 127[1] fixes the clock signal GCK2 to "H" in response to the input of the signal MON [1] of "H". As a result, the charge pump circuit 123[1] stops the step-down operation, and the voltage Vob [1] is set to substantially the negative voltage VBG.

Since the transistor MO22[1] is an OS transistor with a very small off-state current, the capacitor C22[1] can hold the negative voltage VBG for a long time even if the clock signal GCK2 is in an inactive state.

The negative voltage holding circuits 122[2] to 122[4] also operate in the same manner, and the voltages Vob [2] to Vob [4] are set to be substantially the negative voltage VBG.

Between time t1 and time t2, the negative voltage supply apparatus 100 is in an inactive state because the signal WAKE is "L". Here, the standby power of the negative voltage supply device 100 is reduced by performing clock gating so that the clock signal CK1 is fixed to "L".

Since the negative voltage holding circuit 122 has excellent holding characteristics, the period during which the signal WAKE is "L" can be extended. Therefore, during this period, power gating can be performed to stop the supply of the power supply voltages (Vddd, Vdda) to the negative voltage supply device 100. By performing power gating, the power consumption of the negative voltage supply apparatus 100 can be further reduced.

Fig. 10 shows an example of power gating during the period in which the signal WAKE is "L". At time t2, the supply of the voltages Vddd, Vdda starts, the signal WAKE becomes "H", and the clock signal CK1 is in an active state. The operation of the negative voltage supply device 100 from time t2 to time t3 is the same as that from time t0 to time t 1. In FIG. 10, the voltages Vob [1] to Vob [4] at times t1 to t3 do not exceed the negative voltage VBG. When the monitor circuits 128[1] to 128[4] become active, the terminals OCM [1] to OCM [4] change from "L" to "H". Thus, the charge pump circuits 123[1] to 123[4] are in a standby state.

Since the negative voltage holding circuit 122 has a function of controlling the step-down of the terminal OB and a function of holding the voltage of the terminal OB, the set negative voltage can be stably output from the terminal OB for a long time.

Negative voltage supply apparatus 101

Other configuration examples of the negative voltage supply device are explained with reference to fig. 11, 12, 13A, and 13B. In the present configuration example, a dynamic comparison circuit is used for the negative voltage monitoring circuit.

The negative voltage supply device 101 shown in fig. 11 includes a control circuit 141, a charge pump circuit 142, a frequency dividing circuit 143, an output voltage regulator 150, and 4 terminals OB. The output voltage regulator 150 includes 4 negative voltage holding circuits 152.

The negative voltage supply device 101 is inputted with voltages Vdda, Vddd, GND, a positive reference voltage Vpref, a clock signal CK1, and a signal WAKE.

The control circuit 141 has the same function as the control circuit 111. The control circuit 141 generates the clock signal GCK1 according to the signal WAKE.

The charge pump circuit 142 has the same circuit configuration as the charge pump circuit 112 (see fig. 7). The charge pump circuit 142 performs a step-down operation in accordance with the clock signal GCK1 and outputs a voltage Vcp.

The frequency divider circuit 143 divides the clock signal GCK1 to generate a clock signal GCK 3. The clock signal GCK3 is input to the 4 negative voltage holding circuits 152.

Fig. 12 shows a circuit configuration example of the negative voltage holding circuit 152. The negative voltage holding circuit 152 includes a charge pump circuit 153, a drive circuit 154, and a monitor circuit 155.

The charge pump circuit 153 has the same circuit structure as the charge pump circuit 123, and includes transistors MO25, MO26, and capacitors C25, C26.

The driver circuit 154 has the same function as the driver circuit 127 (see fig. 9B). The driver circuit 154 performs a logical operation of the signal MON and the clock signal GCK3, and generates a clock signal GCK4 for driving the charge pump circuit 153. When the signal MON is "L", the clock signal GCK4 is in an active state. When the signal MON is not "L", the clock signal GCK4 is in an inactive state.

The monitor circuit 155 includes the comparator circuit 25 (see fig. 5). The monitor circuit 155 is input with a clock signal GCK 3. The terminal INP is electrically connected to the terminal OB, and the positive reference voltage Vpref is input to the terminal INN. The terminal OCMB is electrically connected to an input terminal of the drive circuit 154.

Here, the monitoring circuit 155 monitors the drop of the voltage Vob. The monitor circuit 155 outputs the signal MON of "L" when the voltage Vob is greater than the negative voltage VBG. The monitor circuit 155 outputs the signal MON of "H" when the voltage Vob is less than the negative voltage VBG.

The negative voltage supply device 101 performs the same operation as the negative voltage supply device 100 (see fig. 10). The negative voltage supply device 101 can reduce power consumption (i.e., dynamic power consumption) during the period in which the signal WAKE is "H" as compared to the negative voltage supply device 100.

During the period when the signal WAKE is "H", a current flows through the monitoring circuit 128 of the negative voltage supply apparatus 100 regardless of the clock signal GCK 2. In contrast, while the clock signal GCK3 is "L", the output OCMB of the monitor circuit 155 is fixed to "L". Therefore, the current consumption of the monitor circuit 155 can be made lower than that of the monitor circuit 128.

By providing the monitor circuit 155 for each terminal OB, a negative voltage can be stably output from each terminal OB. However, as the number of terminals OB increases, the influence of the current consumption on the monitor circuit 155 also increases. Therefore, the reduction of the current consumption of the monitoring circuit 155 is effective for reducing the dynamic power consumption of the negative voltage supply device 101 as a whole.

To reduce dynamic power consumption, the clock signal is set to a low speed. If the clock signal GCK1 is set to low speed, it takes a long time until the voltage Vcp reaches the negative voltage VBG. That is, the time for the signal WAKE to be "H" becomes long. Therefore, by setting only the clock signal GCK3 to a low speed, the dynamic power consumption of the negative voltage supply device 101 can be efficiently reduced.

< other construction examples of monitoring Circuit >

Since the monitor circuit 155 is configured by a dynamic comparator circuit, when the same amount of current flows through the 2 OS transistors of the differential pair, the signal MON at the terminal OCM may become unstable. Next, a countermeasure for stabilizing the signal MON will be described with reference to fig. 13A and 13B.

Fig. 13A shows an example of switching the positive reference voltage of the dynamic comparison circuit according to the signal MON. Fig. 13B shows an example of controlling the power supply of the differential input circuit of the dynamic comparison circuit in accordance with the signal MON.

(monitor circuit 161)

The monitor circuit 161 shown in fig. 13A includes a comparison circuit 171, a latch circuit 173, and a selection circuit 175.

The comparator 171 is constituted by the comparator 25. The differential pair of the comparator circuit 171 is formed by transistors MO7 and MO 8. Currents Imo7, Imo8 are the drain currents of transistors MO7, MO8, respectively.

In synchronization with the rise of the clock signal GCK3, the data of the latch circuit 173 is updated by the output of the comparison circuit 171. The output signal of the latch circuit 173 is the signal MON. For example, the latch circuit 173 may include a delay flip-flop (DFF) circuit.

The selection circuit 175 selects a voltage input to the terminal INN of the comparison circuit 171 from the positive reference voltage Vpref and the voltage GND. The selection circuit 175 is inputted with the signal MON and the signal WAKE. The signal WAKE is used as a RESET signal (RESET) of the selection circuit 175. In addition, a signal other than the signal WAKE may be used as the reset signal.

An example of the operation of the monitor circuit 161 is illustrated. When the signal WAKE changes from "L" to "H", the selection circuit 175 is reset to supply the positive reference voltage Vpref to the terminal INN. When the clock signal GCK3 is in an active state, the comparison circuit 171 compares the voltage Vob of the terminal OB with the negative voltage VBG. When the voltage Vob is higher than the negative voltage VBG, the signal MON is "L". When the signal MON is "L", the selection circuit 175 inputs the positive reference voltage Vpref to the terminal INN.

When the voltage Vob becomes lower than the negative voltage VBG and the clock signal GCK3 is "H", a signal of "H" is output from the terminal OCMB. At this time, current Imo7 may become equal to current Imo8, and thus the output of terminal OCMB may oscillate. If the selection circuit 175 detects a rise of the signal MON a prescribed number of times (1 time or more), the terminal INN is supplied with the voltage GND. Then, the current Imo8 decreases, a difference is generated between the current Imo7 and the current Imo8, and thereby the output of the terminal OCMB is stabilized. When the clock signal GCK3 is "H", the terminal OCMB can stably output a signal of "H".

In the present example, the terminal INN is inputted with the voltage GND, but there is no limitation on the signal as long as there is a difference between the currents Imo7 and Imo8 when the signal MON is "H". A positive voltage lower than the voltage Vpref may be input to the terminal INN. The use of the voltage GND does not increase the kind of voltage to be used.

(monitor circuit 162)

The monitor circuit 162 shown in fig. 13B includes a comparison circuit 172 and a selection circuit 177. The comparison circuit 172 is constituted by the comparison circuit 25. Similarly to the monitor circuit 161, the latch circuit 173 may be provided in the monitor circuit 162.

The selection circuit 177 controls the supply of the high-level-side power supply voltage to the differential input circuit 172A of the comparison circuit 172. The selection circuit 177 is inputted with signals MON and WAKE. The signal WAKE is used as a reset signal of the selection circuit 177. As the reset signal, a signal other than the signal WAKE may be used.

When the signal WAKE changes from "L" to "H", the selection circuit 177 is reset to supply the voltage Vdda to the differential input circuit 172A. When the clock signal GCK3 is in an active state, the comparison circuit 172 compares the voltage Vob of the terminal OB with the negative voltage VBG. If the selection circuit 177 detects a rise of the signal MON a predetermined number of times (1 time or more), the voltage GND is supplied to the differential input circuit 172A. As a result, the 2 inverter circuits of the differential input circuit 172A are in an inactive state, and therefore the output of the comparison circuit 172 does not oscillate.

The negative voltage supply device of the present embodiment is applied to a negative voltage power supply circuit of various semiconductor devices. Examples of a semiconductor device using the negative voltage supply device as a power supply circuit include various semiconductor devices (e.g., DRAM and image sensor) in which a substrate bias voltage is a negative voltage, a semiconductor device driven with a negative voltage (e.g., memory device such as flash memory), and a semiconductor device including an OS transistor including a back gate. A structure example of a semiconductor device including the present negative voltage supply device is described in embodiment 3.

[ embodiment 3]

Storage device

Here, as a semiconductor device using an OS transistor, a memory device in which a data holding portion includes an OS transistor will be described.

The memory device 200 shown in fig. 14A includes a negative voltage supply device 210, a control circuit 215, a memory cell array 220, and a peripheral circuit 221. The peripheral circuit 221 includes a row circuit 223, a column circuit 224, and an input-output circuit 225.

Memory cell array 220 includes memory cells 230, read word lines RWL, write word lines WWL, read bit lines RBL, write bit lines WBL, source lines SL, and wirings BGL. Read word line RWL and write word line WWL are sometimes referred to as word line RWL and word line WWL, respectively. Read bit line RBL and write bit line WBL are also sometimes referred to as bit line RBL and bit line WBL.

The control circuit 215 controls the entire memory device 200 to write data WDA and read data RDA. The control circuit 215 processes an instruction signal (e.g., a chip enable signal, a write enable signal) from the outside, and generates a control signal of the peripheral circuit 221.

The negative voltage supply device described in embodiment 2 is used as the negative voltage supply device 210. The negative voltage supply device 210 includes N (N is an integer of 2 or more) terminals OB [1] to OB [ N ]. Terminals OB [1] to OB [ N ] output a negative voltage Vbg 1. The memory cell array 220 is divided into N blocks. The wiring BGL of each block is electrically connected to the terminal OB.

The row circuit 223 has a function of selecting a row to be accessed. For example, row circuit 223 includes a row decoder and word line drivers. The column circuit 224 has a function of precharging the bit lines WBL and RBL, a function of writing data to the bit line WBL, a function of amplifying data on the bit line RBL, a function of reading data from the bit line RBL, and the like. The input/output circuit 225 has a function of holding write data, a function of holding read data, and the like.

The structure of the peripheral circuit 221 is appropriately changed depending on the structure of the memory cell array 220, a reading method, a writing method, and the like.

< storage Unit 230>

Fig. 14B shows a circuit configuration example of the memory cell 230. The memory cell 230 in this example is a 2 transistor type (2T) gain cell. The memory cell 230 includes transistors MW1, MR1 and capacitor CS 1. Transistors MW1 and MR1 are write transistor and read transistor, respectively. The back gates of transistors MW1 and MR1 are electrically connected to wiring BGL.

Since the readout transistor is an OS transistor, the memory cell 230 does not consume power when holding data. Therefore, the memory cell 230 is a low power consumption memory cell capable of holding data for a long time. The memory device 200 may be used as a nonvolatile memory device. The OS transistor and the capacitor may be stacked over the Si transistor. Accordingly, the memory cell array 220 can be stacked on the peripheral circuit 221, whereby the integration of the memory cell array 220 can be improved.

Other structure examples of the memory cell are explained with reference to fig. 15A to 15F.

< storage units 231 to 235>

The memory cell 231 shown in fig. 15A is a 3T type gain cell, which includes transistors MW2, MR2, MS2, and capacitor CS 2. Transistors MW2, MR2, MS2 are the write transistor, read transistor and select transistor, respectively. The back gates of transistors MW2, MR2, and MS2 are electrically connected to wiring BGL. Memory cell 231 is electrically connected to word lines RWL and WWL, bit lines RBL and WBL, capacitor line CDL, and power supply line PL 2. For example, a voltage GND (low-level power supply voltage) is input to the capacitor line CDL and the power supply line PL 2.

Fig. 15B and 15C show other configuration examples of the 2T-type gain cell. In the memory cell 232 shown in fig. 15B, an n-channel Si transistor is used as the readout transistor. In the memory cell 233 shown in fig. 15C, a p-channel Si transistor is used as a readout transistor.

Fig. 15D and 15E show other configuration examples of the 3T-type gain cell. In the memory cell 234 shown in fig. 15D, an n-channel Si transistor is used as a read transistor and a select transistor. In the memory cell 235 shown in fig. 15E, a p-channel Si transistor is used as a read transistor and a select transistor. In the example of fig. 15E, the power supply line PL2 is input with a voltage Vddd (high-level-side power supply voltage).

In the gain cell, a bit line serving as both the read bit line RBL and the write bit line WBL may be provided.

< storage Unit 236>

Fig. 15F shows an example of a 1T1C (capacitance) type memory cell. The memory cell 236 shown in fig. 15F is electrically connected to the word line WL, the bit line BL, the capacitor line CDL, and the wiring BGL. The memory cell 236 includes a transistor MW3 and a capacitor CS 3. The back gate of transistor MW3 is electrically connected to wiring BGL.

< storage cell 237>

The memory cell 237 shown in fig. 16A includes a memory cell 240 and a backup circuit 241. The memory cell 240 has the same circuit structure as a standard 6T-type SRAM cell.

The backup circuit 241 is a circuit for backing up data of the node Q, Qb included in the memory cell 240, and is constituted by 2 1T1C type cells. The nodes SN1, SN2 are holding nodes. The gain cell formed by transistor MW5 and capacitor CS5 backs up the data at node Q. The gain cell composed of the transistor MW6 and the capacitor CS6 backs up the data of the node Qb.

Since the transistors MW5 and MW6 are OS transistors, the memory cell 240 can be stacked on the backup circuit 241. Therefore, the area overhead of the memory cell 237 due to the additional provision of the backup circuit 241 can be reduced. The area overhead may be 0.

The memory cell 240 is electrically connected to power supply lines V _ VDM, V _ VSM, word lines WL, and bit line pairs (BL, BLB). The power supply lines V _ VDM, V _ VSM are power supply lines for Vddd, GND, respectively. Backup circuit 241 is electrically connected to wirings OGL and BGL and power supply line PL 3. Power supply line PL3 is input with voltage GND.

The memory cell 237 in the normal state operates as an SRAM cell. An example of the operation of the memory cell 237 is described with reference to fig. 16B. If the memory cell 237 is not accessed for more than a certain time, the supply of the voltages Vddd, GND to the power lines V _ VDM, V _ VSM is stopped. Before the supply of the voltage Vddd is stopped, the data of the node Q, Qb is written to the backup circuit 241. In fig. 16B, t1, t2, and the like represent time.

(general work)

Before time t1, memory cell 237 is in a normal operating state (write state or read state). The memory cell 237 operates in the same manner as a single-port SRAM. At time t1, nodes Q, Qb, SN1, and SN2 are "H", "L", and "H", respectively.

(backup)

At t1, the wiring OGL becomes "H", whereby the backup operation is started, and the transistors MW5, MW6 are turned on. The voltage at node SN1 rises from GND to Vddd. The voltage at node SN2 drops from Vddd to GND. At t2, the wiring OGL becomes "L", and the backup operation ends. The node SN1 and the node SN2 are written with the data of the node Q and the data of the node Qb of t1, respectively.

(Power door control)

At t2, power gating begins. The voltage of the power supply line V _ VDM changes from Vddd to GND. The voltage difference between the power line V _ VDM and the power line V _ VSM becomes small, and thus the memory cell 240 becomes inactive. Although the data in the memory unit 240 disappears, the backup circuit 241 continues to hold the data. During power gating, the bit lines BL, BLB are in a floating state.

(recovery)

The recovery operation is an operation of recovering data in the memory unit 240 using data held in the backup circuit 241. In the recovery operation, the memory cell 240 is used as a sense amplifier for detecting data of the nodes Q and Qb.

First, the reset operation of the node Q, Qb is performed. At t3, the voltage of the bit line pair (BL, BLB) is precharged to the voltage Vpr 2. Also, the word line WL is in the selected state. Therefore, the power supply lines V _ VDM, V _ VSM are precharged to the voltage Vpr2, and the voltage of the node Q, Qb is fixed to Vpr 2.

At t4, the wiring OGL becomes "H", whereby the transistors MW5, MW6 are turned on. The charge of capacitor CS5 is distributed to node Q and node SN 1. The charge of capacitor CS6 is distributed to node Qb and node SN 2. As a result, a voltage difference is generated between the node Q and the node Qb.

At t5, the supply of the voltages VDM, GND is started again. The memory cell 240 becomes active and amplifies the voltage difference between the nodes Q and Qb. Eventually, the voltage of the node Q, SN1 becomes Vddd, and the voltages of the nodes Qb and SN2 become GND. That is, the states of the nodes Q and Qb are restored to the states of t1 (i.e., "H" and "L"), respectively.

< storage Unit 238>

The memory cell 238 shown in fig. 17A is a modification of the memory cell 237, and includes a backup circuit 242 instead of the backup circuit 241. The backup circuit 242 is composed of 1T1C type memory cell, and includes a node SN3, a transistor MW7, and a capacitor CS 7.

Fig. 17B is a timing chart showing an example of the operation of the memory cell 238. The memory unit 238 operates in the same manner as the memory unit 237. The description of fig. 16B may be applied to the description of fig. 17B.

The backup circuit 242 backs up only the data of the node Q, but can restore the data of the node Q, Qb with the held data of the node SN 3. This is because the node Q, Qb is precharged to Vpr2 in advance, a potential difference can be generated between the node Q and the node Qb by using the charge of one capacitor CS 7.

In this specification and the like, a memory device in which a data holding portion such as a memory cell includes an OS transistor is sometimes referred to as an OS-memory device. Examples of the OS-memory device include a dorsram (registered trademark), a norsram (registered trademark), and an OS-SRAM.

The DOSRAM is an abbreviation of Dynamic Oxide Semiconductor RAM (Dynamic Oxide Semiconductor random access memory), and refers to a RAM including a 1T1C type memory cell (see fig. 15F). Norsram is an abbreviation of Nonvolatile oxide semiconductor RAM (Nonvolatile oxide semiconductor random access memory), and refers to a RAM including a gain cell (see fig. 14A, 15A to 15D). The OS-SRAM is a RAM including an SRAM cell (see fig. 16A and 17A) including a backup circuit.

Next, a processing apparatus will be described as an example of the semiconductor device. Here, a microcontroller unit (MCU) and an FPGA are exemplified.

《MCU》

The MCU250 of fig. 18 is a semiconductor device capable of clock gating and power gating.

The MCU250 is input with voltages Vddd, Vdda, GND. MCU250 includes a Power Management Unit (PMU)260, a negative voltage supply 261, a bus 262, power switches 264, 265, a Level Shifter (LS) and buffer circuit 267, a processor core 270 (hereinafter referred to as core 270), and a memory device 280. Data and the like are transferred among the PMU260, the core 270, and the memory device 280 through the bus 262.

In order to reduce power consumption of a semiconductor device, circuits which do not need to operate are stopped by using power gating or clock gating. A flip-flop is one of sequential circuits (memory circuits that retain their states) included in a semiconductor device in many cases. Therefore, by reducing the power consumption of the flip-flop, the power consumption of the semiconductor device including the flip-flop can be effectively reduced. In general, when power supply is stopped, the state of the flip-flop is erased (data held therein disappears). Thus, to power gate the semiconductor device, the state of the flip-flop needs to be backed up.

The core 270 includes a plurality of flip-flops 271. Flip-flops 271 are provided in various registers of core 270. The flip-flop 271 includes a backup circuit 272 and a scan flip-flop 273. In other words, the flip-flop 271 is a scan flip-flop including a backup circuit.

In order to backup data of the flip-flop 271 at the time of clock gating and power gating, a backup circuit 272 is provided in the flip-flop 271. The backup circuit 272 includes a plurality of OS transistors having back gates. Since the backup circuit 272 does not include a Si transistor, the backup circuit 272 can be stacked on a logic unit formed of a Si transistor. Fig. 19 shows an example of the circuit configuration of the flip-flop 271.

The scan flip-flop 273 includes nodes D1, Q1, SD, SE, RT, CK10, and a clock buffer circuit 273A.

The node D1 is a data input node, the node Q1 is a data output node, and the node SD is an input node of scan test data. Node SE is an input node for signal SCE. The node CK10 is an input node of the clock signal GCLK 10. The clock signal GCLK10 is input to the clock buffer circuit 272A. The analog switches in the scan flip-flop 273 are electrically connected to the nodes CK11 and CKB11 of the clock buffer circuit 273A, respectively. The node RT is an input node of the reset signal.

When the signal SCE is "L", the scan flip-flop 273 is inputted with the data of the node D1. When the signal SCE is "H", the scan flip-flop 273 is inputted with data of the node SD.

The circuit configuration of the scan flip-flop 273 is not limited to the circuit configuration of fig. 19. Scan flip-flops prepared in a standard circuit library may be used.

The backup circuit 272 includes nodes SD _ IN, SN11, transistors MO11 through MO13, a capacitor C11, and a node SN 11. The on/off of the transistor MO11 and the on/off of the transistor MO13 are controlled by a signal BKH, and the on/off of the transistor MO12 is controlled by a signal RCH. The back gates of the transistors MO11 to MO13 are electrically connected to the wiring BGL2 in the CPU core 330. The negative voltage Vbg2 is input to the wiring BGL 1.

The node SD _ IN is an input node of the scan test data and is electrically connected to the node Q1 of the other scan flip-flop 273. Node SN11 is a holding node for backup circuit 340.

Since the off-state current of the OS transistor is extremely small, the voltage drop of the node SN11 can be suppressed, and power is hardly consumed when data is held, the backup circuit 272 can hold data for a long time, that is, has nonvolatile properties. Thus, data may be retained in the backup circuit 340 during the time that the CPU core 330 is in a power gated state.

The memory device 280 includes a control circuit 281, a peripheral circuit 282, and a memory cell array 283. The above-described OS-memory device can be used as the memory device 280.

The negative voltage supply device 261 of embodiment 2 is used. The negative voltage supply 261 generates negative voltages Vbg1, Vbg2 from the voltage GND. The negative voltage supply 261 includes a plurality of terminals OB1 for outputting Vbg1 and a plurality of terminals OB2 for outputting Vb 2. Negative voltages Vbg1 and Vbg2 are input to the memory device 280 and the core 270, respectively.

The MCU250 receives a clock signal, an interrupt request signal, and the like from the outside. The external clock signal is input to the PMU 260. Interrupt request signals are input to the PMU260 and the core 270.

The PMU260 has functions to control clock gating and power gating. PMU260 generates a gated clock signal GCK10 (hereinafter, GCLK10) from an external clock signal. The clock signal GCLK10 is input to the core 270 and the memory device 280. The PMU260 generates various control signals. The control signals include control signals for the power switches 264, 265, control signals for the backup circuit 272, and control signals (e.g., reset signals) for the scan flip-flop 273.

The control signal of the backup circuit 272 is input to the LS and buffer circuit 267. The LS and buffer circuit 267 has a function of performing level conversion of a control signal and a function of holding the level-converted control signal. The control signal held by the LS and buffer circuit 267 is input to the backup circuit 272.

Power switch 264 controls the supply of voltage Vddd to core 270. Power switch 265 controls the supply of voltages Vddd, Vdda to memory device 280. In the case where the core 270 includes a plurality of power domains, a power switch corresponding to each power domain is provided as the power switch 264. The same applies to the power switch 265. In addition to the voltages Vddd, Vdda, a plurality of positive voltages are input to the memory device 280 according to the circuit configuration. The positive voltage input to the memory device 280 is a bit line precharge voltage, a data read reference voltage, or the like.

Signal SLEEP is output from core 270 to PMU 260. Signal SLEEP is a trigger signal used to transition core 270 to a SLEEP mode (standby mode). When the signal SLEEP is input to the PMU260, the PMU260 outputs a control signal for switching from the active mode to the SLEEP mode to a functional circuit to be controlled. The transition from the active mode to the sleep mode may be made by inputting an interrupt request signal.

First, to transition core 270 from an active mode to a sleep mode, PMU260 stops supplying the clock signal to core 270. Next, the data in the scan flip-flop 273 is written to the backup circuit 272. Specifically, the signal BKH of "H" is input to the backup circuit 272 during a predetermined clock cycle.

For example, by inputting an interrupt request signal, processing for restoring the core 270 from the sleep mode to the active mode is performed. In response to the interrupt request signal, the PMU260 outputs a control signal for transitioning from the sleep mode to the active mode to the functional circuit to be controlled. The PMU260 controls the power switches 264 and 265 to again start supplying potential to the core 270 and the memory device 280. Next, the data held by the backup circuit 272 is restored to the scan flip-flop 273. Specifically, during a predetermined clock cycle, a signal BCH of "H" is input to the backup circuit 272, and a signal SCE of "H" is input to the scan flip-flop 273. Finally, the supply of the clock signal GCLK10 to the core 270 memory device 280 is again commenced.

The PMU260 performs clock gating and power gating of the memory device 280 in the same manner as the core 270.

Alternatively, the PMU260 may be provided with a timer circuit for measuring time, and power gating of the core 270 and the memory device 280 may be performed based on the measured time.

《FPGA》

Fig. 20 shows an example of an FPGA. The FPGA400 shown in fig. 20 includes a negative voltage supply 405, a logic array 410, input-output cells (I/O)411, and peripheral circuits. Also, 1 or more of the above-described OS-memory devices may be incorporated in the FPGA 400.

I/O411 is an input-output interface of logic array 410. The peripheral circuitry includes functional circuitry for driving the logic array 410 and the I/O411. For example, the peripheral circuits include a clock generator 412, a configuration controller 413, a context controller 414, a row driver 415, and a column driver 416. The FPGA400 is inputted with Vddd, Vdda, and GND.

The negative voltage supply device 405 of embodiment 2 is used. The negative voltage supply device 405 generates a negative voltage Vbg4 from the voltage GND and includes a plurality of terminals OB for a negative voltage Vbg 4. The FPGA400 includes an OS transistor in a holding section of configuration data. The back gate of the OS transistor is input with a negative voltage Vbg 4.

Logic array 410 includes a Routing Switch Array (RSA)421 and Logic Elements (LE) 425. Here, LE425 is a logic circuit with a4 input 1 output. RSA421 includes a plurality of Routing Switches (RS) 422. Each RS422 controls the connection between two LEs 422. Multiple LEs 425 arranged on the same column may also be connected to each other to form a register chain.

LE425 includes a plurality of configuration memories (CFMs) 426. The circuit structure of LE425 is determined by configuration data stored in CFM 426. The CFM426 is a configuration memory corresponding to multiple contexts capable of storing configuration data sets. In addition, RS422 includes memory corresponding to multiple contexts, and the connections between LEs 425 are determined by configuration data stored in RS 422.

By switching the loaded configuration data set, the circuit configuration of the FPGA400 can be changed quickly. The switching of the configuration data sets may be performed by the context controller 414. Row driver 415 and column driver 416 are circuits for driving RS422 and CFM 426. The configuration controller 413 has the function of controlling the row driver 415 and the column driver 416.

Here, a circuit configuration example of the logic array 410 of two contexts is explained. These two contexts are referred to as "cnxt 0" and "cnxt 1". A context signal used to select CNTXT0 is referred to as "ctx [0 ]" and a context signal used to select CNTXT1 is referred to as "ctx [1 ]".

< Wiring switch (RS) >

RSA421 includes multiple RSs 422. Fig. 21A shows a structural example of the RS 422. RS422 is a programmable wiring switch IN which terminal IN2 is electrically connected to the output terminal of LE425, and terminal OUT2 is electrically connected to the input terminal of the other LE 425. IN the RS422, two switch circuits 423 (hereinafter, referred to as SW423) are electrically connected IN parallel between a terminal IN2 and a terminal OUT 2. Note that IN the case where the number of contexts is greater than 2, the same number of SWs 423 as the number of contexts may be electrically connected IN parallel between the terminal IN2 and the terminal OUT.

The SW423 has the same circuit configuration as the 3T type gain unit. The back gate of the OS transistor of the SW423 is electrically connected to the wiring BGL 2. The negative voltage Vbg4 is input to the wiring BGL 2.

SW423[0] and SW423[1] are connected to a common bit line BL. The column driver 416 writes configuration data to the bit line BL. SW423[ i ] (i is 0 or 1) is electrically connected to word line WL [ i ] and wiring CXL [ i ]. The wiring CXL [ i ] is a wiring for a context signal. When CNTXT0 is selected, the select transistor of SW423[0] is turned on according to ctx [0], and the select transistor of SW423[1] is turned off by ctx [1 ]. On the other hand, when cntext 1 is selected, the select transistor of SW423[0] is turned off, and the select transistor of SW423[1] is turned on.

< configuration memory (CFM) >

Fig. 21B shows a structural example of the CFM 426. CFM426 includes 2 memory cells 428 and 2 transistors ME.

Memory cells 428[0], 428[1] are electrically coupled to a common bit line pair (BL, BLB). The bit lines BL and BLB are written with the configuration data and the inverted data thereof, respectively. The memory cell 428[ i ] is electrically connected to the word line WL [ i ] and the wiring CXL [ i ]. Transistor ME [ i ] controls the conduction state between terminal OUT3 and the output terminal of memory cell 428[ i ].

The storage unit 428[ i ] is composed of 2 gain units. One gain cell stores data for bit line BL and the other bit line BLB. The back gate of the OS transistor of the memory cell 428[ i ] is electrically connected to the wiring BGL 4.

When CNTXT0 is selected, transistor ME [0] is turned on according to ctx [0], and the configuration data stored in memory cell 428[0] is output from terminal OUT 3. When CNTXT1 is selected, transistor ME11[1] is turned on according to ctx [1], and the configuration data stored in memory cell 428[1] is output.

Camera device

In this embodiment, an imaging device will be described as an example of a semiconductor device. The image pickup device 440 shown in fig. 22A includes a negative voltage supply device 441, a control circuit 442, a pixel array 443, and a peripheral circuit 444. Peripheral circuitry 444 includes row drivers 445 and column drivers 446. The pixel array 443 includes a plurality of pixels 448 arranged in a matrix of rows and columns. The pixel 448 is an imaging device having a function of converting light into electric charge, a function of storing electric charge, and the like.

Voltages Vddd, Vdda, and GND are input to the imaging device 440. The negative voltage supply device 441 used is the negative voltage supply device of embodiment 2. The negative voltage supply device 441 generates a negative voltage Vbg5 from the voltage GND and includes a plurality of terminals OB for a negative voltage Vbg 5.

Fig. 22B shows an example of the pixel 448. The pixel 448 includes a photodiode PD1, transistors MI1 to MI4, a capacitor C40, and a node FN 40. The node FN40 is used as a data holding node. The capacitor C40 is a storage capacitor for holding the voltage of the node FN 40. The transistor MI1 is referred to as a reset transistor. The transistor MI1 has a function of resetting the voltage of the node FN 40. The transistor MI2 is referred to as an exposure transistor that controls exposure operation. The transistor MI2 is a transfer transistor that controls the conduction state between the node FN40 and the photodiode PD 1. By using the transistor MI2, the timing of the exposure operation can be controlled, and therefore image capturing can be performed in a global shutter manner. The transistor MI3 is referred to as an amplifying transistor. The transistor MI3 has a function of generating an on-state current (on-state current) corresponding to the voltage of the node FN 40. The transistor MI4 is referred to as a select transistor. The transistor MI4 is a transfer transistor that controls the conduction state between the transistor MI3 and the output terminal of the pixel 448.

The back gates of the transistors MI1 and MI2 are electrically connected to the wiring BGL 5. The negative voltage Vbg5 is input to the wiring BGL5, whereby off-currents of the transistors MI1 and MI2 can be reduced. Therefore, the fluctuation of the voltage at the node FN40 can be further suppressed, and high-precision imaging can be performed.

As the photodiode PD1, a p-n junction or p-i junction diode element in a silicon substrate, a p-i-n type diode element using an amorphous silicon film (amorphous silicon film, microcrystalline silicon film), or the like can be used. Note that other photoelectric conversion elements may be used instead of the photodiode in the pixel 448. For example, diode-connected transistors may also be used. Further, a variable resistor utilizing a photoelectric effect may be formed using silicon, germanium, selenium, or the like. In addition, a photoelectric conversion element containing selenium utilizing a phenomenon called avalanche multiplication (avalanche multiplexing) may be used. In the photoelectric conversion element, a high-sensitivity sensor that amplifies electrons with respect to the amount of incident light can be obtained. As the selenium-based material, amorphous selenium or crystalline selenium can be used. For example, crystalline selenium can be obtained by performing heat treatment after forming amorphous selenium. When the particle size of the crystalline selenium is smaller than the pixel pitch, the characteristic deviation between the pixels 448 can be reduced.

Electronic component

Next, an electronic component including the semiconductor device will be described with reference to fig. 23A and 23B.

The electronic component 7000 shown in fig. 23A is a packaged IC chip including leads and a circuit portion. Although a Quad Flat Package (QFP) is employed as the Package of the electronic component 7000 in fig. 23A, the embodiment of the Package is not limited thereto.

The electronic component 7000 is mounted on the printed circuit board 7002, for example. A plurality of such IC chips are combined and electrically connected to each other on the printed circuit board 7002, thereby forming a circuit board (circuit board 7004) on which electronic components are mounted.

The circuit portion of the electronic component 7000 has a laminated structure. At least three kinds of layers 7031 to 7033 are included in the circuit portion. Layer 7031 comprises a Si transistor formed from a Si wafer. The layers 7032 and 7033 include an OS transistor and a capacitor, respectively. A layer 7033 may also be disposed between layers 7031 and 7032.

Fig. 23B is a schematic view of an electronic component 7400. The electronic component 7400 is a camera module that includes an image sensor chip 7451. The image sensor chip 7451 includes an image pickup device 440 (see fig. 22A). The image sensor chip 7451 includes at least layers 7031 to 7033 and a layer 7034. The layer 7034 includes a photoelectric conversion element.

The electronic component 7400 includes a package substrate 7411 for fixing the image sensor chip 7451, a lens cover 7421, a lens 7435, and the like. In fig. 23B, a part of the lens cover 7421 and the lens 7435 is omitted to show the internal structure of the electronic component 7400.

A signal processing circuit and the like are provided between the package substrate 7411 and the image sensor chip 7451. The electronic component 7400 is a System In Package (SiP).

The land (land)7441 is electrically connected to the electrode pad (pad) 7461. The electrode pad 7461 is electrically connected to the image sensor chip 7451 or the IC chip 7490 via a wire 7471. The IC chip 7490 may also include the OS-memory device described above.

Electronic apparatus

An embodiment of an electronic apparatus including the electronic component described above is described with reference to fig. 24A and 24D.

Fig. 24A shows a configuration example of a tablet information terminal. The information terminal 2010 shown in fig. 24A includes a housing 2011, a display 2012, an illuminance sensor 2013, a camera 2015, operation buttons 2016, and the like. The housing 2011 incorporates a storage device, a processing device, and the like, and these devices are formed by an electronic component 7000. The electronic component 7000 may also be used for a controller of the display portion 2012 and the like. The electronic component 7440 is used for the camera 2015.

The display unit 2012 includes a display system incorporating a touch sensor. When the stylus 2017 (or electronic pen), a finger, or the like touches the screen of the information terminal 2010, the information terminal 2010 may be operated. The information terminal 2010 has functions of audio call, video call using the camera 2015, electronic mail, notebook, internet, music playback, and the like.

Fig. 24B shows a configuration example of a Personal Computer (PC). The PC2030 in fig. 24B includes a housing 2031, a display portion 2032, an illuminance sensor 2034, a camera 2035, and a keyboard 2036. The keyboard 2036 may be configured to be detachable from the housing 3031. The PC2030 can be used as a notebook PC when the housing 2033 is mounted with a keyboard 2036. The PC3030 can be used as a tablet PC when the keyboard 2036 is removed from the housing 2031.

The housing 3011 incorporates a storage device, a processing device, a controller of the display portion 2032, and the like. As these means, an electronic component 7000 is used. The electronic component 2440 is used in the camera 2035.

The robot 2100 illustrated in fig. 24C includes an illuminance sensor 2101, a microphone 2102, an upper camera 2103, a speaker 2104, a display unit 2105, a lower camera 2106, an obstacle sensor 2107, a moving mechanism 2108, a processing device 2110, and a storage device 2111.

The electronic component 7000 can be used for the processing device 2110, the storage device 2111, the controller of the display portion 2105, and the like. The electronic component 7440 is used for the upper camera 2103 and the lower camera 2106.

Various information is displayed on the display unit 2105. The robot 2100 can display information that the user wants to see on the display unit 2105. The display unit 2105 may be provided with a touch panel.

By using the microphone 2102 and the speaker 2104, communication with the robot 2100 by sound can be achieved.

The upper camera 2103 and the lower camera 2106 capture images of the periphery of the robot 2100. For example, the sound emitted from the speaker 2104 by the robot 2100 is selected based on the information of the user captured by the upper camera 2103.

The robot 2100 may move using the moving mechanism 2108. The obstacle sensor 2107 may sense whether an obstacle exists in the moving direction of the robot 2100. The robot 2100 can recognize the surrounding environment using the upper camera 2103, the lower camera 2106, and the obstacle sensor 2107, and can safely and independently move.

The flying object 2120 shown in fig. 24D includes a processing device 2121, a storage device 2122, a camera 2123, and a propeller 2124. The electronic component 7000 is used in the processing device 2121, the storage device 2122, and the like. An electronic component 7400 is included in the camera 2123.

The automobile 2140 shown in fig. 24D includes various sensors such as an infrared radar, a millimeter wave radar, and a laser radar. The automobile 2140 analyzes the image captured by the camera 2141 to determine traffic information around it, such as the presence of a guardrail 2150 or a pedestrian, and the like, whereby automatic driving is possible. The camera 2141 incorporates an electronic component 7400. The electronic circuit (e.g., processing device, memory device) of the automobile 2140 incorporates the electronic component 7000.

Circuit section of electronic component

The laminated structure of the circuit portion of the electronic component 7000 will be described with reference to fig. 25. As an example, fig. 25 shows a cross-sectional structure of the memory cell 237 (see fig. 16A). Fig. 25 shows a transistor MW5, a capacitor CS5, and a transistor MT 5. The transistor MT5 is a transfer transistor formed of a single-crystal silicon wafer 5500 electrically connected to a bit line BL. Further, fig. 25 is a sectional view for explaining an example of a stacked structure of an IC chip, not a sectional view of an IC chip along a specific line.

The transistor MT5, the transistor MW5, and the capacitor CS5 are formed in the layer 7031, the layer 7032, and the layer 7033, respectively. A plurality of wiring layers are provided between the layers 7031 and 7032. The wiring layer is provided with word lines WL and the like. The transistor MW5 has the same structure as the OS transistor 5003 (see fig. 26B) described later.

Example of Structure of OS transistor

Next, a structure example of the OS transistor is described with reference to fig. 26A and 26B. The left side of fig. 26A and 26B shows the cross-sectional structure of the OS transistor in the channel length direction. The right side of fig. 26A and 26B shows a cross-sectional structure of the OS transistor in the channel width direction.

The OS transistor 5001 shown in fig. 26A is formed over an insulating surface, here, over the insulating layer 5001. Here, the OS transistor 5001 is formed over the insulating layer 5021. The OS transistor 5001 is covered with insulating layers 5028 and 5029. The OS transistor 5001 includes insulating layers 5022 to 5027, 5030 to 5032, metal oxide layers 5011 to 5013, and conductive layers 5050 to 5054.

The insulating layer, the metal oxide layer, the electric conductor, and the like in the drawings may each have a single-layer structure or a stacked-layer structure. These layers can be formed using various deposition methods such as a sputtering method, a Molecular Beam Epitaxy (MBE) method, a Pulsed Laser Ablation (PLA) method, a Chemical Vapor Deposition (CVD) method, and an Atomic Layer Deposition (ALD) method. Examples of the CVD method include a plasma CVD method, a thermal CVD method, and a metal organic CVD method.

The metal oxide layers 5011 to 5013 are collectively referred to as an oxide layer 5010. As shown in fig. 26A, the oxide layer 5010 includes a portion where a metal oxide layer 5011, a metal oxide layer 5012, and a metal oxide layer 5013 are stacked in this order. When the OS transistor 5001 is turned on, a channel is mainly formed in the metal oxide layer 5012 of the oxide layer 5010.

A gate electrode of the OS transistor 5001 is formed using the conductive layer 5050. A pair of electrodes serving as a source electrode and a drain electrode of the OS transistor 5001 is formed using the conductive layers 5051 and 5052. The conductive layers 5050 to 5052 are covered with the insulating layers 5030 to 5032 which function as barrier layers. A back gate electrode of the OS transistor 5001 is formed using a stack of conductive layers 5053 and 5054.

A gate insulating layer on the gate side is formed using the insulating layer 5027. The gate insulating layer on the back gate side is formed using a stack of insulating layers 5024 to 5026. The insulating layer 5028 is an interlayer insulating layer. The insulating layer 5029 is a barrier layer.

The metal oxide layer 5013 covers the stacked body of the metal oxide layers 5011 and 5012 and the conductive layers 5051 and 5052. The insulating layer 5027 covers the metal oxide layer 5013. The conductive layers 5051 and 5052 have a region overlapping with the conductive layer 5050 with the metal oxide layer 5013 and the insulating layer 5027 therebetween.

As examples of the conductive material used for the conductive layers 5050 to 5054, there are the following materials: a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus; silicides such as nickel silicide; metals such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium; and a metal nitride (tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride) containing the above metal as a component. In addition, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide to which silicon oxide is added, or the like can be used.

For example, the conductive layer 5050 is a single layer of tantalum nitride or tungsten. Alternatively, when the conductive layer 5050 has a two-layer structure or a three-layer structure, the following combinations may be employed: aluminum and titanium; titanium nitride and titanium; titanium nitride and tungsten; tantalum nitride and tungsten; tungsten nitride and tungsten; titanium, aluminum and titanium; titanium nitride, aluminum and titanium; titanium nitride, aluminum, and titanium nitride. Among them, the first-mentioned conductor is used for the layer on the insulating layer 5027 side.

The conductive layers 5051 and 5052 have the same layer structure. For example, when the conductive layer 5051 is a single layer, a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing such a metal as a main component can be used. When the conductive layer 5051 has a two-layer structure or a three-layer structure, the following combinations may be employed: titanium and aluminum; tungsten and aluminum; tungsten and copper; copper-magnesium-aluminum alloys and copper; titanium and copper; titanium or titanium nitride, aluminum or copper, and titanium or titanium nitride; molybdenum or molybdenum nitride, aluminum or copper, and molybdenum or molybdenum nitride. Among them, the first-mentioned conductor is used for the layer on the insulating layer 5027 side.

For example, it is preferable that the conductive layer 5053 be a conductive layer having barrier properties against hydrogen (e.g., a tantalum nitride layer), and the conductive layer 5054 be a conductive layer having higher conductivity than the conductive layer 5053 (e.g., a tungsten layer). By adopting this structure, the stack of the conductive layers 5053 and 5054 is used as a wiring and has a function of suppressing diffusion of hydrogen to the oxide layer 5010.

As examples of the insulating material used for the insulating layers 5021 to 5032, there are the following materials: aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and aluminum silicate. The insulating layers 5021 to 5032 are each formed using a single-layer structure or a stacked-layer structure of these insulating materials. The layers for the insulating layers 5021 to 5032 may include a variety of insulating materials.

In this specification and the like, oxynitride refers to a compound having an oxygen content greater than a nitrogen content, and oxynitride refers to a compound having a nitrogen content greater than an oxygen content.

In the OS transistor 5001, the oxide layer 5010 is preferably surrounded by an insulating layer having barrier properties to oxygen and hydrogen (hereinafter, such an insulating layer is referred to as a barrier layer). With this structure, release of oxygen from the oxide layer 5010 can be suppressed, and invasion of hydrogen into the oxide layer 5010 can be suppressed, whereby reliability and electrical characteristics of the OS transistor 5001 can be improved.

For example, the insulating layer 5029 can be used as a barrier layer, and at least one of the insulating layers 5021, 5022 and 5024 can be used as a barrier layer. The barrier layer can be formed using a material such as aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, silicon nitride, or the like. Other barrier layers can also be disposed between the oxide layer 5010 and the conductive layer 5050. Alternatively, a metal oxide layer having barrier properties against oxygen and hydrogen may be provided as the metal oxide layer 5013.

The insulating layer 5030 is preferably a barrier layer which prevents oxidation of the conductive layer 5050. When the insulating layer 5030 has barrier properties against oxygen, the conductive layer 5050 can be suppressed from being oxidized by oxygen released from the insulating layer 5028 or the like. For example, the insulating layer 5030 can be formed using a metal oxide such as aluminum oxide.

Fig. 26A illustrates an example in which the oxide layer 5010 has a three-layer structure, but an embodiment of the present invention is not limited thereto. For example, the oxide layer 5010 may have a two-layer structure without the metal oxide layers 5011 and 5013, or may be formed of one of the metal oxide layers 5011 and 5012. The oxide layer 5010 may be formed of four or more metal oxide layers.

The OS transistor 5003 in fig. 26B is different from the OS transistor 5001 in the structure of a gate electrode and an oxide layer.

The gate electrode (5050) of the OS transistor 5003 is covered with the insulating layers 5033, 5034. The OS transistor 5003 includes an oxide layer 5009 formed of metal oxide layers 5011 and 5012. Instead of the conductive layers 5051 and 5052, low-resistance regions 5011a and 5011b are provided in the metal oxide layer 5011, and low-resistance regions 5012a and 5012b are provided in the metal oxide layer 5012. By selectively adding an impurity element (e.g., hydrogen or nitrogen) to the oxide layer 5009, the low-resistance regions 5011a, 5011b, 5012a, and 5012b can be formed.

By adding an impurity element to the metal oxide layer, oxygen vacancies are formed in the region to which the impurity element is added, and the impurity element intrudes into the oxygen vacancies. Therefore, the carrier density increases, and the resistance of this region decreases.

Metal oxides

The channel formation region of the OS transistor preferably includes a closed-aligned composite metal oxide semiconductor (CAC-OS).

The CAC-OS has a function of electrical conductivity in one part of the material and an insulating function in the other part of the material, and as a whole, the CAC-OS has a function of a semiconductor. When CAC-OS or CACmetal oxide is used for an active layer of a transistor, electrons (or holes) used as carriers flow due to the conductive function, and electrons used as carriers do not flow due to the insulating function. The CAC-OS can have a switching function (on/off function) by a complementary action of the conductive function and the insulating function. In the CAC-OS, functions can be maximized by separating the functions.

The CAC-OS includes a conductive region and an insulating region. The conductive region has the above-described function of conductivity, and the insulating region has the above-described function of insulation. Sometimes conductive and insulating regions in a material are separated at the nanoparticle level. The conductive region and the insulating region may be unevenly distributed in the material. Sometimes the conductive areas are observed as having their edges blurred and connected in a cloud.

In CAC-OS, the conductive region and the insulating region may have a size of 0.5nm to 10nm, preferably 0.5nm to 3nm, and may be dispersed in the material.

The CAC-OS contains components with different band gaps. For example, the CAC-OS includes a component having a wide gap due to the insulating region and a component having a narrow gap due to the conductive region. In this configuration, carriers flow mainly in a component having a narrow gap. The component having a narrow gap and the component having a wide gap act complementarily, and carriers flow through the component having a wide gap in conjunction with the component having a narrow gap. Therefore, when the CAC-OS described above is used for a channel formation region of a transistor, high current driving force and high field-effect mobility of the OS transistor can be achieved.

Metal oxide semiconductors are classified into single crystal metal oxide semiconductors and non-single crystal metal oxide semiconductors according to their crystallinity. Examples of the non-single crystalline metal oxide semiconductor include a c-axis oriented crystalline oxide semiconductor (CAAC-OS), a polycrystalline metal oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), and an amorphous-like metal oxide semiconductor (a-like OS).

The channel formation region of the OS transistor preferably includes a metal oxide having a crystalline portion, such as CAAC-OS or nc-OS.

CAAC-OS has c-axis orientation, and a plurality of nanocrystals are connected in the a-b plane direction, and the crystal structure is distorted. The distortion is a portion in which the direction of lattice alignment changes between a region in which lattice alignments coincide and a region in which other lattice alignments coincide among regions in which a plurality of nanocrystals are connected.

In nc-OS, a minute region (for example, a region of 1nm to 10nm, particularly 1nm to 3 nm) has a periodic atomic arrangement. nc-OS has no regularity of crystallographic orientation between different nanocrystals. Therefore, the orientation of the entire film was not observed. Therefore, sometimes nc-OS does not differ from a-like OS or amorphous oxide semiconductor in some analytical methods.

The a-like OS has a structure between nc-OS and amorphous metal oxide semiconductor. The a-like OS contains holes or low density regions. The a-like OS has lower crystallinity than nc-OS and CAAC-OS.

In this specification and the like, CAC represents a function or a material of a metal oxide semiconductor, and CAAC represents a crystal structure of a metal oxide semiconductor.

Description of the symbols

9A, 9B: curve, 10, 11, 20, 21, 22, 23, 24, 25, 171, 172: comparison circuit, 14, 15, 34: differential pair, 17: current source, 18: load circuit, 30, 31, 32, 33, 172A: differential input circuit, 35, 40, 41, 42, 43, 45: output circuit, 38, 39: inverter circuit, 100, 101: negative voltage supply device, 111, 141: control circuit, 112, 117A, 117B, 117C, 123, 142, 153: charge pump circuit, 114: bias voltage generation circuit, 120, 150: output voltage regulator, 122, 152: negative voltage holding circuit, 127, 154: drive circuit, 128, 155, 161, 162: monitor circuit, 143: frequency dividing circuit, 171, 172: comparison circuit, 173: latch circuit, 175, 177: a selection circuit for selecting a selection of a circuit,

200. 211, 280: storage device, 210, 261: negative voltage supply device, 215, 281: control circuit, 220, 283: memory cell array, 221, 282: peripheral circuit, 223: row circuit, 224: column circuit, 225: input-output circuit, 230, 231, 232, 233, 234, 235, 236, 237, 238, 240: memory cells, 241, 242, 272: backup circuit, 250: microcontroller unit (MCU), 260: power Management Unit (PMU), 262: bus, 264, 265: power switch, 265: power switch, 267: level Shifter (LS) and buffer circuit, 270: processor core, 271: flip-flop, 272A, 273B: clock buffer circuit, 273: scan flip-flop, 330: the core of the CPU is a core of the CPU,

340: backup circuit, 400: FPGA, 405: negative voltage supply device, 410: logic array, 411: input-output unit (I/O), 412: clock generator, 413: configuration controller, 414: context controller, 415: row driver, 416: column driver, 421: wiring switch array (RSA), 422: wiring switch (RS), 423: switching circuit (SW), 425: logic Element (LE), 426: configuration memory (CFM), 428: memory cell, 440: imaging device, 441: negative voltage supply device, 442: control circuit, 443: pixel array, 444: peripheral circuitry, 445: row driver, 446: column driver, 448: pixel, 2010: information terminal 2011, 2031, 3011, 3031: housing, 2012, 2032, 2105: display unit, 2013, 2034, 2101: illuminance sensor, 2015, 2035, 2123, 2141: camera, 2016: operation buttons, 2017: stylus, 2030, 3030: PC, 2036: keyboard, 2100: robot, 2102: microphone, 2103: upper camera, 2104: speaker, 2106: lower camera, 2107: obstacle sensor, 2108: moving mechanism, 2110, 2121: processing device, 2111, 2122: storage device, 2120: flyer, 2121: processing apparatus, 2124: propeller, 2140, 2980: automobile, 2150: guard bar, 5001, 5003: OS transistor, 5009, 5010: oxide layer, 5011, 5012, 5013: metal oxide layers, 5011a, 5011b, 5012a, 5012 b: low-resistance regions, 5021, 5022, 5024, 5027, 5028, 5029, 5030, 5033, 5034: an insulating layer is formed on the substrate,

5050. 5051, 5052, 5053, 5054: conductive layer, 5500: single crystal silicon wafer, 7400: electronic component, 7411: package substrate, 7421: lens cover, 7435: lens, 7440: electronic component, 7441: land, 7451: image sensor chip, 7461: electrode pad, 7471: a wire, 7490, an IC chip,

BGL, BGL1, BGL2, BGL4, BGL5, CXL, OGL: wiring, BL, BLB: bit lines, CK10, CK11, D1, FN40, Q, Qb, Q1, RT, SD _ IN, SE, SN1, SN2, SN3, SN11, X1, X2, X5, X6, X11, X12, X13: node, CDL: capacitor line, C11, C21, C22, C25, C40, CS1, CS3, CS5, CS6, CS 7: capacitors, IN2, INN, INP, IN _ cp, OB1, OB2, OCM, OCMB, OUT2, OUT _ cp, OUT 3: terminals, MI1, MI2, MI3, MI4, MN1, MN5, MN6, MN7, MO1, MO2, MO3, MO5, MO7, MO11, MO12, MO13, MO14, MO21, MO22, MO25, MP1, MP2, MP5, MP6, MP7, MR1, MT5, MW1, MW2, MW3, MW5, MW6, MW 7: transistors, PL2, PL3, V _ VDM, V _ VSM: power supply line, RBL: sense bit line, RWL: sense word line, Rd1, Rd 2: load, SL: source line, WBL: write bit line, WL: word line, WWL: the word line is written.

The present application is based on japanese patent application No.2017-107964, filed by the office of japanese patent on 31/5/2017, the entire contents of which are incorporated herein by reference.