阅读说明：本技术 数据储存装置及其快取分流方法
(Data storage device and cache shunting method thereof
) 是由 王德富
刘迅思 于 2018-06-26 设计创作，主要内容包括：本发明提供一种数据储存装置,包括：一闪存,具有多个区块用以储存数据；一动态随机存取内存；以及一控制器,用以依据来自一主机的一写入指令的至少一数据特征以由该动态随机存取内存中配置相应的一快取空间,其中,该控制器是将该写入指令中的数据写入相应的该快取空间；其中,响应来自该主机的一读取指令,该控制器是判断在该快取空间中是否储存有该读取指令欲读取的所有数据；当该快取空间中储存有该读取指令欲读取的所有数据,该控制器是直接由该快取空间读取该读取指令欲读取的所有数据。(The invention provides a data storage device, comprising: a flash memory having a plurality of blocks for storing data; a dynamic random access memory; the controller is used for allocating a corresponding cache space from the dynamic random access memory according to at least one data characteristic of a write command from a host, wherein the controller writes the data in the write command into the corresponding cache space; wherein, in response to a read command from the host, the controller determines whether all data to be read by the read command is stored in the cache space; when the cache space stores all the data to be read by the read instruction, the controller directly reads all the data to be read by the read instruction from the cache space.)
1. A data storage device, comprising:
a flash memory having a plurality of blocks for storing data;
a dynamic random access memory; and
a controller for allocating a corresponding cache space from the DRAM according to at least one data characteristic of a write command from a host,
wherein the controller writes the data in the write command into the corresponding cache space;
wherein, in response to a read command from the host, the controller determines whether all data to be read by the read command is stored in the cache space;
when the cache space stores all the data to be read by the read instruction, the controller directly reads all the data to be read by the read instruction from the cache space.
2. The data storage device of claim 1 wherein the at least one data characteristic comprises a stream identifier, a namespace identifier, a data size, a logical address distribution, or combinations thereof, of the write command.
3. The data storage device of claim 1, wherein:
if the size of the cache space is enough to store all the data in the write command, the controller writes all the data in the write command into the cache space, but does not write the data in the write command into the flash memory;
if the size of the cache space is not enough to store all the data in the write command, the controller writes part of the data in the write command into the cache space and writes the rest of the data in the write command into the flash memory.
4. A data storage device in accordance with claim 3 wherein data written into the cache space is, for example, frequently accessed data or hot data.
5. The data storage device of claim 1, wherein:
when the cache space does not store all the data to be read by the read instruction, the controller determines whether there is a part of the data to be read by the read instruction in the cache space,
if yes, the controller reads partial data to be read by the reading instruction from the cache space and reads the rest data to be read by the reading instruction from the flash memory;
if not, the controller reads all data to be read by the reading instruction from the flash memory.
6. A cache splitting method for a data storage device, the data storage device including a flash memory and a dynamic random access memory, the method comprising:
allocating a corresponding cache space from the DRAM according to at least one data characteristic of a write command from a host;
writing the data in the write command into the corresponding cache space;
responding to a reading instruction from the host computer, and judging whether all data to be read by the reading instruction is stored in the cache space; and
when the cache space stores all the data to be read by the read instruction, all the data to be read by the read instruction is directly read by the cache space.
7. The cache splitting method of claim 6, wherein the at least one data characteristic comprises a stream identifier, a namespace identifier, a data size, a logical address distribution, or a combination thereof, of the write instruction.
8. The cache splitting method of claim 6, further comprising:
if the size of the cache space is enough to store all the data in the write command, all the data in the write command is written into the cache space, and the data in the write command is not written into the flash memory; and
if the size of the cache space is not enough to store all the data in the write command, part of the data in the write command is written into the cache space, and the rest of the data in the write command is written into the flash memory.
9. The cache splitting method as claimed in claim 8, wherein the data written into said cache space is frequently accessed data or hot data.
10. The cache splitting method of claim 6, further comprising:
when the cache space does not store all the data to be read by the reading instruction, judging whether partial data to be read by the reading instruction exists in the cache space;
if yes, reading part of data to be read by the reading instruction from the cache space, and reading the rest data to be read by the reading instruction from the flash memory; and
if not, all data to be read by the reading instruction is read by the flash memory.
[ technical field ] A method for producing a semiconductor device
The present invention relates to a data storage device, and more particularly, to a data storage device and a cache splitting method thereof.
[ background of the invention ]
Flash memory is a popular non-volatile data storage medium that is electrically erased and programmed. Taking the nand-type flash memory (i.e., NAND FLASH) as an example, it is commonly used as a storage medium for memory cards (memory cards), universal serial bus flash devices (USB flash devices), Solid State Disks (SSDs), embedded flash modules (eMMC) …, and the like.
The storage array of a flash memory (e.g., NAND FLASH) includes blocks (pages), and each block includes pages (pages). Since the number of blocks in a flash memory is limited, how to effectively utilize the blocks in the flash memory is an important issue.
[ summary of the invention ]
The invention provides a data storage device, comprising: a flash memory having a plurality of blocks for storing data; a dynamic random access memory; the controller is used for allocating a corresponding cache space from the dynamic random access memory according to at least one data characteristic of a write command from a host, wherein the controller writes the data in the write command into the corresponding cache space; wherein, in response to a read command from the host, the controller determines whether all data to be read by the read command is stored in the cache space; when the cache space stores all the data to be read by the read instruction, the controller directly reads all the data to be read by the read instruction from the cache space.
The invention further provides a cache shunting method, which is used for a data storage device, wherein the data storage device comprises a flash memory and a dynamic random access memory, and the method comprises the following steps: allocating a corresponding cache space from the DRAM according to at least one data characteristic of a write command from a host; writing the data in the write command into the corresponding cache space; responding to a reading instruction from the host computer, and judging whether all data to be read by the reading instruction is stored in the cache space; when the cache space stores all the data to be read by the read instruction, all the data to be read by the read instruction is directly read by the cache space.
[ description of the drawings ]
FIG. 1 is a block diagram of an electronic system according to an embodiment of the invention.
FIG. 2A is a diagram illustrating a cache controller writing data into a cache space according to an embodiment of the present invention.
FIG. 2B is a diagram illustrating the cache controller of FIG. 2A reading data from the cache space according to the present invention.
FIG. 2C is a diagram illustrating a flash memory being written with a plurality of stream commands according to an embodiment of the present invention.
FIG. 2D is a diagram illustrating data being written into flash memories according to stream identifiers of stream commands according to an embodiment of the invention.
FIG. 2E is a diagram illustrating data being written into flash memories according to stream identifiers of stream commands according to an embodiment of the invention.
FIG. 3 is a flow chart illustrating a cache splitting method for a data storage device according to an embodiment of the present invention.
[ notation ] to show
100 electronic system
120-host
140-data storage device
160-controller
162-arithmetic unit
164-permanent memory
166-dynamic random access memory
168-cache
180-flash memory
181 to block
182-page
181A-181F-block
1821 supplement 1823-page
1620-cache controller
1621-series flow classifier
1622 data searcher
1623 data access device
1630 cache space
1631-range
1661-H2F Table
1662 cache space
1663 data buffer
LBA 6-LBA 102-logical Address
211-
S310-S330 step
[ detailed description ] embodiments
The following description sets forth various embodiments of the invention. The following description is made for the purpose of illustrating the general principles of the invention and is not meant to limit the invention. The actual scope of the invention should be determined with reference to the claims.
The nonvolatile memory may be a flash memory (flash memory), a Magnetoresistive random access memory (Magnetoresistive RAM), a Ferroelectric RAM (Ferroelectric RAM), a Resistive RAM (RRAM), a Spin Transfer Torque RAM (STT-RAM) …, and the like, and provides a storage medium for storing data for a long time, and may be used to implement a data storage device or be applied to a data center. The following discussion will be made by taking a Flash Memory (Flash Memory) as an example.
Nowadays, Flash Memory is often used as a storage medium for implementing products such as Memory Card (Memory Card), universal serial bus Flash Device (USB Flash Device), Solid State Disk (SSD) …, etc. One application is to package flash memory with its controller in a multi-chip package-known as an embedded flash memory module (e.g., eMMC).
The data storage device using the flash memory as the storage medium can be applied to various electronic devices. The electronic device comprises a smart phone, a wearable device, a tablet computer, a virtual reality device …, and the like. The operation module of the electronic device can be regarded as a Host (Host) to operate the data storage device used by the electronic device to access the flash memory in the data storage device.
Flash-implemented Data storage devices may also be used to construct Data centers (Data centers). For example, a server may operate an array of Solid State Disks (SSDs) to form a data center. The server can be regarded as a Host (Host), and the linked solid state disk is operated to access the flash memory therein.
The Host (Host) distinguishes user data by logical addresses (e.g., logical block address LBA, global Host page number GHP, Host block HBlk, Host page HPage …, etc.). After the user data is written into the flash memory, the mapping relation between the logical address and the physical space of the flash memory is recorded by the flash memory of the control unit, and when the host reads the user data, the control unit provides the user data from the flash memory according to the mapping relation.
The flash memory can be used as a storage medium of a data storage device, and the storage space comprises a plurality of Blocks (Blocks), wherein each block comprises a plurality of Pages (Pages). Flash memory uses blocks as the minimum unit of erase (erase) operations. Blocks (data blocks) become idle blocks after being erased, and the idle blocks become data blocks after user data is written in the idle blocks. When user data is written into a block page by page, the logical addresses of the user data stored in each page of the block need to be dynamically sorted into a physical-to-logical mapping table (F2 HTable). In one embodiment, the idle blocks configured to receive user data are called active blocks (active blocks), the idle blocks used in a Garbage Collection Procedure (Garbage Collection Procedure) to receive user data of a source Block (source Block) are called Destination blocks (Destination blocks), and the physical-to-logical mapping tables (F2H Table) of the active blocks and the Destination blocks can be dynamically organized on a volatile memory. For example, Static Random Access Memory (SRAM) used by the control unit/controller of the data storage device may be used for dynamic sorting of the physical-to-logical mapping Table, and then the mapping information from the physical address to the logical address is reverse converted and used to update the logical-to-physical mapping Table (H2F Table). The control unit stores the whole logic-to-physical mapping table or only partial updated logic-to-physical mapping table on the flash memory. The physical-to-logical mapping table that is dynamically updated on volatile memory with active blocks or destination blocks is generally referred to as a small table, and the logical-to-physical mapping table that is non-volatile stored on flash memory is referred to as a large table. The control unit integrates the mapping information recorded by the whole or partial small tables into the large table, and finally, the controller takes the large table as the basis for user data access.
FIG. 1 is a block diagram of an electronic system according to an embodiment of the invention. The Electronic system 100 may be, for example, a Personal Computer (Personal Computer), a Data Server (Data Server), a Network-attached storage (NAS), a Portable Electronic Device (Portable Electronic Device), etc., but the invention is not limited thereto. The Portable electronic Device may be, for example, a notebook, a Handheld mobile phone, a smart phone, a tablet computer, a Personal Digital Assistant (PDA), a Digital Camera (Digital Camera), a Digital Video Camera (Digital Video Camera), a Portable Multimedia Player (Portable Multimedia Player), a Personal Navigation Device (Personal Navigation Device), a Handheld Game Console (hand held Game Console), an electronic Book (e-Book), etc., but the invention is not limited thereto.
Electronic system 100 includes a host 120 and a data storage device 140. The data storage device 140 includes a flash memory 180 and a controller 160, and is operable according to commands issued by the host 120. The controller 160 includes an arithmetic unit 162, a persistent Memory (e.g., a read only Memory ROM)164, and a Dynamic Random Access Memory (DRAM) 166. The arithmetic unit 162 may be, for example, a General-Purpose Processor (General-Purpose Processor) or a Microcontroller (Microcontroller), but the present invention is not limited thereto.
The persistent memory 164 and the loaded program codes and data constitute Firmware (Firmware) that is executed by the arithmetic unit 162, so that the controller 160 controls the flash memory 180 based on the Firmware. Dynamic Random Access Memory (RAM)166 is used to load program code and parameters to provide the controller 160 with the action according to the loaded program code and parameters. In one embodiment, the dram 166 may further serve as a Data Buffer 1663 for storing write Data from the host 120. When the data stored in the dram 166 reaches a predetermined size, the data is written into the flash memory 180. In addition, the computing unit 162 can read all or part of the stored logical-to-object mapping table (H2F table) 1661 to the dram 166 from the flash memory 180.
In some embodiments, the data storage device 140 may further include a cache 168, which is a volatile Memory, such as a Static Random Access Memory (SRAM) or other type of Static Memory, for fast Access to data, and which has a faster data Access speed than dynamic Random Access Memory. The cache 168 is used for storing Frequently Accessed Data (frequencytly Accessed Data) or hot Data (HotData) in the flash memory 180. In some embodiments, the cache 168 may be integrated with the controller 160 in a chip package, and the dram 166 may be integrated in the same chip package or may be separate from the chip package of the controller 160.
In some embodiments, dynamic random access memory 166 may replace cache 168. That is, DRAM 166 is used as a cache. In some embodiments, DRAM 166 may be configured (allocated) with one or more cache spaces for storing different types of data, as will be described in greater detail below. For convenience, the following embodiments are described with reference to the dram 166 being configured with one or more cache spaces 1662.
The flash memory 180 includes a plurality of Blocks (Blocks)181, wherein each block 181 includes a plurality of Pages (Pages)182 for storing data.
In one embodiment, the host 120 and the data storage device 140 may communicate with each other via a Peripheral Component Interconnect Express (PCIe) bus or a Serial Advanced Technology Attachment (SATA) bus, for example. In addition, the data storage device 140 supports, for example, a Non-Volatile Memory Express (NVMe) standard.
The host 120 can write data to the data storage device 140 or read data stored in the data storage device 140. In detail, the host 120 may generate a Write Command (Write Command) requesting the data storage device 140 to Write data, or may generate a Read Command (Read Command) requesting to Read data stored in the data storage device 140. Either the write command or the read command may be considered an input/output (I/O) command.
When the host 120 issues a read command to read data from the data storage device 140, the arithmetic unit 162 checks whether the data to be read exists in the cache space of the dram 166. If the data to be read exists in the cache space of the dram 166, the arithmetic unit 162 directly fetches the data to be read from the corresponding cache space of the dram 166 and sends the fetched data back to the host 120 to complete the read instruction.
When the host 120 issues a write command to write data to the data storage device 140, the arithmetic unit 162 checks the attribute of the write command and stores the data in the write command in the corresponding cache space of the dram 166 according to the attribute of the write command.
FIG. 2A is a diagram illustrating a cache controller writing data into a cache space according to an embodiment of the present invention. FIG. 2B is a diagram illustrating the cache controller of FIG. 2A reading data from the cache space according to the present invention.
As shown in FIG. 2A, the unit 162 comprises a cache controller 1620, and the cache controller 1620 comprises: a Stream Classifier (Stream Classifier)1621, a data searcher (Search Engine)1622, and a data accessor (TrigEngine) 1623. In some embodiments, the cache controller 1620 may be a separate control circuit, for example, and is electrically connected to the arithmetic unit 162 and the DRAM 166.
The Stream classifier 1621 is used to classify i/o commands from the host 120, for example, but not limited to, Stream identifier (Stream ID), Namespace identifier (Namespace ID), or data attribute, to classify i/o commands from the host 120.
The data searcher 1622 is used to search the data stored in each cache space and sends a start address and length to the data accessor 1623.
The data accessor 1623 receives a write command from the stream sorter 1621 to write data into the corresponding cache space (e.g., the cache space 1630 in FIG. 2A) or a read command from the stream sorter 1621 to read the desired data from the corresponding cache space, according to the cache start address (e.g., the logical address) and the length indicated by the I/O command from the data searcher 1622.
In detail, the data searcher 1622 may additionally establish a Cache Lookup Table (not shown) in the dram 166, which records mapping relationships between logical addresses and Cache addresses in different Cache spaces. For example, in one embodiment, the data storage device 140 is in an initial state and no data is stored in each cache space. When the host 120 sends a write command (e.g., a Stream write command or other type of write command) to the data storage device 140, the Stream classifier 1621 is used to classify the write command from the host 120, for example, the write command from the host 120 can be classified by using a Stream identifier (Stream ID), a Namespace identifier (Namespace ID), or a data attribute (e.g., logical address distribution, data size, etc.). For example, each namespace identifier may have a different cache space, meaning that each cache space has a different logical address (LBA) range in DRAM 166.
In some embodiments, the stream classifier 1621 may classify according to a logical address in a write command of the host 120 or a size of transmission data, for example. For example, the data size of a write command can be divided into 4K, 16K, or 128K (without limitation), and can be divided into different types. The stream classifier 1621 may also count the distribution of logical addresses in each write command from the host 120, and divide the logical addresses into a plurality of groups, where each group corresponds to one stream. In addition, the stream classifier 1621 may also classify the data by comprehensively considering the logical address of the write command from the host 120 and the size of the transmission data.
Briefly, the stream classifier 1621 classifies the data according to at least one data characteristic of the write command from the host 120, and allocates a cache space corresponding to each classification from the dram 166. The stream identifier, the namespace identifier, the data size, the logical address distribution, and the stream classifier 1621 disclosed in the previous embodiments may be classified according to one of the data characteristics alone or in combination.
If the Write Command is a Stream Write Command (Stream Write Command), it may carry a Stream identifier. Therefore, the stream classifier 1621 may classify according to the stream identifier and notify the data accessor 1623 to allocate a corresponding cache space for each different stream identifier in the dram 166. In addition, the data searcher 1622 converts the starting logical address and the number of sectors in the stream write command into the corresponding cache write address and its range (e.g., consecutive logical addresses) in the cache space.
In some embodiments, since no data is stored in each cache space, the data accessor 1623 writes the data of the stream write command into the corresponding cache space according to the cache write address and the range thereof from the data searcher 1622, and the data accessor 1623 further searches the physical address corresponding to the write logical address in the stream write command according to the logical-to-object mapping table stored in the dram 166, and writes the data of the stream write command into the flash memory 180 according to the searched physical address. In other embodiments, the cache controller 1620 does not write data into the flash memory 180 first, but rather writes (Flush) data into the flash memory 180 quickly before the data storage device 140 is powered down or the cache needs to be cleared.
When the host 120 continues to write data to the data storage device 140, the arithmetic unit 162 can write data from the host 120 into the corresponding cache space and the flash memory 180 according to a similar manner. If the size of the cache space is large enough, the data accessor 1623 may write the data in the streaming write instruction completely into the cache space so that a subsequent read instruction can read the data from the cache space. If the cache space is not large enough to store all the data in the stream write instruction, the data accessor 1623 may determine which portion of the data is to be written into the cache space according to a determination mechanism (e.g., write order of the data or cold/hot data).
After the electronic system 100 operates for a period of time, the computing unit 162 accumulates the number of times of reading data or pages to determine whether the data in the flash memory 180 is frequently accessed data or hot data, and reads the data from the flash memory 180 and temporarily stores the data in each cache space for subsequent reading. Conversely, data that is already stored in the cache space but has been read less frequently (cold data) is replaced (flushed) to free the cache space for temporary storage of hot data.
For example, there may be multiple namespaces in the data storage device 140, wherein several namespaces have higher priority and are read and written frequently. For example, where the first namespace is 20MB, the cache controller 1620 may allocate at least 10MB of the first namespace from the DRAM 166 to store data of the first namespace, e.g., the most frequently operated 10MB of data may reside in the first namespace and the other 10MB of data may be stored in the flash memory 180. Therefore, if the host 120 wants to read the data in the first namespace, the cache hit rate of the first cache space can reach at least 50% when reading through the first cache space, which means that the service life of the flash memory used in the first namespace can be prolonged to more than 2 times, and the efficiency of data reading can be significantly improved.
If the cache controller 1620 allocates at least 20MB of the first cache space from the DRAM 166, all the data in the first namespace can be stored in the first cache space, i.e., no data needs to be read from the flash memory 180. Therefore, the lifetime of the flash memory 180 of the first namespace can be significantly increased. In addition, since all read/write operations to the first namespace are performed to the first cache space, the response speed of the read/write operations is greatly increased.
In one embodiment, when the host 120 issues a read command, the data search unit 1622 searches the cache lookup table to determine whether the data to be read by the read command is stored in the cache space, for example, according to the Start logical address (Start LBA) and the Sector number (Sector Count) indicated in the read command. If the data to be read by the read instruction is all stored in the corresponding Cache space, the data searcher 1622 sends a Cache Start Address (Cache Start Address) and Length (Length) to the data accessor 1623. The data accessor 1623 then fetches the data to be fetched from the corresponding cache space according to the cache start address and length, and transfers the data fetched from the cache space to the host 120.
If only part of the data to be read by the read instruction is stored in the corresponding Cache space, the data searcher 1622 also sends a Cache Start Address (Cache Start Address) and a Length (Length) to the data accessor 1623, so that the data accessor 1623 can fetch the first part of the data to be read from the corresponding Cache space according to the Cache Start Address and the Length. In addition, the data accessor 1623 searches the logical-to-object mapping table stored in the dram 166 for a physical address of the second portion of data that is not in the cache space and is to be read, and reads the second portion of data from the flash memory 180 according to the obtained physical address. The data accessor 1623 then sends the first portion of data (from the cache space) and the second portion of data (from the flash memory 180) to the host 120.
As shown in FIG. 2A, if the write command from the host 120 has a start logical address of 16 and a sector number of 8 and has a stream identifier SID0, the data accessor 1623 may write data into the cache space 1630 according to the cache start address and length from the data searcher 1622, and the written data has a continuous logical address range, such as range 1631, in the cache space 1630.
As shown in FIG. 2B, if the read command from the host 120 also has a start logical address of 16 and a sector number of 8 and a stream ID of 0, the stream classifier 1621 can recognize the stream ID of 0, and the data finder 1622 can obtain or calculate the cache start address and length in the cache space 1630 stored by the stream ID of 0 and send it to the data accessor 1623. The data accessor 1623 retrieves data to be read from the cache space 1630 according to the cache start address and length from the data searcher 1622, and sends the retrieved data to the host 120 to complete the read operation.
For example, when both the host 120 and the data storage device 140 support nvme1.3 or more standards, the host 120 may enable command and stream (direct and Streams) functionality to issue i/o commands to the data storage device 140. In detail, in the architecture of the solid state disk, when the solid state disk carries write operations of multiple data streams, the write operations are disordered, that is, the solid state disk controller directly and continuously writes data into the flash memory regardless of the source of the write command. Since all the loads are mixed, the data from different sources are distributed in different areas of the flash memory in a staggered manner, which is quite disadvantageous for garbage collection operation.
In one embodiment, when the host 120 enables the functions of commands and Streams (direct and Streams) and issues i/o commands to the Data storage device 140, the i/o commands have a Stream identifier (Stream ID), wherein different Stream identifiers represent different types of Data, such as sequential Data or random Data, wherein the sequential Data can be classified as Log Data (Log Data), DataBase (DataBase), Multimedia Data (Multimedia Data), and the random Data can be metadata (Meta Data), System Files (System Files), etc., but the invention is not limited thereto. In some embodiments, the host 120 allocates the stream identifier according to the update frequency of different data,
FIG. 2C is a diagram illustrating a flash memory being written with a plurality of stream commands according to an embodiment of the present invention.
As shown in FIG. 2C, if the host 120 or the data storage device 140 does not support or turn on the command and stream functions and does not use the cache space, the computing unit 162 writes a mixture of data from different streams into different blocks 181, such as blocks 181A, 181B, 181D, and 181E, in the flash memory 180 after the streams 1, 2, and 3 (e.g., sequential write, and random write, respectively) from the host 120 are sent to the computing unit 162. In this example, blocks 181C and 181F are not written with data. However, it can be seen that the data in blocks 181A, 181B, 181D, and 181E are all mixed types of data, which are not placed in a manner that is conducive to garbage collection.
FIG. 2D is a diagram illustrating data being written into flash memories according to stream identifiers of stream commands according to an embodiment of the invention.
As shown in fig. 2D, if the host 120 or the data storage device 140 supports and enables command and stream functions and does not use the cache space, the stream 1, the stream 2, and the stream 3 (e.g., sequential write, and random write, respectively) from the host 120 are transmitted to the arithmetic unit 162, and the arithmetic unit 162 writes the data of the different streams into different blocks 181 of the flash memory 180 according to the stream identifiers (e.g., SID1, SID2, and SID3, respectively) corresponding to the different streams, for example, each page 1821 of the block 181A stores the data of the stream 1, each page 1822 of the block 181B stores the data of the stream 2, and each page 1823 of the block 181C stores the data of the stream 3. In this example, blocks 181D-181F are not written with data.
FIG. 2E is a diagram illustrating data being written into flash memories according to stream identifiers of stream commands according to an embodiment of the invention.
As shown in fig. 2E, if the host 120 or the data storage device 140 supports and enables command and stream functions and uses cache space, stream 1, stream 2, and stream 3 (e.g., sequential write, and random write, respectively) from the host 120 are transmitted to the arithmetic unit 162, the arithmetic unit 162 writes the data of different streams into different blocks 181 in the flash memory 180 according to stream identifiers (e.g., SID1, SID2, and SID3, respectively) corresponding to the different streams, e.g., each page 1821 in block 181A stores data of stream 1, each page 1822 in block 181B stores data of stream 2, and each page 1823 in block 181C stores data of stream 3. In this example, blocks 181D-181F are not written with data.
In addition, the cache controller 1620 further writes the data of stream 1, stream 2, and stream 3 into the cache spaces 211, 212, and 213 corresponding to the respective stream identifiers. As shown in FIG. 2E, cache space 211 stores data for page 1821 in block 181A, cache space 212 stores data for page 1822 in block 181B, and cache space 213 stores data for page 1823 in block 181C. When the cache controller 1620 receives a stream read command (e.g., the stream identifier is SID2) from the host 120, the cache controller 1620 determines that the data with the stream identifier SID2 has been written into the cache space 212, so that the desired data can be directly read from the cache space 212 and the read data is transmitted to the host 120 to complete the read operation.
FIG. 3 is a flow chart illustrating a cache splitting method for a data storage device according to an embodiment of the present invention.
In step S310, a corresponding cache space is allocated from the DRAM according to at least one data characteristic of the write command from the host 120. The at least one data characteristic includes a stream identifier, a namespace identifier, a data size, a logical address distribution, or a combination thereof of the write command.
In step S320, the data in the write command is written into the corresponding cache space. It should be noted that if the size of the cache space is sufficient to store all the data in the write command, the cache controller 1620 may write all the data in the write command into the cache space without writing the data into the flash memory 180. If the size of the cache space is not enough to store all the data in the write command, the cache controller 1620 writes a portion of the data in the write command into the cache space and writes the remaining data into the flash memory 180. The data written into the cache space is frequently accessed data or hot data, for example.
In step S330, in response to a read command from the host 120, it is determined whether all data to be read by the read command is stored in the cache space.
In step S340, when all the data to be read by the read instruction is stored in the cache space, the data corresponding to the read instruction is directly read from the cache space, and the read data is transmitted to the host 120 to complete the read operation.
It should be noted that when the cache space does not store all the data to be read by the read instruction, the cache controller 1620 further determines whether there is a portion of the data in the cache space to be read by the read instruction. If yes, the cache controller 1620 reads a portion of the data to be read by the read instruction from the cache space and reads the remaining data to be read by the read instruction from the flash memory 180. If not, the cache controller 1620 reads all data to be read by the read instruction from the flash memory 180.
However, the above description is only a preferred embodiment of the present invention, and the scope of the present invention should not be limited thereby, and all the simple equivalent changes and modifications made according to the claims and the description of the present invention are still within the scope of the present invention. Moreover, not all objects, advantages, or features of the disclosure are necessarily to be achieved in any one embodiment or claimed herein. In addition, the abstract and the title of the invention are provided for assisting the search of patent documents and are not intended to limit the scope of the invention.
