阅读说明：本技术 用于改进层间介电层形貌的方法 (Method for improving morphology of interlayer dielectric layer ) 是由 苏冠玮 黄俊育 林志勋 谢炳邦 于 2019-03-20 设计创作，主要内容包括：本文公开了用于改进层间介电(ILD)层形貌的方法和产生的集成电路器件。示例性方法包括在晶圆的第一区域上方形成具有第一厚度的第一接触蚀刻停止层,在晶圆的第二区域上方形成具有第二厚度的第二接触蚀刻停止层,并且在第一接触蚀刻停止层和第二接触蚀刻停止层上方形成ILD层。在第一区域和第二区域之间存在第一形貌变化。第二厚度与第一厚度不同,以实现小于第一形貌变化的第二形貌变化。第一形貌变化可以由设置在第一区域中的晶圆上方的第一栅极结构与设置在第二区域中的晶圆上方的第二栅极结构之间的高度差引起。本发明的实施例还涉及用于改进层间介电层形貌的方法。(Methods for improving inter-layer dielectric (ILD) layer topography and resulting integrated circuit devices are disclosed herein. An example method includes forming a first contact etch stop layer having a first thickness over a first region of a wafer, forming a second contact etch stop layer having a second thickness over a second region of the wafer, and forming an ILD layer over the first contact etch stop layer and the second contact etch stop layer. There is a first topographical variation between the first region and the second region. The second thickness is different from the first thickness to achieve a second topographical variation that is less than the first topographical variation. The first topography variation may be caused by a height difference between a first gate structure disposed over the wafer in the first region and a second gate structure disposed over the wafer in the second region. Embodiments of the invention also relate to methods for improving interlevel dielectric layer topography.)

1. A method of forming an integrated circuit device, comprising:

forming a first contact etch stop layer over a first region of a wafer, wherein there is a first topographical variation between the first region and a second region of the wafer, and the first contact etch stop layer has a first thickness;

forming a second contact etch stop layer over the second region of the wafer, wherein the second contact etch stop layer has a second thickness different from the first thickness to reduce the first topographical variation between the first region and the second region to a second topographical variation; and

forming an inter-layer dielectric (ILD) layer over the first and second contact etch stop layers.

2. The method of claim 1, wherein the second topographical variation is a difference in a height of a topmost surface of the first contact etch stop layer in the first region and a height of a topmost surface of the second contact etch stop layer in the second region, wherein the difference is less than or equal to 10%.

3. The method of claim 1, wherein:

forming the first contact etch stop layer comprises:

depositing the first contact etch stop layer over the first region and the second region, an

Etching the first contact etch stop layer from over the second region; and

forming the second contact etch stop layer comprises:

depositing the second contact etch stop layer over the first region and the second region, an

Etching the second contact etch stop layer from over the first region.

4. The method of claim 3, wherein:

forming the first contact etch stop layer further comprises:

performing a first photolithography process to form a first mask layer over the first contact etch stop layer over the first region, and

removing the first mask layer after etching the first contact etch stop layer from over the second region; and

forming the second contact etch stop layer further comprises:

performing a second photolithography process to form a second mask layer over the second contact etch stop layer over the second region, an

Removing the second mask layer after etching the second contact etch stop layer from over the first region.

5. The method of claim 1, wherein a first gate structure having a first height is disposed over the wafer in the first region and a second gate structure having a second height is disposed over the wafer in the second region, wherein the first topography variation is caused by the first height being different from the second height.

6. The method of claim 5, wherein the second topographical variation is caused by any difference between a first sum of the first height and the first thickness and a second sum of the second height and the second thickness.

7. The method of claim 1, wherein the first contact etch stop layer and the second contact etch stop layer comprise different materials.

8. The method of claim 1, wherein the first contact etch stop layer and the second contact etch stop layer comprise the same material.

9. A method of forming an integrated circuit device, comprising:

forming a first contact etch stop layer over a first gate structure having a first height, wherein the first contact etch stop layer has a first thickness;

forming a second contact etch stop layer over a second gate structure having a second height less than the first height, wherein the second contact etch stop layer has a second thickness greater than the first thickness; and

forming an inter-layer dielectric (ILD) layer over the first and second contact etch stop layers.

10. An integrated circuit device, comprising:

a first gate structure having a first height disposed over the substrate in the first region;

a second gate structure having a second height disposed above the substrate in a second region, wherein the second height is less than the first height;

a first contact etch stop layer disposed over the first gate structure, wherein the first contact etch stop layer has a first thickness;

a second contact etch stop layer disposed over the second gate structure, wherein the second contact etch stop layer has a second thickness greater than the first thickness, and the first and second contact etch stop layers overlap at an interface of the first and second regions; and

an interlayer dielectric layer disposed over the first contact etch stop layer and the second contact etch stop layer.

Technical Field

Embodiments of the invention relate to methods for improving interlevel dielectric layer topography.

Background

The Integrated Circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have resulted in generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometry (i.e., the smallest component (or line) that can be produced using a fabrication process) has decreased. Scaling down processes generally provides benefits by increasing production efficiency and reducing associated costs. However, such improvements have also increased the complexity of manufacturing ICs, and to achieve these advances, similar developments in IC processing and manufacturing are required.

For example, IC fabrication typically involves forming a device layer including individual IC devices on a wafer (substrate), and then forming multi-level interconnect (MLI) components over the device layer to facilitate operation of the individual IC devices. In some embodiments, the MLI feature includes an inter-layer dielectric (ILD) layer disposed over the device layer and an inter-metal dielectric (IMD) layer disposed over the ILD layer. The IMD layer includes conductive interconnect structures (e.g., metal interconnect structures) configured to route and/or distribute signals between the IC device and/or components of the IC device. Since the topography of the ILD layer conforms to the topography of the underlying layers, such as the device layers, any topography variations in the underlying layers are typically transferred to the ILD layer. For example, height variations in the IC device that result in topography variations in the device layer (in other words, some regions of the device layer are "higher" or "lower" than other regions) cause the ILD layer to exhibit topography variations even after a planarization process (e.g., a chemical mechanical polishing process) is performed. Such topographical variations may lead to reduced performance or even failure of the IC device. Thus, while existing IC fabrication methods are generally adequate for their intended purposes, they are not entirely satisfactory in all respects (e.g., in terms of adequate control of ILD topography).

Disclosure of Invention

An embodiment of the present invention provides a method of forming an integrated circuit device, comprising: forming a first contact etch stop layer over a first region of a wafer, wherein there is a first topographical variation between the first region and a second region of the wafer, and the first contact etch stop layer has a first thickness; forming a second contact etch stop layer over the second region of the wafer, wherein the second contact etch stop layer has a second thickness different from the first thickness to reduce the first topographical variation between the first region and the second region to a second topographical variation; and forming an interlayer dielectric (ILD) layer over the first contact etch stop layer and the second contact etch stop layer.

Another embodiment of the present invention provides a method of forming an integrated circuit device, comprising: forming a first contact etch stop layer over a first gate structure having a first height, wherein the first contact etch stop layer has a first thickness; forming a second contact etch stop layer over a second gate structure having a second height less than the first height, wherein the second contact etch stop layer has a second thickness greater than the first thickness; and forming an interlayer dielectric (ILD) layer over the first contact etch stop layer and the second contact etch stop layer.

Yet another embodiment of the present invention provides an integrated circuit device including: a first gate structure having a first height disposed over the substrate in the first region; a second gate structure having a second height disposed above the substrate in a second region, wherein the second height is less than the first height; a first contact etch stop layer disposed over the first gate structure, wherein the first contact etch stop layer has a first thickness; a second contact etch stop layer disposed over the second gate structure, wherein the second contact etch stop layer has a second thickness greater than the first thickness, and the first and second contact etch stop layers overlap at an interface of the first and second regions; and an interlayer dielectric layer disposed over the first contact etch stop layer and the second contact etch stop layer.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 is a flow diagram of a method for fabricating an integrated circuit device in accordance with various aspects of the present invention.

Fig. 2A-2L are partial cross-sectional views of a portion or all of an integrated circuit device in accordance with various aspects of the present invention.

Fig. 3 is a partial cross-sectional view of another integrated circuit device in accordance with some or all of the various aspects of the invention.

Detailed Description

The present invention relates generally to Integrated Circuit (IC) devices and, more particularly, to a method for improving interlayer dielectric layer (ILD) topography of an IC device.

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.

Further, the present invention may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Furthermore, in the present invention described below, the formation of one part on, connection to, and/or coupling to another part may include embodiments in which the parts are formed in direct contact, and may also include embodiments in which additional parts are formed interposed between the parts, such that the parts may not be in direct contact. Furthermore, spatially relative terms, such as "lower," "upper," "horizontal," "vertical," "above," "below," "upper," "lower," "top," "bottom," and the like, as well as derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.), are used for ease of description to describe one element of the invention's relationship to another element. Spatially relative terms are intended to encompass different orientations of the device in which the component is embodied.

As IC technology continues to evolve toward smaller technology nodes (e.g., 20nm, 16nm, 10nm, 7nm, and smaller), new manufacturing challenges arise. One such challenge relates to topography variations that occur during IC fabrication. Topographical variations occur when some regions of the wafer are "higher" (e.g., have a greater vertical height) than other regions of the wafer, and vice versa. The "higher" or "lower" regions may include various layers, such as semiconductor layers, dielectric layers, and/or conductive (e.g., metal) layers. Topography variations typically do not have an impact on older technology generations because the IC device dimensions of older technology generations either exceed or are large enough compared to the topography variations to suppress any impact and problems with the topography variations. Thus, conventional IC fabrication methods have not devised satisfactory solutions to address the challenges caused by topography variations in advanced technology nodes.

For example, IC fabrication typically involves forming a device layer including individual IC devices on a wafer (substrate), and then forming multi-level interconnect (MLI) components over the device layer to facilitate operation of the individual IC devices. In some embodiments, the MLI feature includes a Contact Etch Stop Layer (CESL) disposed over the device layer, an ILD layer disposed over the CESL layer, and an inter-metal dielectric (IMD) layer disposed over the ILD layer. The IMD layer includes conductive interconnect structures (e.g., metal interconnect structures) configured to route and/or distribute signals between the IC device and/or components of the IC device. Since the topography of the CESL and ILD layers conforms to the topography of the underlying layers (such as the device layers), any topography variations in the underlying layers are typically transferred to the ILD layers. For example, even after the planarization process is performed, height variations in the IC device that result in topography variations in the device layer (in other words, some regions of the device layer are "higher" or "lower" than other regions) result in the CESL layer (which typically has the same thickness over the various IC devices of the device layer) and the ILD layer also exhibiting topography variations. Such topographical variations may lead to degradation of the IC device or even failure of the IC device.

Accordingly, the present invention proposes to minimize the impact of topography variations of the device layer on topography variations of the ILD layer by implementing CESL of different thicknesses over device features of different heights. Topography variations in the device layer may be "smoothed" using CESL of different thicknesses over devices of different heights, thereby allowing the subsequently formed ILD layer to exhibit a "smoother" topography. Many advantages are described herein through the implementation of such techniques. Different embodiments may have different advantages, and no particular advantage is necessarily required of any embodiment.

Fig. 1 is a flow diagram of a method 10 for fabricating an integrated circuit device in accordance with various aspects of the present invention. In block 12, a first contact etch stop layer having a first thickness is formed over a first gate structure having a first height. In block 14, a second contact etch stop layer having a second thickness is formed over the second gate structure having the second height. The second height is less than the first height. The first thickness and the second thickness are configured to minimize topographical variations. For example, the second thickness is greater than the first thickness. In block 16, an ILD layer is formed over the first contact etch stop layer and the second contact etch stop layer. In block 18, the method 10 may continue to complete fabrication of the IC device. Fig. 1 has been simplified for clarity in order to better understand the inventive concepts of the present invention. Additional components may be added to method 10, and in other embodiments of method 10, some of the components described below may be replaced, modified, or eliminated.

Fig. 2A-2L are partial cross-sectional views of an IC device 100 at various stages of manufacture of a method, such as method 10 of fig. 1, in accordance with various aspects of the present invention. The IC device 100 may be included in a microprocessor, memory, and/or other IC device. In some embodiments, the IC device 100 is an IC chip, a portion of a system-on-a-chip (SoC), or a portion thereof, the IC device 100 including various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, etc,

p-type FETs (PFETs), n-type FETs (NFETs), metal-oxide-semiconductor FETs (MOSFETs), Complementary MOS (CMOS) transistors, Bipolar Junction Transistors (BJTs), Laterally Diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. The individual transistors are configured as planar transistors or as multi-gate transistors, such as fin fets (finfets), depending on the design requirements of the IC device 100. The IC device 100 includes a device region 102, a device region 104, a device region 106, and a device region 108. Each of the device regions 102-108 includes a respective active and/or passive microelectronic device configured to provide a core region (often referred to as a logic region), a memory region (such as a Static Random Access Memory (SRAM) region and/or a flash memory region), an analog region, a peripheral region (often referred to as an I/O region), a dummy region, other suitable regions, or combinations thereof. For example, device region 102 is a flash cell memory region (including one or more flash memories), device region 104 is a high voltage region (including one or more transistors), device region 106 is an I/O region (including one or more transistors), and device region 108 is a core region (including one or more transistors). In some embodiments, the high voltage region generally refers to a region of the IC device 100 that includes transistors operating at voltages greater than about 5V. In some embodiments, the IC device 100 includes a low voltage region, which generally refers to a region of the IC device 100 that includes transistors operating at a voltage of less than about 5V. Fig. 2A-2L have been simplified for clarity in order to better understand the inventive concepts of the present invention. Additional components may be added to the IC device 100 and some of the components described below may be replaced, modified, or eliminated in other embodiments of the IC device 100.

Turning to fig. 2A, the IC device 100 includes a substrate (wafer) 110. In the illustrated embodiment, the substrate 110 comprises silicon. Alternatively or additionally, the substrate 110 comprises another elemental semiconductor, such as germanium; a compound semiconductor such as silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, zinc oxide, zinc selenide, zinc sulfide, zinc telluride, cadmium selenide, cadmium sulfide, and/or cadmium telluride; alloy semiconductors such as SiGe, SiPC, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. Optionally, the substrate 110 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate may be fabricated by separation by implanted oxygen (SIMOX), wafer bonding, and/or other suitable methods. In some embodiments, the substrate 110 includes one or more III-V materials. In some embodiments, the substrate 110 includes one or more group II-IV materials.

Isolation features 112 are disposed above the substrate 110 and/or in the substrate 110 to isolate various device regions of the IC device 100. For example, isolation features 112 separate and isolate active device regions and/or passive device regions (such as device regions 102-108) from each other. The isolation feature 112 comprises silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., comprising silicon, oxygen, nitrogen, carbon, or other suitable isolation compositions), or combinations thereof. The isolation feature 112 may include different structures such as a Shallow Trench Isolation (STI) structure, a Deep Trench Isolation (DTI) structure, and/or a local oxidation of silicon (LOCOS) structure. In some embodiments, the STI features may be formed by etching trenches in the substrate 110 (e.g., by using a dry etch process and/or a wet etch process) and filling the trenches with an insulating material (e.g., by using a chemical vapor deposition process or a spin-on-glass process). A Chemical Mechanical Polishing (CMP) process may be performed to remove excess insulating material and/or to planarize the top surface of the isolation features 112. In some embodiments, the STI features may be formed by depositing an insulating material over the substrate 110 after forming the fins, such that a layer of insulating material fills the gaps (trenches) between the fins, and etching back the layer of insulating material to form the isolation features 112. In some embodiments, the isolation feature 112 comprises a multi-layer structure filling a trench, such as a bulk dielectric layer disposed over a liner dielectric layer, wherein the bulk dielectric layer and the liner dielectric layer comprise a material that depends on design requirements (e.g., the bulk dielectric layer disposed over the liner dielectric layer comprising a thermal oxide comprises silicon nitride). In some embodiments, the isolation feature 112 includes a dielectric layer disposed over a doped liner layer (including, for example, borosilicate glass or phosphosilicate glass).

The substrate 110 includes various doped regions configured according to the design requirements of the IC device 100. For example, substrate 110 includes doped region 114, doped region 116, doped region 118, and doped region 120. Each of the doped regions 114 to 120 is an n-type doped region (also referred to as an n-well) or a p-type doped region (also referred to as a p-well), depending on the type of device disposed in the respective device region 104 to 108. The N-type doped region is doped with an N-type dopant, such as phosphorus, arsenic, other N-type dopants, or combinations thereof. The P-type doped region is doped with a P-type dopant, such as boron (e.g., BF)₂) Indium, other p-type dopants, or combinations thereof. In some embodiments, one or more of the doped regions 114-120 includes a combination of p-type dopants and n-type dopants. The doped regions 114 to 120 may be formed directly on the substrate 110 and/or in the substrate 110, for example, providing a p-well structure, an n-well structure, a dual-well structure, a raised structure, or a combination thereof. An ion implantation process, a diffusion process, and/or other suitable doping processes may be performed to form the doped regions 114-120.

Various gate structures are disposed over substrate 110, such as gate structure 124A, gate structure 124B, gate structure 124C, gate structure 124D, and gate structure 124E. Various deposition processes, photolithography processes, etching processes, other suitable processes, or combinations thereof may be performed to fabricate the gate stacks of the gate structures 124A-124E. Deposition processes include CVD, Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), high density plasma CVD (hdpcvd), metal organic CVD (mocvd), remote plasma CVD (rpcvd), plasma enhanced CVD (pecvd), low pressure CVD (lpcvd), atomic layer CVD (alcvd), atmospheric pressure CVD (apcvd), plating, other suitable methods, or combinations thereof. The lithographic patterning process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), other suitable processes, or combinations thereof. Alternatively, the lithography process is assisted, implemented, or replaced by other methods (e.g., maskless lithography, electron beam writing, and ion beam writing). The etching process includes a dry etching process, a wet etching process, other etching processes, or a combination thereof.

The gate structures 124A-124E include gate stacks configured to perform a desired function according to design requirements of the IC device 100 such that the gate structures 124A-124E include the same or different layers and/or materials. For example, gate structures 124A, 124B are configured to form portions of respective flash memory cells, and gate structures 124C-124E are configured to form portions of respective transistors. The gate structures 124A, 124B each have a height H1, height H1 representing the combined thickness of the various layers of the gate stack of the gate structures 124A, 124B. Height H1 extends from the top surface of substrate 110 to the top surface of the gate stack of gate structures 124A, 124B. The gate structures 124C-124E each have a height H2, height H2 representing the combined thickness of the various layers of the gate stack of the gate structures 124C-124E. Height H2 extends from the top surface of substrate 110 to the top surface of the gate stack of gate structures 124C-124E. In the illustrated embodiment, height H1 is greater than height H2, which results in a topographical variation Δ between device region 102 and device regions 104 through 108₁. Change in morphology Δ₁Is the difference between height H1 and height H2 (in other words, Δ₁H1-H2). Can change the topography by₁To subsequently formed layers of the IC device 100, which may degrade the performance of the IC device 100. The present invention provides a solution to the problem presented by such topographical variationsThe solution to warfare is described below. In some embodiments, height H1 is greater than or equal to about

And height H2 is less than about

(e.g., about

). In some embodiments, the topographical variation Δ₁Is the distance (or height) between the top surface of the tallest component in device region 102 and the top surface of the tallest component in device regions 104 through 108. In some embodiments, the gate structures 124A-124E may be collectively referred to as a device layer, wherein the device layer includes high topography regions (here, device regions 102) and low topography regions (here, device regions 104-108).

Gate structure 124A has a gate stack that includes tunnel oxide layer 126a, floating gate layer 128a, dielectric layer 130a, control gate layer 132a, and hard mask layer 134A. Gate structure 124B has a gate stack that includes tunnel oxide layer 126B, floating gate layer 128B, dielectric layer 130B, control gate layer 132B, and hard mask layer 134B. The tunnel oxide layers 126a, 126b are disposed over the substrate 110 and comprise any suitable material, such as silicon and/or oxygen (e.g., silicon oxide). Floating gate layers 128a, 128b are disposed on tunnel oxide layers 126a, 126b, respectively, and comprise a conductive material, such as polysilicon. In some embodiments, floating gate layers 128a, 128b may include nano-islands comprising semiconductor materials, such as silicon and/or germanium. Dielectric layers 130a, 130b are disposed on floating gate layers 128a, 128b, respectively, and comprise a dielectric material. In some embodiments, the dielectric layers 130a, 130b comprise a multi-layer structure, such as an oxide-nitride-oxide (ONO) structure. For example, dielectric layers 130a, 130b may include a first silicon-and-oxygen-containing layer disposed over floating gate layer 128a, 128b, a silicon-and-nitrogen-containing layer disposed over the first silicon-and-oxygen-containing layer, and a second silicon-and-oxygen-containing layer disposed over the silicon-and-nitrogen-containing layer. Control gate layers 132a, 132b are disposed on dielectric layers 130a, 130b, respectively, and comprise a conductive material, such as polysilicon. In some embodiments, the gate stack of the gate structures 124a, 124b may include various material combinations, such as metal-oxide-nitride-oxide-silicon (MONOS), silicon-oxide-nitride-silicon (SONOS), silicon-nitride-oxide-silicon (SNOS), metal-nitride-oxide-silicon (MNOS), or other suitable material combinations. Hard mask layers 134a, 134b are disposed on respective control gate layers 132a, 132b and comprise any suitable material, such as silicon, nitrogen, and/or carbon (e.g., silicon nitride or silicon carbide). In the illustrated embodiment, the top surface of the gate stack of the gate structures 124A, 124B is the top surface of the respective hard mask layers 134A, 134B, such that the height H1 extends from the top surface of the substrate 110 to the top surfaces of the hard mask layers 134A, 134B.

Gate structure 124C has a gate stack that includes an interfacial layer 136a, a gate dielectric 138a, a gate electrode 140a, and a hard mask layer 142 a; gate structure 124D has a gate stack that includes an interfacial layer 136b, a gate dielectric 138b, a gate electrode 140b, and a hard mask layer 142 b; and gate structure 124E has a gate stack that includes an interfacial layer 136c, a gate dielectric 138c, a gate electrode 140c, and a hard mask layer 142 c. Since the gate structures 124C-124E correspond to different transistors, the gate structures 124C-124E may include different numbers, configurations, and/or layers of materials for the interfacial layers 136 a-136C, the gate dielectrics 138 a-138C, the gate electrodes 140 a-140C, and/or the hard mask layers 142 a-142C. For example, to optimize the performance of the transistor in device region 104 (here, the high voltage region), the thickness of gate dielectric 138a is greater than the thickness of gate dielectric 138b and/or gate dielectric 138 c. The gate stack of gate structures 124C-124E is fabricated according to a gate-last process, a gate-first process, or a hybrid gate-last/gate-first process. In a gate last process embodiment, the one or more gate structures 124C-124E include dummy gate stacks that are subsequently replaced with metal gate stacks. The dummy gate stack includes, for example, an interface layer (including, for example, silicon oxide) and a dummy gate electrode layer (including, for example, polysilicon). In such embodiments, the dummy gate electrode layer is removed to form openings (trenches) in which the gate dielectrics 138a to 138c and/or the gate electrodes 140a to 140c are subsequently formed.

The interface layers 136 a-136 c are disposed on the substrate 110 and comprise any suitable material, such as silicon and/or oxygen (e.g., silicon oxide). Gate dielectrics 138 a-138 c are conformally disposed on the surfaces defined by the respective interface layers 136 a-136 c and the respective gate stacks such that the gate dielectrics 138 a-138 c have a substantially uniform thickness. The gate dielectrics 138 a-138 c comprise dielectric materials such as silicon oxide, high-k dielectric materials, other suitable dielectric materials, or combinations thereof. High-k dielectric materials generally refer to dielectric materials having a high dielectric constant, e.g., greater than the dielectric constant of silicon oxide (k ≈ 3.9). Exemplary high-k dielectric materials include hafnium, aluminum, zirconium, lanthanum, tantalum, titanium, yttrium, oxygen, nitrogen, other suitable compositions, or combinations thereof. In some embodiments, the gate dielectrics 138 a-138 c may comprise a high-k dielectric layer, including, for example, HfO₂、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO₂、Al₂O₃、HfO₂-Al₂O₃、TiO₂、Ta₂O₅、La₂O₃、Y₂O₃Other suitable high-k dielectric materials, or combinations thereof. Gate electrodes 140 a-140 c are disposed on the respective gate dielectrics 138 a-138 c. The gate electrodes 140a to 140c include a conductive material. In some embodiments, gate electrodes 140 a-140 c include multiple layers, such as one or more capping layers, work function layers, glue/barrier layers, and/or metal fill (or bulk) layers. The capping layer may include a material that prevents or eliminates diffusion and/or reaction of constituents between the gate dielectrics 138 a-138C and other layers of the gate structures 124C-124E. In some embodiments, the capping layer includes a metal and nitrogen, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (W)₂N), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), or combinations thereof. The work function layer includes a conductive material, such as an n-type work function material and/or a p-type work function, tuned to have a desired work function, such as an n-type work function or a p-type work functionA letter material. The P-type work function material comprises TiN, TaN, Ru, Mo, Al, WN and ZrSi₂、MoSi₂、TaSi₂、NiSi₂WN, other p-type work function materials, or combinations thereof. The N-type work function material comprises Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, other N-type work function materials, or combinations thereof. The glue/barrier layer may comprise a material that promotes adhesion between adjacent layers, such as a work function layer and a metal fill layer, and/or a material that blocks and/or reduces diffusion between gate layers, such as a work function layer and a metal fill layer. For example, the glue/barrier layer includes a metal (e.g., W, Al, Ta, Ti, Ni, Cu, Co, other suitable metals, or combinations thereof), a metal oxide, a metal nitride (e.g., TiN), or combinations thereof. The metal fill layer may comprise a suitable conductive material, such as Al, W, and/or Cu. Hard mask layers 142 a-142 c are disposed on respective gate dielectrics 138 a-138 c and respective gate electrodes 140 a-140 c. The hard mask layers 142 a-142 c comprise any suitable material, such as silicon, nitrogen, and/or carbon (e.g., silicon nitride or silicon carbide). In the illustrated embodiment, the top surface of the gate stack of gate structures 124C-124E is the top surface of the respective hard mask layers 142 a-142C, such that height H2 extends from the top surface of substrate 110 to the top surfaces of the hard mask layers 142 a-142C.

The gate structures 124A-124E also include respective gate spacers, such as gate spacer 144A, gate spacer 144b, gate spacer 144c, gate spacer 144d, and gate spacer 144E. The gate spacers 144 a-144 e are disposed adjacent to (e.g., along sidewalls of) the respective gate stacks. The gate spacers 144 a-144 e are formed by any suitable process and comprise a dielectric material. The dielectric material may include silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). For example, in the illustrated embodiment, a dielectric layer comprising silicon and nitrogen, such as a silicon nitride layer, may be deposited over the substrate 110 and the gate stack of the gate structures 124A-124E, and then anisotropically etched to form the gate spacers 144A-144E. In some embodiments, the gate spacers 144 a-144 e comprise a multi-layer structure, such as a first dielectric layer comprising silicon nitride and a second dielectric layer comprising silicon oxide. In some embodiments, the gate spacers 144 a-144 e include more than one set of spacers formed adjacent to the gate stack, such as seal spacers, offset spacers, sacrificial spacers, dummy spacers, and/or main spacers. In such embodiments, each set of spacers may comprise a material having a different etch rate. For example, a first dielectric layer comprising silicon and oxygen may be deposited over substrate 110 and then anisotropically etched to form a first set of spacers adjacent to the gate stack, and a second dielectric layer comprising silicon and nitrogen may be deposited over substrate 110 and then anisotropically etched to form a second set of spacers adjacent to the first set of spacers. In some embodiments, the gate spacers 144 a-144 e comprise the same or different materials, layers, groups, and/or configurations depending on the design requirements of the IC device 100.

Respective source/drain features 146 are disposed in the substrate 110. In the illustrated embodiment, each of the gate structures 124A-124E is disposed over the substrate 110 such that each of the gate structures 124A-124E is interposed between source/drain features 146. A channel region disposed in the substrate 110 may span between the source/drain features 146, beneath each of the gate structures 124A-124E, so that current may flow between the respective source/drain features 146 during operation. The source/drain features 146 include lightly doped source and drain (LDD) features and/or heavily doped source and drain (HDD) features, which may be formed before and/or after the formation of the gate spacers 144 a-144 e. In some embodiments, the source/drain features 146 are formed by implanting and/or diffusing n-type dopants, p-type dopants, or a combination thereof into the substrate 110, depending on the desired transistor configuration (e.g., PMOS or NMOS). An annealing process, such as a Rapid Thermal Anneal (RTA) and/or a laser anneal, may be performed to activate the dopants of the source/drain features 146. Source/drain features 146 may also include epitaxial source/drain features disposed on substrate 110 and/or in substrate 110. For example, a semiconductor material is epitaxially grown on the substrate 110 such that the epitaxial source/drain features are fully embedded or partially embedded (e.g., have a top surface that is higher than the top surface of the substrate 110). The epitaxial process may implement CVD deposition techniques (e.g., Vapor Phase Epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD, and/or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The epitaxial process may use gaseous and/or liquid precursors that interact with the components of the substrate 110. The epitaxial source/drain features may comprise any suitable material, such as silicon and/or germanium, and may comprise n-type dopants and/or p-type dopants. In some embodiments, the epitaxial source/drain features may include a silicon-and germanium-containing layer (e.g., a Si: Ge: B epitaxial layer or a Si: Ge: C epitaxial layer) doped with boron, carbon, other p-type dopants, or a combination thereof. In some embodiments, the epitaxial source/drain features may include a silicon-or silicon-containing carbon layer (e.g., a Si: P epitaxial layer, a Si: C epitaxial layer, or a Si: C: P epitaxial layer) doped with phosphorus, arsenic, other n-type dopants, or a combination thereof. In some embodiments, the epitaxial source/drain features include materials and/or dopants that achieve a desired tensile and/or compressive stress in the channel region. In some embodiments, the epitaxial source/drain features are doped during deposition by adding impurities to the source material of the epitaxial process. In some embodiments, the epitaxial source/drain features are doped by an ion implantation process after the deposition process.

A silicide layer 148 is formed on the source/drain features 146. In some embodiments, silicide layer 148 is formed by depositing a metal layer over source/drain features 146. The metal layer comprises any material suitable for promoting silicide formation, such as nickel, platinum, palladium, vanadium, titanium, cobalt, tantalum, ytterbium, zirconium, other suitable metals, or combinations thereof. The IC device 100 is then heated (e.g., subjected to an annealing process) to react the constituents (e.g., silicon and/or germanium) of the source/drain features 146 with the metal. Thus, silicide layer 148 includes metal and the composition of source/drain features 146 (e.g., silicon and/or germanium). In some embodiments, silicide layer 148 includes nickel silicide, titanium silicide, or cobalt silicide. Any unreacted metal, such as the remaining portion of the metal layer, is selectively removed by any suitable process, such as an etching process.

Turning to fig. 2B, a Contact Etch Stop Layer (CESL)150 is formed over the IC device 100, specifically over the gate structures 124A-124E in the device regions 102-108. In some embodiments, the CESL150 is conformally deposited over the gate structures 124A-124E such that the CESL150 has substantially the same thickness over the gate structures 124A-124E and various other IC features (such as the isolation features 112 and/or the source/drain features 146). In the illustrated embodiment, CESL150 has a thickness C1 over gate structures 124A-124E. In some embodiments, the thickness C1 is about

To about(e.g., about

). Other thickness profiles of CESL150 are contemplated by the present invention. For example, in some embodiments, the thickness of the CESL150 disposed on the top surface of the gate stack of the gate structures 124A-124E is greater than the thickness of the CESL150 disposed on the top surface of the spacers 144A-144E. CESL150 includes a material having different etch characteristics than other features of IC device 100, such as hardmask layers 134a, 134b, hardmask layers 142 a-142 c, gate spacers 144 a-144 e, and/or subsequently formed ILDs. In some embodiments, CESL150 comprises silicon, oxygen, nitrogen, carbon, other suitable CESL components, or combinations thereof. For example, CESL150 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or other suitable CESL material. In the illustrated embodiment, CESL150 includes silicon and nitrogen, such as silicon nitride. In some embodiments, CESL150 comprises a material configured to achieve a desired stress (such as tensile stress or compressive stress), depending on the type of transistor in IC device 100 over which CESL150 is to remain. In some embodiments, CESL150 has a multilayer structure, including, for example, more than one layer of material.The CESL150 is formed by CVD, PECVD, sub-atmospheric CVD (sacvd), LPCVD, ALD, plasma enhanced ALD (peald), Molecular Layer Deposition (MLD), plasma pulse CVD (picvd), other suitable methods, or combinations thereof.

Turning to fig. 2C, a mask layer 160 is formed over CESL150 in the high topography region of the IC device 100. For example, the mask layer 160 covers the device region 102 including the gate structures 124A, 124B having the height H1. The opening 162 of the mask layer 160 exposes the CESL150 in low profile regions of the IC device 100, such as the device regions 104-108 including the gate structures 124C-124E having the height H2. The mask layer 160 serves as a CESL cut mask for removing the CESL150 from low profile regions of the IC device 100. In the illustrated embodiment, the mask layer 160 is a photoresist layer, which is also referred to as a resist layer, a photosensitive layer, an imaging layer, a patterned layer, and/or a radiation sensitive layer. Accordingly, the mask layer 160 comprises a material that is sensitive to radiation used during a lithographic exposure process, such as DUV radiation, EUV radiation, electron beam radiation, ion beam radiation, and/or other suitable radiation. Optionally, in some embodiments, mask layer 160 comprises a material having different etch characteristics than CESL150, such as silicon, amorphous silicon, a semiconductor oxide (e.g., silicon oxide (SiO), for example)₂) Silicon nitride (SiN), semiconductor oxynitrides (SiON), and/or semiconductor carbides (SiC), other semiconductor materials, and/or other dielectric materials. In some embodiments, the mask layer 160 has a multi-layer structure. For example, mask layer 160 may include a mask barrier layer disposed over CESL150, and a mask layer disposed over the mask barrier layer. The mask barrier layer may comprise a material having a high etch resistance, such as a material comprising titanium and nitrogen (e.g., TiN), that achieves a desired etch selectivity (e.g., between the mask barrier layer and the mask layer), and the mask layer may comprise a material that achieves the desired etch selectivity (e.g., between the mask layer and CESL 150).

The mask layer 160 is formed by a photolithography process. For example, in some embodiments, mask layer 160 is formed by spin coating a liquid photoresist material onto CESL 150. After spin-coating the liquid photoresist material (but before performing the exposure process), a pre-bake process may be performed on the mask layer 160, for example, to evaporate the solvent and densify the liquid photoresist material formed over the CESL 150. In some embodiments, an ARC layer is formed over CESL150 prior to forming mask layer 160, such that mask layer 160 is formed over the ARC layer. The ARC layer may be a nitrogen-free ARC (nfarc) layer that includes materials such as silicon oxide, silicon oxycarbide, PECVD silicon oxide, other suitable materials, or combinations thereof. In some embodiments, more than one layer (including one or more ARC layers) may be formed between mask layer 160 and CESL 150. The opening 162 is then formed by an exposure process. During the exposure process, the mask layer 160 is irradiated with radiation (such as UV light, DUV light, or EUV light), wherein the mask blocks, transmits, and/or reflects the radiation to the mask layer 160 according to a mask pattern and/or a mask type of the mask (e.g., a binary mask, a phase-shift mask, or an EUV mask), thereby projecting an image corresponding to the mask pattern onto the mask layer 160. In the illustrated embodiment, the radiation is patterned using a mask having a CESL cut pattern defined therein, such that the patterned radiation forms an image of the CESL cut pattern on the mask layer 160. Since the mask layer 160 is sensitive to radiation, the exposed portions of the mask layer 160 are physically and/or chemically altered in response to the exposure process, thereby causing the exposed portions to increase or decrease in solubility to a developer. In some embodiments, after the exposure process, a post-exposure bake (PEB) process is performed on the mask layer 160. A development process is then performed to dissolve the exposed (or unexposed) portions of the mask layer 160, depending on the characteristics of the mask layer 160 and the characteristics of the developing solution used in the development process. In some embodiments, a rinsing process is performed after the developing process, e.g., to remove any residues and/or particles from the IC device 100. In some embodiments, a post-development bake (PDB) process is performed on the mask layer 160. Alternatively, the lithographic exposure process may be implemented or replaced by other methods, such as maskless lithography, e-beam writing, ion-beam writing, and nanoimprint techniques. In such embodiments, an image may be projected onto the mask layer 160 by directly modulating the radiation according to the CESL cutting pattern.

Turning to fig. 2D, the CESL150 is removed from the low-profile region of the IC device 100. For example, the CESL150 is removed from the device regions 104-108 including the gate structures 124C-124E having the height H2, thereby exposing the gate structures 124C-124E. In the illustrated embodiment, an etch process is performed to remove CESL150, wherein the mask layer 160 serves as an etch mask that protects the CESL150 in high profile regions of the IC device 100 during the etch process. The etching process is a wet etching process, a dry etching process, other suitable etching process, or a combination thereof. In some embodiments, the etching process selectively etches the CESL150 without substantially etching the mask layer 160, the silicide layer 148, the gate spacers 144 c-144 e, and/or the hard mask layers 142 a-142 c.

Turning to fig. 2E, the mask layer 160 is removed from the high topography regions of the IC device 100. The mask layer 160 is removed, for example, by a photoresist strip process, thereby exposing the CESL150 disposed over the device region 102 (specifically, disposed over the gate structures 124A, 124B). In some embodiments, the mask layer 160 is removed by an etching process, other suitable process, or a combination thereof. The remaining CESL150 changes the surface topography of the IC device 100. In the illustrated embodiment, the CESL150 increases the topography variation between the device region 102 and the device regions 104-108 because the CESL150 remains over a high topography region of the IC device 100. For example, the topography variation Δ between device region 102 and device regions 104 through 108₂Greater than the change in morphology Δ₁. Change in morphology Δ₂Is the difference between the height H1 of the gate structures 124A, 124B and the sum of the thickness C1 disposed above the gate structures 124A, 124B and the height H2 of the gate structures 124C-124E (in other words, Δ 2 ═ H1+ C1) -H2). Thus, the topography change Δ₂Is the distance (or height) between the top surface of the CESL150 in the device region 102 and the top surface of the hard mask layers 142 a-142 c in the device regions 104-108. In some embodiments, the topographical variation Δ₂Is the distance (or height) between the top surface of the tallest component in device region 102 and the top surface of the tallest component in device regions 104 through 108.

Turning to fig. 2F, CESL170 is formed over the IC device 100, specifically over the gate structures 124A-124E in the device regions 102-108. In the illustrated embodiment, CESL170 is formed over CESL150 in device region 102. In some embodiments, the CESL170 is conformally deposited over the IC components of the IC device 100 such that the CESL170 has substantially the same thickness over the CESL150, the gate structures 124C-124E, and various other IC components, such as the isolation components 112 and/or the source/drain components 146. In the illustrated embodiment, CESL170 has a thickness C2 over gate structures 124C-124E. Thickness C2 is configured to minimize topographical variations between device region 102 and device regions 104 through 108. For example, in the illustrated embodiment, the thickness C2 is greater than the thickness C1. In some embodiments, the thickness C2 is about

To about

(e.g., about

). Other thickness profiles of CESL170 are contemplated by the present invention. For example, in some embodiments, the thickness of CESL170 disposed on the top surfaces of gate structures 124C-124E and/or CESL150 is greater than the thickness of CESL170 disposed on the top surfaces of spacers 144 a-144E. CESL170 comprises a material having different etch characteristics than other features of IC device 100, such as hardmask layers 134a, 134b, hardmask layers 142 a-142 c, gate spacers 144 a-144 e, CESL150, and/or subsequently formed ILDs. In some embodiments, CESL170 comprises silicon, oxygen, nitrogen, carbon, other suitable CESL components, or combinations thereof. For example, CESL170 comprises silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or other suitable CESL material. In some embodiments, CESL170 comprises the same material as CESL 150. In some embodiments, CESL170 comprises a different material than CESL 150. In the illustrated embodiment, CESL170 includes silicon and nitrogen, such as silicon nitride. In some embodimentsDepending on the type of transistor in the IC device 100 over which the CESL170 is to remain, the CESL170 comprises a material configured to achieve a desired stress (such as a tensile stress or a compressive stress). In some embodiments, CESL170 has a multilayer structure including, for example, more than one layer of material. CESL170 is formed by CVD, PECVD, SACVD, LPCVD, ALD, PEALD, MLD, PICVD, other suitable methods, or combinations thereof.

Turning to fig. 2G, a mask layer 180 is formed over CESL170 in the low profile region of the IC device 100. For example, masking layer 180 covers device regions 104-108 including gate structures 124C-124E having height H2. The opening 182 of the mask layer 180 exposes the CESL170 in high topography regions of the IC device 100, such as the device region 102 including the gate structures 124A, 124B having a height H2. The mask layer 180 serves as a CESL cut mask for removing the CESL170 from high topography regions of the IC device 100. In the embodiment shown, the mask layer 180 is a photoresist layer. Thus, mask layer 180 comprises a material that is sensitive to radiation used during a lithographic exposure process, such as DUV radiation, EUV radiation, electron beam radiation, ion beam radiation, and/or other suitable radiation. Optionally, in some embodiments, mask layer 180 comprises a material having different etch characteristics than CESL170, such as silicon, amorphous silicon, a semiconductor oxide (e.g., SiO), or a combination thereof₂) Semiconductor nitrides (e.g., SiN), semiconductor oxynitrides (e.g., SiON), and/or semiconductor carbides (e.g., SiC), other semiconductor materials, and/or other dielectric materials. In some embodiments, the mask layer 180 has a multi-layer structure. For example, mask layer 180 may include a mask barrier layer disposed over CESL170, and a mask layer disposed over the mask barrier layer. The mask barrier layer may comprise a material having a high etch resistance, such as a material comprising titanium and nitrogen (e.g., TiN), that achieves a desired etch selectivity (e.g., between the mask barrier layer and the mask layer), and the mask layer may comprise a material that achieves the desired etch selectivity (e.g., between the mask layer and CESL 170).

The mask layer 180 is formed by a photolithography process. For example, in some embodiments, by mixing a liquidA photoresist material is spin coated onto CESL170 to form mask layer 180. After spin-coating the liquid photoresist material (but before performing the exposure process), a pre-bake process may be performed on the mask layer 180, for example, to evaporate the solvent and densify the liquid photoresist material formed over the CESL 170. In some embodiments, an ARC layer is formed over CESL170 prior to forming mask layer 180, such that mask layer 180 is formed over the ARC layer. The ARC layer may be an NFARC layer comprising, for example, SiO₂、SOC、PECVD-SiO₂Other suitable materials, or combinations thereof. In some embodiments, more than one layer (including one or more ARC layers) may be formed between masking layer 180 and CESL 170. The opening 182 is then formed by an exposure process. During the exposure process, the mask layer 180 is irradiated with radiation (such as UV light, DUV light, or EUV light), wherein the mask blocks, transmits, and/or reflects the radiation to the mask layer 180 according to a mask pattern and/or a mask type of the mask (e.g., a binary mask, a phase-shift mask, or an EUV mask), thereby projecting an image corresponding to the mask pattern onto the mask layer 180. In the illustrated embodiment, the radiation is patterned using a mask having a CESL cut pattern defined therein, such that the patterned radiation forms an image of the CESL cut pattern on the mask layer 180. Since the mask layer 180 is sensitive to radiation, the exposed portions of the mask layer 180 are physically and/or chemically altered in response to the exposure process, thereby causing the exposed portions to increase or decrease in solubility to a developer. In some embodiments, the mask layer 180 is subjected to a PEB process after the exposure process. A development process is then performed to dissolve the exposed (or unexposed) portions of the mask layer 180, depending on the characteristics of the mask layer 180 and the characteristics of the developing solution used in the development process. In some embodiments, a rinsing process is performed after the developing process, e.g., to remove any residues and/or particles from the IC device 100. In some embodiments, a PDB process is performed on the mask layer 180. Alternatively, the lithographic exposure process may be implemented or replaced by other methods, such as maskless lithography, e-beam writing, ion-beam writing, and nanoimprint techniques. In such embodiments, the radiation may be directly modulated by cutting the pattern according to CESLAn image is projected onto the mask layer 180.

Turning to fig. 2H, CESL170 is removed from the high topography region of the IC device 100. For example, CESL170 is removed from the device region 102 including the gate structures 124A, 124B having height H1, thereby exposing the CESL 150. In the illustrated embodiment, an etch process is performed to remove CESL170, wherein the mask layer 180 serves as an etch mask that protects the CESL170 in low-profile regions of the IC device 100 during the etch process. The etching process is a wet etching process, a dry etching process, other suitable etching process, or a combination thereof. In some embodiments, the etching process selectively etches CESL170 without substantially etching mask layer 180 and/or CESL 150.

Turning to fig. 2I, the mask layer 180 is removed from the low profile regions of the IC device 100. The mask layer 180 is removed, for example, by a photoresist strip process, thereby exposing the CESL170 disposed over the device regions 104-108 (specifically, disposed over the gate structures 124C-124E). In some embodiments, the mask layer 180 is removed by an etching process, other suitable process, or a combination thereof. The remaining CESL170 changes the surface topography of the IC device 100. In the illustrated embodiment, the CESL170 reduces the topography variation between the device region 102 and the device regions 104-108 because the CESL170 remains over a low topography region of the IC device 100 and the CESL170 has a thickness C2 (which is greater than the thickness C1). For example, the topography variation Δ between device region 102 and device regions 104 through 108₃Less than a change in topography Δ₁. Change in morphology Δ₃Is the difference between the sum of the height H1 of the gate structures 124A, 124B and the thickness C1 of the CESL150 disposed over the gate structures 124A, 124B and the sum of the height H2 of the gate structures 124C-124E and the thickness C2 of the CESL170 disposed over the gate structures 124C-124E (in other words, Δ₃(H1+ C1) - (H2+ C2)). Thus, the topography change Δ₃Is the distance (or height) between the top surface of the CESL150 in the device region 102 and the top surface of the CESL170 in the device regions 104-108. In some embodiments, thickness C1 and thickness are such as to ensure that the device layer exhibits a topography that will minimize (or eliminate) topographical variations in subsequently formed layers, such as subsequently formed ILD layersThe degree C2 is configured to achieve a topography change Δ less than or equal to about 10%₃. In some embodiments, thickness C2 of CESL170 is configured to eliminate any topographical variations (e.g., Δ) between device region 102 and device regions 104-108₃0). In some embodiments, the topographical variation Δ₃Is the distance (or height) between the top surface of the tallest component in device region 102 and the top surface of the tallest component in device regions 104 through 108.

Turning to fig. 2J, an ILD layer 190 is formed over the IC device 100, specifically over CESL150 and CESL 170. In some embodiments, ILD layer 190 is about thick

To about

ILD layer 190 comprises a dielectric material including, for example, silicon oxide, silicon nitride, silicon oxynitride, oxides formed from TEOS, PSG, BPSG, low-k dielectric material, other suitable dielectric materials, or combinations thereof. Exemplary low-k dielectric materials include FSG, carbon-doped silicon oxide, Black

(applied materials of Santa Clara, Calif.), xerogels, aerogels, amorphous fluorinated carbons, parylene, BCB, SiLK (Dow chemical company of Mitland, Mich.), polyimides, other low-k dielectric materials, or combinations thereof. In the illustrated embodiment, the ILD layer 190 comprises a low-k dielectric material (commonly referred to as a low-k dielectric layer). In some embodiments, a low-k dielectric material generally refers to a material having a dielectric constant (k) of less than about 3. In some embodiments, ILD layer 190 has a multilayer structure comprising a plurality of dielectric materials. The ILD layer 190 is formed over the CESL150 and the CESL170 by a deposition process such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable deposition processes, or a combination thereof. In some embodiments, ILD layer 190 is formed by a flowable CVD (fcvd) process, including for exampleSuch as depositing a flowable material (such as a liquid compound) over CESL150 and CESL170 and converting the flowable material to a solid material by a suitable technique, such as thermal annealing or ultraviolet radiation treatment.

A top surface 192 of ILD layer 190 exhibits a surface profile 194. The topography variation Δ of ILD layer 190 at the interface region 196 of high topography regions (here device regions 102) and low topography regions (here device regions 104) is minimized because the topography of ILD layer 190 conforms to the topography of the device layers below it₄This is because the proposed method utilizes CESL of different thicknesses (here, thickness C1 on gate structures 124A, 124B and thickness C2 on gate structures 124C-124E) on device features of different heights to "smooth" the topography variations in the device layer. Thus, ILD layer 190 exhibits a "smoother" topography as compared to an ILD layer formed over CESL (located over device features of different heights) having the same thickness. In some embodiments, thickness C1 and thickness C2 are configured to minimize topography variation and achieve the ILD topography ratio given by:

|(H1+C1+D1)–(H2+C2+D2)|/(H1+C1+D1)≤10％，

where D1 is the thickness of ILD layer 190 over the top surface of the gate stack of gate structures 124A, 124B, and D2 is the thickness of ILD layer 190 over the top surface of the gate stack of gate structures 124C-124E. It should be noted that the range of thickness C1 and the range of thickness C2 are specifically configured to facilitate minimizing topographical variations of CESL150 and CESL 170. In other words, if the value of the thickness C1 and/or the value of the thickness C2 is too high or too low, the CESL150 and/or the CESL170 may not achieve the desired effectiveness in reducing (or eliminating) topographical variations between the device region 102 and the device regions 104-108. In some embodiments, the thickness C1 of CESL150 and the thickness C2 of CESL170 are configured to vary the topography by a Δ₃Minimizing reduces the likelihood of cracking of ILD layer 190 at interface 196, thereby preserving the integrity of IC device 100. For example, in conventional fabrication methods, forming an ILD layer over a CESL layer (located over gate structures 124A-124E) having the same thickness may occur in the ILD layer between device region 102 and device region 104 "Cracks "thereby making the ILD layer discontinuous. This may result in, for example, no ILD layer being formed on top corner portions of CESL on gate structure 124B due to topography variations between gate structure 124B and gate structure 124C. The absence of an ILD layer on top corners of the CESL on gate structure 124B may result in an undesirable etch of the CESL and/or gate structure 124B. Furthermore, the undesired etching may result in the later deposited conductive material undesirably connecting to the gate structure 124B, which may ultimately lead to device failure. These problems are eliminated (or significantly reduced) by configuring thickness C1 and thickness C2 to minimize the topography variations of the underlying device layers.

Turning to fig. 2K, a CMP process and/or other planarization process is performed to planarize a top surface 192 of the ILD layer 190 such that the ILD layer 190 has a substantially planar surface. In some embodiments, by minimizing the topography variation Δ₄The surface profile 198 of the top surface 192 is substantially flat and any topographical variations are minimal. Thus, utilizing CESL of different thicknesses on devices of different heights may also improve CMP uniformity and/or reduce ILD loss at the edges of the IC device 100.

Turning to fig. 2L, the ILD layer 190, CESL150, and CESL170 are portions of a multilayer interconnect (MLI) feature 200 disposed over the substrate 110, wherein the process continues to form the various features of the MLI feature 200. The MLI component 200 electrically connects the various devices and/or components of the IC device 100 such that the various devices and/or components can operate as dictated by the design requirements of the IC device 100. The MLI component 200 includes a combination of dielectric layers and conductive layers (e.g., metal layers) configured to form various interconnect structures. The conductive layers are configured to form vertical interconnect features, such as contacts and/or vias, and/or horizontal interconnect features, such as wires. The vertical interconnect features typically connect horizontal interconnect features in different layers (or different planes) of the MLI component 200. During operation of the IC device 100, the interconnect components are configured to route signals between and/or distribute signals (e.g., clock signals, voltage signals, and/or ground signals) to devices and/or components of the IC device 100. It should be noted that although the MLI component 200 is shown with a given number of dielectric and conductive layers, the present invention contemplates MLI components 200 with more or fewer dielectric and/or conductive layers.

An inter-metal dielectric (IMD) layer 210 of MLI features 200 is formed over ILD layer 190. IMD layer 210 includes a dielectric material including, for example, silicon oxide, silicon nitride, silicon oxynitride, an oxide formed from TEOS, PSG, BPSG, a low-k dielectric material, other suitable dielectric material, or combinations thereof. Exemplary low-k dielectric materials include FSG, carbon-doped silicon oxide, Black

(applied materials of Santa Clara, Calif.), xerogels, aerogels, amorphous fluorinated carbons, parylene, BCB, SiLK (Dow chemical company of Mitland, Mich.), polyimides, other low-k dielectric materials, or combinations thereof. In the illustrated embodiment, IMD layer 210 includes a low-k dielectric material. IMD layer 210 includes a multi-layer structure. IMD layer 210 is formed by a deposition process such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable deposition processes, or combinations thereof. In some embodiments, IMD layer 210 is formed by an FCVD process. In some embodiments, the CESL is disposed between the IMD layer 210 and the ILD layer 190.

The contacts 220A-220E and the leads 230A-230C (collectively referred to as metal one (M1) layer of the MLI component 200) are disposed in one or more dielectric layers of the MLI component 200, such as the ILD layer 190 and/or the IMD layer 210, to form an interconnect structure. Contacts 220A-220E electrically and/or physically connect IC device components, such as the gate stacks and/or source/drain components 146 of gate structures 124A-124E, to wires 230A-230C. The contacts 220A-220E and the wires 230A-230C comprise any suitable conductive material, such as Ta, Ti, Al, Cu, Co, W, TiN, TaN, other suitable conductive materials, or combinations thereof. Various conductive materials may be combined to provide the contacts 220A-220E and the wires 230A-230C with various layers, such as barrier layers, adhesive layers, liner layers, bulk layers, other suitable layers, or combinations thereof. In some embodiments, contacts 220A-220E comprise Ti, TiN, W, and/or Co; and the conductive lines 230A to 230C include Cu, Co, and/or Ru. Contacts 220A-220E and conductive lines 230A-230C are formed by patterning ILD layer 190 and/or IMD layer 210. Patterning the ILD layer 190 and/or IMD layer 210 may include a photolithography process and/or an etching process to form openings (trenches), such as contact openings, line openings, and/or via openings, in the respective ILD layer 190 and/or IMD layer 210. In some embodiments, the photolithography process includes forming a photoresist layer over ILD layer 190 and/or IMD layer 210, exposing the photoresist layer to patterned radiation, and developing the exposed photoresist layer to form a patterned photoresist layer, which may be used as a masking element for etching openings in ILD layer 190 and/or IMD layer 210. The etching process includes a dry etching process, a wet etching process, other etching processes, or a combination thereof. Thereafter, the openings are filled with one or more conductive materials. The conductive material may be deposited by PVD, CVD, ALD, electroplating, electroless plating, other suitable deposition process, or combinations thereof. Thereafter, any excess conductive material may be removed by a planarization process (such as a CMP process) to planarize the top surfaces of ILD layer 190, IMD layer 210, contacts 220A-220E, and/or conductive lines 230A-230C.

Fig. 3 is a partial cross-sectional view of a portion or all of an IC device 300 that may be fabricated using the methods described herein, such as the method 10 of fig. 1, in accordance with various aspects of the invention. The IC device 300 is similar in many respects to the IC device 100. Accordingly, for clarity and simplicity, like components in fig. 3 and fig. 2A-2L are identified with like reference numerals. In fig. 3, an IC device 300 is fabricated similar to IC device 100, except that CESL150 is not removed from low profile regions such as device regions 104-108. In such embodiments, the processes associated with fig. 2C-2E are omitted and the processes associated with fig. 2F-2L are continued. Thus, the CESL150 is disposed over the gate structures 124A, 124B in the device region 102, and the CESL150 and the CESL170 are disposed over the gate structures 124C-124E in the device regions 104-108. The thickness of CESL150 and CESL170 is configured to vary the topography by Δ₃Minimizing and thus minimizing topography variations of the ILD layer 190. For the sake of clarity, has been simplifiedFig. 3 is generalized to better understand the inventive concept of the present invention. Additional components may be added to the IC device 300 and some of the components described below may be replaced, modified, or eliminated in other embodiments of the IC device 300.

The present invention provides many different embodiments. Methods for improving ILD layer topography and resulting integrated circuit devices are disclosed. The methods disclosed herein may be implemented in any of a variety of device types. For example, various aspects of the invention may be implemented to form ILD layers suitable for planar Field Effect Transistors (FETs), multi-gate transistors (planar or vertical) (such as fin FET (finfet) devices, all-around Gate (GAA) devices, omega-gate (Ω -gate) or pi-gate (Π -gate) devices, strained semiconductor devices, silicon-on-insulator (SOI) devices, partially depleted SOI devices, fully depleted SOI devices, or other devices. The present invention contemplates other integrated circuit devices that may benefit from the methods described herein for improving ILD layer topography as may be appreciated by one of ordinary skill in the art.

An example method includes forming a first contact etch stop layer over a first region of a wafer, forming a second contact etch stop layer over a second region of the wafer, and forming an inter-layer dielectric (ILD) layer over the first contact etch stop layer and the second contact etch stop layer. There is a first topography variation between the first region and the second region of the wafer, and the first contact etch stop layer has a first thickness. The second contact etch stop layer has a second thickness different from the first thickness to reduce the first topographical variation between the first region and the second region to a second topographical variation. In some embodiments, the second topographical variation is a difference in a height of a topmost surface of the first contact etch stop layer in the first region and a height of a topmost surface of the second contact etch stop layer in the second region, wherein the difference is less than or equal to about 10%. In some embodiments, a first gate structure having a first height is disposed over the wafer in the first region and a second gate structure having a second height is disposed over the wafer in the second region, wherein the first topography variation is caused by the first height being different from the second height. In some embodiments, the second topographical variation is caused by any difference between a first sum of the first height and the first thickness and a second sum of the second height and the second thickness.

In some embodiments, the method further includes forming an inter-metal dielectric layer over the ILD layer. In some embodiments, the first contact etch stop layer is formed by depositing a first contact etch stop layer over the first region and the second region and etching the first contact etch stop layer from over the second region. In some embodiments, the second contact etch stop layer is formed by depositing a second contact etch stop layer over the first region and the second region and etching the second contact etch stop layer from over the first region. In some embodiments, forming the first contact etch stop layer further comprises performing a first photolithography process to form a first mask layer over the first contact etch stop layer over the first region and removing the first mask layer after etching the first contact etch stop layer from over the second region. In some embodiments, forming the second contact etch stop layer further comprises performing a second photolithography process to form a second mask layer over the second contact etch stop layer over the second region and removing the second mask layer after etching the second contact etch stop layer from over the first region. In some embodiments, the first contact etch stop layer and the second contact etch stop layer comprise different materials. In some embodiments, the first contact etch stop layer and the second contact etch stop layer comprise the same material.

Another exemplary method includes forming a first contact etch stop layer over a first gate structure having a first height, forming a second contact etch stop layer over a second gate structure having a second height less than the first height, and forming an inter-layer dielectric (ILD) layer over the first contact etch stop layer and the second contact etch stop layer. The first contact etch stop layer has a first thickness and the second contact etch stop layer has a second thickness greater than the first thickness. In some embodiments, a difference between a first sum of the first height and the first thickness and a second sum of the second height and the second thickness is less than or equal to about 10%. In some embodiments, the first contact etch stop layer is formed before the second contact etch stop layer. In some embodiments, the first contact etch stop layer is formed after the second contact etch stop layer. In some embodiments, forming the ILD layer includes depositing a low-k dielectric material over the first contact etch stop layer and the second contact etch stop layer and performing a planarization process on the low-k dielectric material to planarize a top surface of the low-k dielectric material.

In some embodiments, forming a first contact etch stop layer over the first gate structure and a second contact etch stop layer over the second gate structure includes depositing a first material layer having a first thickness over the first gate structure and the second gate structure, etching the first material layer over the second gate structure, depositing a second material layer having a second thickness over the second gate structure and over the first material layer of the first gate structure, and etching the second material layer over the first material layer. In some embodiments, a first photolithography process is performed to form a first mask layer that covers the first material layer over the first gate structure during etching of the first material layer. In some embodiments, a second photolithography process is performed to form a second mask layer that covers the second material layer over the second gate structure during etching of the second material layer. In some embodiments, the first and second mask layers are formed by forming a patterned photoresist layer. In some embodiments, forming a first contact etch stop layer over the first gate structure and a second contact etch stop layer over the second gate structure includes depositing a first material layer over the first gate structure and the second gate structure, depositing a second material layer over the first material layer, and removing the second material layer from over the first gate structure such that the first material layer forms a first contact etch stop layer having a first thickness over the first gate structure and the first material layer and the second material layer form a second contact etch stop layer over the second gate structure.

An exemplary integrated circuit device includes: a first gate structure having a first height disposed over the substrate in the first region; a second gate structure having a second height disposed over the substrate in the second region; a first contact etch stop layer disposed over the first gate structure; a second contact etch stop layer disposed over the second gate structure; and an interlayer dielectric layer disposed over the first contact etch stop layer and the second contact etch stop layer. The second height is less than the first height. The first contact etch stop layer has a first thickness and the second contact etch stop layer has a second thickness greater than the first thickness. The first contact etch stop layer and the second contact etch stop layer overlap at an interface of the first region and the second region. In some embodiments, the difference between the sum of the first height and the first thickness and the sum of the second height and the second thickness is less than or equal to about 10%.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.