阅读说明：本技术 半导体装置、半导体装置的制造方法 (Semiconductor device and method for manufacturing semiconductor device ) 是由 上马场龙 高桥彻雄 古川彰彦 于 2019-06-21 设计创作，主要内容包括：本发明的目的在于针对晶体管区域和二极管区域形成于同一衬底的半导体装置,提供在二极管的恢复动作时具有良好的耐受性的半导体装置。该半导体装置具备晶体管区域和二极管区域,该晶体管区域和二极管区域在具有第1导电型的漂移层的半导体衬底相邻地形成,该晶体管区域在该漂移层之上具有第2导电型的基极层以及扩散层、第1导电型的发射极层以及栅极电极,在该漂移层的下侧具有第2导电型的集电极层,该二极管区域在该漂移层之上具有第2导电型的阳极层,在该漂移层的下侧具有第1导电型的阴极层,该阴极层越接近该晶体管区域则从该半导体衬底的下表面算起的深度越浅,且第1导电型杂质浓度越小。(The present invention provides a semiconductor device having a transistor region and a diode region formed in the same substrate, which has excellent resistance during a recovery operation of a diode. The semiconductor device includes a transistor region and a diode region, the transistor region and the diode region being formed adjacent to a semiconductor substrate having a drift layer of a 1 st conductivity type, the transistor region having a base layer and a diffusion layer of a 2 nd conductivity type, an emitter layer and a gate electrode of the 1 st conductivity type on the drift layer, a collector layer of the 2 nd conductivity type on a lower side of the drift layer, the diode region having an anode layer of the 2 nd conductivity type on the drift layer, and a cathode layer of the 1 st conductivity type on a lower side of the drift layer, a depth of the cathode layer from a lower surface of the semiconductor substrate being shallower and a concentration of impurities of the 1 st conductivity type being smaller as the cathode layer approaches the transistor region.)

1. A semiconductor device is characterized by comprising:

a transistor region formed in a semiconductor substrate having a drift layer of a 1 st conductivity type; and

a diode region formed adjacent to the transistor region in the semiconductor substrate,

the transistor region has: a base layer of a 2 nd conductivity type formed on the drift layer; a diffusion layer formed on the base layer, the diffusion layer having a higher impurity concentration of the 2 nd conductivity type than the base layer; an emitter layer of a 1 st conductivity type formed on the base layer; a gate electrode in contact with the base layer with an insulating film interposed therebetween; and a collector layer of the 2 nd conductivity type formed on the lower side of the drift layer,

the diode region has: an anode layer of a 2 nd conductivity type formed over the drift layer; and a cathode layer of the 1 st conductivity type formed on a lower side of the drift layer,

the cathode layer has an adjacent region in contact with the transistor region, and the depth from the lower surface of the semiconductor substrate is shallower and the concentration of the impurity of the 1 st conductivity type is smaller the closer the adjacent region is to the transistor region.

2. The semiconductor device according to claim 1,

the cathode layer includes a non-adjacent region that is in contact with the adjacent region and has a constant depth from the lower surface of the semiconductor substrate.

3. The semiconductor device according to claim 1 or 2,

the upper surface of the adjacent region is inclined.

4. The semiconductor device according to any one of claims 1 to 3,

and a p-type layer having the same impurity concentration as the collector layer is provided over the adjacent region.

5. The semiconductor device according to claim 4, comprising:

a buffer layer of a 1 st conductivity type in contact with an upper surface of the collector layer, an upper surface of the p-type layer, and an upper surface of the cathode layer.

6. The semiconductor device according to any one of claims 1 to 5, comprising:

a barrier metal formed over the diffusion layer and the emitter layer; and

an upper electrode in direct contact with the barrier metal and the anode layer.

7. The semiconductor device according to any one of claims 1 to 6,

a carrier accumulation layer of a 1 st conductivity type having a higher impurity concentration of the 1 st conductivity type than the drift layer is provided between the drift layer and the base layer.

8. A method for manufacturing a semiconductor device, comprising:

forming a collector layer of the transistor region on a lower surface side of the semiconductor substrate; and

a cathode layer of a diode region adjacent to the transistor region is formed on a lower surface side of the semiconductor substrate,

in the formation of the cathode layer, ion implantation is performed on the lower surface of the semiconductor substrate using a resist mask that covers at least a part of the lower surface of the transistor region, and in an adjacent region of the lower surface of the diode region that is adjacent to the transistor region, the opening density of the resist mask is reduced as the resist mask approaches the transistor region.

9. The method for manufacturing a semiconductor device according to claim 8,

the resist mask exposes a region of the lower surface of the semiconductor substrate, which is in contact with the adjacent region, i.e., a non-adjacent region.

Technical Field

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background

An inverter device used in a wide range of fields such as home appliances, electric vehicles, and railways often drives an inductive load such as an induction motor. The inverter device includes a plurality of power Semiconductor devices such as switching elements such as igbts (insulated Gate bipolar transistors) or MOSFETs (Metal-Oxide-Semiconductor Field-Effect transistors) and a free-wheeling diode (hereinafter, simply referred to as a "diode"). Since the inverter device is required to have high efficiency and low power, the market is demanding high performance and low cost of the power semiconductor device.

For higher performance and lower cost of power semiconductor devices, trench MOS gate structures, thinner semiconductor substrates, Reverse Conducting IGBTs (RC-IGBTs), and the like have been developed. The RC-IGBT is formed by integrating an IGBT and a diode in the same semiconductor substrate. One of the methods for obtaining good electrical characteristics of the RC-IGBT is to form an optimum diffusion layer in each of the IGBT and the diode.

Patent document 1 discloses an RC-IGBT. In the back surface of the semiconductor device of patent document 1, a plurality of n + type diffusion layers and p type diffusion layers are alternately formed in the diode region. Patent document 1 proposes to suppress the reduction of the recovery characteristic and suppress the reduction of the recovery tolerance by suppressing the electrons supplied from the back surface side in the entire diode operation. These are effective for high frequency operation. However, there is a possibility that, in a low-frequency operation, if the effective area of the p-type diffusion layer is reduced to cope with the reduction, the recovery tolerance is lowered.

Patent document 1: japanese laid-open patent publication No. 2012-129504

In the transistor region of the RC-IGBT, a stacked structure of a semiconductor substrate, a barrier metal, a tungsten plug, and a surface electrode is generally provided. A p + -type diffusion layer, a p-type base layer, and an n + -type emitter layer are provided on the surface side of a semiconductor substrate. On the other hand, a semiconductor substrate and a surface electrode are provided in the diode region of the RC-IGBT. Since the barrier metal and the tungsten plug are not formed in the diode region, even if a p-type anode layer having a low impurity concentration is provided, ohmic contact can be formed between the p-type anode layer and the surface electrode.

However, a p-type base layer or a p + -type diffusion layer is formed in the transistor region adjacent to the diode region. Therefore, these layers have a large influence when the RC-IGBT performs a diode operation. In particular, there is a problem that, during a recovery operation when the diode is switched from on to off, hole carriers are concentrated in a p-type base layer or a p + diffusion layer having a lower resistance than a p-type anode layer, and the off current increases.

Disclosure of Invention

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device having a transistor region and a diode region formed in the same substrate, which has good endurance in a recovery operation of a diode, and a method for manufacturing the semiconductor device.

The semiconductor device according to the present invention is characterized by comprising: a transistor region formed in a semiconductor substrate having a drift layer of a 1 st conductivity type; and a diode region formed in the semiconductor substrate and formed adjacent to the transistor region, the transistor region having: a base layer of a 2 nd conductivity type formed on the drift layer; a diffusion layer formed on the base layer, the diffusion layer having a higher impurity concentration of the 2 nd conductivity type than the base layer; an emitter layer of a 1 st conductivity type formed on the base layer; a gate electrode in contact with the base layer with an insulating film interposed therebetween; and a collector layer of a 2 nd conductivity type formed on a lower side of the drift layer, the diode region having: an anode layer of a 2 nd conductivity type formed over the drift layer; and a cathode layer of the 1 st conductivity type formed under the drift layer, the cathode layer having an adjacent region in contact with the transistor region, the depth from the lower surface of the semiconductor substrate being shallower and the 1 st conductivity type impurity concentration being smaller as the adjacent region is closer to the transistor region.

The method for manufacturing a semiconductor device according to the present invention includes: forming a collector layer of the transistor region on a lower surface side of the semiconductor substrate; and a cathode layer that forms a diode region adjacent to the transistor region on a lower surface side of the semiconductor substrate, wherein in the formation of the cathode layer, ion implantation is performed on the lower surface of the semiconductor substrate using a resist mask that covers at least a part of the lower surface of the transistor region, and an adjacent region of the lower surface of the diode region adjacent to the transistor region has a smaller opening density as it approaches the transistor region.

Other features of the invention will be apparent below.

ADVANTAGEOUS EFFECTS OF INVENTION

According to the present invention, the depth and the impurity concentration of the cathode layer are made smaller as the depth and the impurity concentration are closer to the transistor region, and therefore, it is possible to provide a good resistance at the time of a recovery operation of the diode.

Drawings

Fig. 1 is a plan view of a semiconductor device according to embodiment 1.

Fig. 2 is a bottom view of the semiconductor device according to embodiment 1.

Fig. 3 is a cross-sectional view taken along line a-a' of fig. 1.

Fig. 4 is a sectional view taken along line B-B' of fig. 1.

Fig. 5 is a diagram illustrating a turn-on operation of the diode.

Fig. 6 is a diagram illustrating an off operation of the diode.

Fig. 7 is a top view of a resist mask.

Fig. 8 is a sectional view of a semiconductor device according to embodiment 2.

Fig. 9 is a sectional view of a semiconductor device according to embodiment 2.

Description of the reference numerals

1 transistor region, 2 diode region, 3 drift layer, 4 base layer, 5 diffusion layer, 6 emitter layer, 14 buffer layer, 15 collector layer, 15A p type layer, 20 cathode layer, 20A adjacent region, 20B non-adjacent region, 50 resist mask, 50A, 50B opening, 100, 101 semiconductor device.

Detailed Description

The following describes embodiments with reference to the drawings. Since the drawings are schematically illustrated, the correlation between the size and the position of the images illustrated in the different drawings is not necessarily accurate, and may be appropriately changed. In the following description, the same or corresponding components are denoted by the same reference numerals and are shown, and their names and functions are also the same. Therefore, detailed description thereof will sometimes be omitted.

In the following description, terms indicating specific positions and directions such as "upper", "lower", "side", "bottom", "front", and "back" are used in some cases, but these terms are used for convenience and ease of understanding of the embodiments, and do not limit the directions in actual implementation. The conductivity type of the semiconductor will be described with reference to n-type 1 conductivity type and p-type 2 conductivity type. However, the conductivity types may be reversed, and the 1 st conductivity type may be p-type and the 2 nd conductivity type may be n-type. N + type indicates that the impurity concentration is higher than that of n type, and n-type indicates that the impurity concentration is lower than that of n type. Similarly, p + type indicates a higher impurity concentration than p type, and p-type indicates a lower impurity concentration than p type.