阅读说明：本技术 可编程可抹除的非挥发性存储器 (Programmable erasable non-volatile memory ) 是由 许家荣 于 2019-05-21 设计创作，主要内容包括：本发明公开一种可编程可抹除的非挥发性存储器,包括：第一选择晶体管、第一浮动栅晶体管、第二选择晶体管与第二浮动栅晶体管。第一选择晶体管的选择栅极与第一源/漏端分别接收选择栅极电压与第一源极线电压。第一浮动栅晶体管的第一源/漏端与第二源/漏端分别连接至第一选择晶体管的第二源/漏端以及接收第一位线电压。第二选择晶体管也包括选择栅极。第二选择晶体管的第一源/漏端接收第一源极线电压。第二浮动栅晶体管的第一源/漏端与第二源/漏端分别连接至第二选择晶体管的第二源/漏端以及接收第二位线电压。(The invention discloses a programmable erasable nonvolatile memory, comprising: a first selection transistor, a first floating gate transistor, a second selection transistor and a second floating gate transistor. The select gate and the first source/drain of the first select transistor receive a select gate voltage and a first source line voltage, respectively. The first floating gate transistor has a first source/drain terminal and a second source/drain terminal connected to the second source/drain terminal of the first select transistor, respectively, and receiving the first bit line voltage. The second select transistor also includes a select gate. The first source/drain terminal of the second select transistor receives the first source line voltage. The first source/drain terminal and the second source/drain terminal of the second floating gate transistor are connected to the second source/drain terminal of the second select transistor and receive a second bit line voltage, respectively.)

1. A programmable erasable non-volatile memory, comprising:

a first select transistor comprising: the selection grid electrode receives a selection grid electrode voltage, and the first source/drain terminal receives a first source electrode line voltage and a second source/drain terminal;

a first floating gate transistor comprising: a floating gate, a first source/drain terminal connected to the second source/drain terminal of the first selection transistor, and a second source/drain terminal receiving a first bit line voltage;

a second select transistor comprising: the first source/drain terminal of the selection grid receives a second source line voltage and a second source/drain terminal;

a second floating gate transistor comprising: the floating gate, a first source/drain terminal connected to the second source/drain terminal of the second select transistor, and a second source/drain terminal receiving a second bit line voltage;

wherein the first select transistor and the first floating gate transistor are formed in a first well region; the second selection transistor and the second floating gate transistor are made in the second well region; and the first well region and the second well region are different types of well regions.

2. The programmable erasable non-volatile memory of claim 1, wherein said first select transistor and said first floating gate transistor are n-type transistors, said first well region is a P-type well region receiving a P-type well region voltage; and the second selection transistor and the second floating gate transistor are p-type transistors, and the second well region is an N-type well region receiving an N-type well region voltage.

3. The programmable erasable non-volatile memory of claim 1, wherein said first select transistor and said first floating gate transistor are p-type transistors, said first well region is an N-well region receiving an N-well region voltage; and the second selection transistor and the second floating gate transistor are n-type transistors, and the second well region is a P-type well region receiving a P-type well region voltage.

4. The programmable erasable non-volatile memory of claim 1, wherein said first floating gate transistor has a first channel length; the second floating gate transistor having a second channel length; and the first channel length is less than the second channel length.

5. The programmable erasable non-volatile memory of claim 1, wherein said first floating gate transistor has a first channel width; the second floating gate transistor has a second channel width; and the first channel width is less than the second channel width.

6. The programmable erasable non-volatile memory of claim 1, wherein during a programming operation, a plurality of electrons are injected from a channel region of said first floating gate transistor into said floating gate of said first floating gate transistor.

7. The programmable, erasable non-volatile memory of claim 1, wherein during an erase operation, a plurality of electrons are ejected from said floating gate of said first floating gate transistor to said first well region.

8. The programmable erasable non-volatile memory of claim 1, wherein during a read operation, said second floating gate transistor generates a read current.

9. The programmable, erasable non-volatile memory of claim 8, wherein said second floating gate transistor generates a first read current when said floating gate of said second floating gate transistor stores a plurality of electrons; the second floating gate transistor generates a second read current when the floating gate of the second floating gate transistor does not store the electrons, and the first read current is different from the second read current.

10. A programmable erasable non-volatile memory, comprising:

a semiconductor layer;

a first well region formed in the semiconductor layer;

a first doped region, a second doped region and a third doped region are formed on the surface of the first well region, wherein the first doped region receives a first source line voltage, and the third doped region receives a first bit line voltage;

a second well region formed in the semiconductor layer;

a fourth doped region, a fifth doped region and a sixth doped region are arranged on the surface of the second well region, wherein the fourth doped region receives a second source line voltage, and the sixth doped region receives a second bit line voltage;

a select gate formed over a surface between the first doped region and the second doped region and over a surface between the fourth doped region and the fifth doped region, the select gate receiving a select gate voltage;

a floating gate formed over a surface between the second doped region and the third doped region and over a surface between the fifth doped region and the sixth doped region; and

and an isolation structure formed in the semiconductor layer and located between the first well region and the second well region.

11. The programmable erasable non-volatile memory of claim 10, wherein said first well region is a P-well region receiving a P-well region voltage, said second well region is an N-well region receiving an N-well region voltage, and said first doped region, said second doped region and said third doped region are N-type doped regions; and the fourth doped region, the fifth doped region and the sixth doped region are p-type doped regions.

12. The programmable erasable non-volatile memory of claim 10, wherein said first well region is an N-well region receiving an N-well region voltage, said second well region is a P-well region receiving a P-well region voltage, and said first doped region, said second doped region and said third doped region are P-type doped regions; and the fourth doped region, the fifth doped region and the sixth doped region are n-type doped regions.

13. The programmable, erasable non-volatile memory of claim 10, wherein the first well region, the second doped region, the third doped region and the floating gate form a first floating gate transistor, and the second well region, the fifth doped region, the sixth doped region and the second floating gate form a second floating gate transistor.

14. The programmable erasable non-volatile memory of claim 13, wherein said first floating gate transistor has a first channel length; the second floating gate transistor having a second channel length; and the first channel length is less than the second channel length.

15. The programmable erasable non-volatile memory of claim 13, wherein said first floating gate transistor has a first channel width; the second floating gate transistor has a second channel width; and the first channel width is less than the second channel width.

16. The programmable erasable non-volatile memory of claim 10, wherein the first well region comprises a plurality of sub first type well regions, and the sub first type well regions are sequentially formed in the semiconductor layer from a shallow to a deep surface of the semiconductor layer; the first doped region, the second doped region and the third doped region are formed on the surface of the first sub first-type well region in the first well region; the second well region comprises a plurality of sub second type well regions, and the sub second type well regions are formed in the semiconductor layer from the surface of the semiconductor layer to the depth in sequence; and the fourth doped region, the fifth doped region and the sixth doped region are formed on the surface of the first sub-second-type well region in the second well region.

17. The programmable, erasable non-volatile memory of claim 16, wherein a last sub first-type well region of said first well regions and a last sub second-type well region of said second well regions are in contact with each other.

18. The programmable erasable non-volatile memory of claim 17, wherein the last sub-first type well region in the first well region has a first concentration, a penultimate sub-first type well region in the first well region has a second concentration, and the second concentration is greater than the first concentration.

19. The programmable, erasable non-volatile memory of claim 18, wherein said last sub-second type well region in said second well region has a third concentration, a penultimate sub-second type well region in said second well region has a fourth concentration, and said fourth concentration is greater than said third concentration.

20. The programmable erasable nonvolatile memory of claim 10, wherein the isolation structure is a shallow trench isolation structure.

21. The programmable, erasable non-volatile memory of claim 10, wherein the semiconductor layer is a p-type substrate, an n-type buried layer, or a deep n-type well region.

Technical Field

The present invention relates to a nonvolatile memory (nonvolatile memory), and more particularly, to a programmable erasable nonvolatile memory.

Background

Referring to fig. 1A to 1D, a conventional programmable erasable nonvolatile memory is disclosed in US 8941167. FIG. 1A is a top view of a non-volatile memory; FIG. 1B is a cross-sectional view of the nonvolatile memory in a first direction (a1a2 direction); FIG. 1C is a cross-sectional view of the nonvolatile memory in a second direction (b1b2 direction); FIG. 1D is an equivalent circuit diagram of the nonvolatile memory.

As shown in fig. 1A and 1B, the conventional nonvolatile memory includes two serially connected p-type transistors fabricated in an N-well (NW). The N-well NW includes three p-type doped regions 31, 32, 33, and two gates 34, 36 made of polysilicon (polysilicon) are disposed above the surface between the three p-type doped regions 31, 32, 33.

The first p-type transistor acts as a select transistor with its select gate 34 connected to a select gate voltage (V)_SG) The p-doped region 31 is connected to a source line voltage (V)_SL). Furthermore, the p-type doped region 32 can be regarded as a p-type doped region of the first p-type transistor and a p-type doped region of the second p-type transistor connected to each other. The second p-type transistor acts as a floating gate transistor and includes a floating gate 36 with a p-doped region 33 connected to the bit line voltage (V)_BL). The N-well (NW) is connected to an N-well voltage (V)_NW)。

As shown in fig. 1A and fig. 1C, the conventional nonvolatile memory further includes an n-type transistor, or a device formed by combining a floating gate 36 and an erase gate region 35. The n-type transistor is fabricated in a P-type well (PW). An n-doped region 38 is included in the P-well region (PW). In other words, the erase gate region 35 includes a P-well (PW) and an n-doped region 38.

As shown in FIG. 1A, the floating gate 36 extends outward and is adjacent to the erase gate region 35. Thus, the floating gate 36 may be considered to be the gate of an n-type transistor, while the n-doped region 38 may be considered to be an interconnection of an n-type source doped region and an n-type drain doped region. Furthermore, the n-type doped region 38 is connected to an erase line voltage (V)_EL). The P-well (PW) is connected to a P-well voltage (V)_PW). Furthermore, as shown in fig. 1C, the erase gate region 35 and the N-well (NW) may be separated by an isolation structure 39, wherein the isolation structure 39 is, for example, a Shallow Trench Isolation (STI) structure.

As shown in the equivalent circuit of FIG. 1D, the nonvolatile memory includes a select transistor, a floating gate transistor and an n-type transistor. Wherein the selection transistor and the floating gate transistor are both p-type transistors and are formed in an N-type well region (NW), and the N-type well region (NW) receives a voltage (V) of the N-type well region_NW). In addition, the n-type transistor is formed in a P-well (PW) receiving the P-well voltage (V)_PW)。

The select gate terminal of the select transistor receives a select gate voltage (V)_SG) The first source/drain terminal of the selection transistor receives a source line voltage (V)_SL). The first source/drain terminal of the floating gate transistor is connected to the second source/drain terminal of the select transistor, which receives the bit line voltage (V)_BL). The gate terminal of the n-type transistor is connected with the floating gate of the floating gate transistor, the first source/drain terminal of the n-type transistor and the second source/drain terminal of the n-type transistor are connected with each other and receive the erase line voltage (V)_EL)。

Disclosure of Invention

The invention aims to provide a programmable erasable nonvolatile memory with a novel structure.

The invention relates to a programmable erasable nonvolatile memory, which comprises: a first select transistor including a select gate receiving a select gate voltage, a first source/drain receiving a first source line voltage and a second source/drain; a first floating gate transistor including a floating gate, a first source/drain terminal connected to the second source/drain terminal of the first select transistor, and a second source/drain terminal receiving a first bit line voltage; a second selection transistor including the selection gate, a first source/drain terminal receiving a second source line voltage and a second source/drain terminal; a second floating gate transistor including the floating gate, a first source/drain terminal connected to the second source/drain terminal of the second select transistor, and a second source/drain terminal receiving a second bit line voltage. Wherein the first select transistor and the first floating gate transistor are formed in a first well region; the second selection transistor and the second floating gate transistor are made in a second well region; and the first well region and the second well region are different types of well regions.

The invention relates to a programmable erasable nonvolatile memory, which comprises: a semiconductor layer; a first well region formed in the semiconductor layer; a first doped region, a second doped region and a third doped region formed on the surface of the first well region, wherein the first doped region receives a first source line voltage, and the third doped region receives a first bit line voltage; a second well region formed in the semiconductor layer; a fourth doped region, a fifth doped region and a sixth doped region on the surface of the second well region, wherein the fourth doped region receives a second source line voltage, and the sixth doped region receives a second bit line voltage; a select gate formed over a surface between the first doped region and the second doped region and over a surface between the fourth doped region and the fifth doped region, the select gate receiving a select gate voltage; a floating gate formed over the surface between the second doped region and the third doped region and over the surface between the fifth doped region and the sixth doped region; and an isolation structure formed in the semiconductor layer and located between the first well region and the second well region.

In order that the manner in which the above recited and other aspects of the present invention are obtained can be understood in detail, a more particular description of the invention, briefly summarized below, may be had by reference to the appended drawings, in which:

drawings

FIGS. 1A-1D are schematic diagrams of a conventional programmable erasable nonvolatile memory;

FIGS. 2A-2C are schematic diagrams of a first embodiment of a programmable and erasable nonvolatile memory according to the present invention;

FIGS. 3A to 3D are schematic diagrams illustrating bias voltages of the non-volatile memory according to the first embodiment;

FIGS. 4A and 4B are schematic diagrams of a programmable erasable nonvolatile memory according to a second embodiment of the present invention.

Description of the symbols

20. 40: non-volatile memory

21. 22, 23, 41, 42, 43: p-type doped region

25. 26, 27, 45, 46, 47: n-type doped region

29. 49: isolation structure

31. 32, 33: p-type doped region

34. 36: grid electrode

35: erase gate region

38: n-type doped region

39: isolation structure

Detailed Description

Referring to fig. 2A to 2C, a first embodiment of the present invention is shown. FIG. 2A is a top view of a non-volatile memory; FIG. 2B is a cross-sectional view of the nonvolatile memory taken along the dashed line a-B; FIG. 2C is an equivalent circuit diagram of the non-volatile memory.

As shown in fig. 2A and 2B, the nonvolatile memory 20 includes two serially connected P-type transistors fabricated in an N-well (NW) and two serially connected N-type transistors fabricated in a P-well (PW). The N-well (NW) and the P-well (PW) are separated by an isolation structure 29, and the isolation structure 29 is, for example, a Shallow Trench Isolation (STI) structure. In addition, the isolation structure 29, the N-well (NW), and the P-well (PW) are formed in the P-substrate (P _ sub). Of course, the isolation structure 29, the N-well (NW) and the P-well (PW) may be formed in other semiconductor layers, such as an N-substrate (N-substrate), an N-type buried layer (NBL), and a deep N-well (deep N well, DNW).

Three p-doped regions 21, 22, 23 are included in the N-well region (NW). Wherein a gate SG made of polysilicon (polysilicon) is formed over the surface between the p-type doped regions 21, 22; on the surface between the p-type doped regions 22, 23A gate FG of polysilicon is formed. Wherein the first p-type transistor is used as a first selection transistor with its selection gate SG connected to the selection gate voltage (V)_SG) The p-doped region 21 is connected to a first source line voltage (V)_SL1). Furthermore, the p-type doped region 22 can be regarded as a p-type doped region of the first p-type transistor and a p-type doped region of the second p-type transistor connected to each other. The second p-type transistor, which acts as the first floating gate transistor, includes a floating gate FG above it, with a second doped region 23 of p-type connected to a first bit line voltage (V)_BL1). The N-well (NW) is connected to an N-well voltage (V)_NW)。

Similarly, the P-well (PW) includes three n-doped regions 25, 26, and 27, and two gates SG and FG made of polysilicon (polysilicon) are disposed above the surface between the three n-doped regions 25, 26, and 27. Wherein the first n-type transistor is used as the second selection transistor, and its selection gate SG is connected to the selection gate voltage (V)_SG) The n-doped region 25 is connected to a second source line voltage (V)_SL2). Furthermore, the n-type doped region 26 can be regarded as an n-type doped region of the first n-type transistor and an n-type doped region of the second n-type transistor connected to each other. The second n-type transistor is used as a second floating gate transistor and includes a floating gate FG above it with a second n-type doped region 27 connected to a second bit line voltage (V)_BL2). The P-well (PW) is connected to a P-well voltage (V)_PW)。

According to the first embodiment of the present invention, the select gate SG of the first select transistor and the gate SG of the second select transistor are composed of the same polysilicon, that is, the select gate SG of the first select transistor and the select gate SG of the second select transistor are connected to each other. Furthermore, the floating gate FG of the first floating gate transistor and the floating gate FG of the second floating gate transistor are composed of the same polysilicon, i.e., the floating gate FG of the first floating gate transistor and the floating gate FG of the second floating gate transistor are connected to each other. Further, a channel length (channel length) L1 of the first floating gate transistor is smaller than a channel length L2 of the second floating gate transistor. The channel width w1 of the first floating gate transistor is smaller than the channel width w2 of the second floating gate transistor.

As shown in the equivalent circuit of fig. 2C, the nonvolatile memory 20 includes a first selection transistor, a second selection transistor, a first floating gate transistor and a second floating gate transistor. That is, a memory cell (memory cell) of the nonvolatile memory 20 is composed of four transistors, and the memory cell is connected to two bit lines (bit lines), two source lines (source lines), and two select lines (select lines) connected to each other. In other words, the first selection transistor and the second selection transistor have a common selection gate SG, i.e., two selection lines are considered to be connected to each other.

Furthermore, the first selection transistor and the first floating gate transistor are both p-type transistors and are formed in an N-well (NW) region, and the N-well region (NW) receives a voltage (V) from the N-well region_NW). In addition, the second selection transistor and the second floating gate transistor are both n-type transistors and are made in a P-type well region (PW), and the P-type well region (PW) receives the P-type well region voltage (V)_PW)。

The select gate terminal SG of the first select transistor receives a select gate voltage (V)_SG) The first source/drain terminal of the first selection transistor receives a first source line voltage (V)_SL1). The first floating gate transistor has a first source/drain terminal connected to the second source/drain terminal of the first select transistor, and the second source/drain terminal of the first floating gate transistor receives a first bit line voltage (V)_BL1)。

The select gate terminal SG of the second select transistor is connected to the select gate terminal SG of the first select transistor, and the first source/drain terminal of the second select transistor receives the second source line voltage (V)_SL2). The first source/drain terminal of the second floating gate transistor is connected to the second source/drain terminal of the second select transistor, and the second source/drain terminal of the second floating gate transistor receives a second bit line voltage (V)_BL2)。

The operation of the non-volatile memory 20 is described in detail below.

In the programming operation, the first select transistor and the first floating gate transistor are operated, so that hot carriers (hot carriers), such as electrons, are injected (inject) into the floating gate FG from a channel region (channel region) of the first floating gate transistor.

When the nonvolatile memory 20 is erased, the first select transistor and the first floating gate transistor are operated, so that electrons exit (project) the floating gate FG from a channel region (channel region) of the first floating gate transistor.

When the nonvolatile memory 20 performs a read operation, the second selection transistor and the second floating gate transistor are operated such that the second floating gate transistor generates a read current according to the number of electrons on the floating gate FG, and the storage state of the nonvolatile memory 20 is determined according to the magnitude of the read current.

Referring to fig. 3A to 3D, bias diagrams of the non-volatile memory according to the first embodiment are shown.

As shown in FIG. 3A and FIG. 3B, the programming operation can be divided into two time intervals. For example, the programming operation requires 50 μ s, the first time interval is 20 μ s in the initial period, and the second time interval is 30 μ s in the later period.

In the initial stage of programming operation, the gate voltage (V) is selected_SG) A second source line voltage (V)_SL2) Second bit line voltage (V)_BL2) And P-type well region voltage (V)_PW) Are both 0V, so that the second select transistor is turned off. Further, the gate voltage (V) is selected_SG) Is 0V, the first source line voltage (V)_SL1) Is 5V, the first bit line voltage (V)_BL1) is-2V, N well region voltage (V)_NW) Is 5V so that the first select transistor is turned on and a programming current Ipgm is generated through the first floating gate transistor. Thus, electrons are injected into the floating gate FG from the channel area of the first floating gate transistor.

At the end of the programming action, the second source line voltage (V)_SL2) Second bit line voltage (V)_BL2) Is raised to 5V so that the floating gate FG of the second floating gate transistor is coupled (coupled) out to a voltage of about 5V. Therefore, more electrons will be injected into the floating gate FG of the first floating gate transistor, which may improve the programming efficiency of the non-volatile memory device 20.

As shown in FIG. 3A andFIG. 3C shows the select gate voltage (V) during an erase operation_SG) 0V, second source line voltage (V)_SL2) Second bit line voltage (V)_BL2) And P-type well region voltage (V)_PW) Are all-7.5V. Furthermore, the first source line voltage (V)_SL1) A first bit line voltage (V)_BL1) And N-type well region voltage (V)_NW) Are all 7.5V.

Since the floating gate FG of the second floating gate transistor may be coupled (coupled) out to a voltage of about-7.5V. At the same time, due to the first bit line voltage (V)_BL1) And N-type well region voltage (V)_NW) Are all 7.5V. Thus, the floating gate FG of the first floating gate transistor is coupled to the N-well voltage (V)_NW) With a voltage difference of 15V, this causes electrons to be ejected from the floating gate FG of the first floating gate transistor into the N-well region (NW).

As shown in FIGS. 3A and 3D, during a read operation, the gate voltage (V) is selected_SG) A first source line voltage (V)_SL1) A first bit line voltage (V)_BL1) And N-type well region voltage (V)_NW) Is 2.5V, so that the first select transistor is turned off. Further, the gate voltage (V) is selected_SG) Is 2.5V, the second source line voltage (V)_SL2) Is 0V, the second bit line voltage (V)_BL2) Is 2.5V, P well region voltage (V)_PW) Is 0V so that the second select transistor is turned on and the second floating gate transistor generates the read current Iread.

Basically, the magnitude of the read current Iread is determined by whether electrons are stored in the floating gate FG of the second floating gate transistor. For example, the floating gate FG of the second floating gate transistor stores electrons, which causes the second floating gate transistor to be in an off state, resulting in a read current Iread of very little about 0. On the other hand, if the floating gate FG of the second floating gate transistor does not store electrons, the second floating gate transistor is turned on, and a large read current Iread is generated. Therefore, in the read operation, the storage state of the nonvolatile memory 20 can be determined according to the magnitude of the read current Iread.

According to an embodiment of the present invention, the channel length L1 of the first floating gate transistor is smaller than the channel length L2 of the second floating gate transistor. In addition, the channel width w1 of the first floating gate transistor is smaller than the channel width w2 of the second floating gate transistor. Thus, the first floating gate transistor has better programming efficiency and the second floating gate transistor has better reading efficiency.

Basically, the N-well (NW) and the P-well (PW) of the non-volatile memory 20 have high doping concentrations (doping concentrations). When the non-volatile memory 20 is erased, the voltage (V) of the N-well region_NW) 7.5V, P-well region voltage (V)_PW) It was-7.5V. That is, there is a voltage difference (voltage difference) of 15V between the N-well (NW) and the P-well (PW). If the N-well (NW) and the P-well (PW) contact each other in the nonvolatile memory 20, the junction breakdown voltage (junction breakdown voltage) is not sufficient to support, so that junction breakdown may easily occur.

As shown in fig. 2B, in order to prevent junction breakdown (junction breakdown) of the nonvolatile memory 20, a wider isolation structure 29 is required to be designed in the P-type substrate (P _ sub) to separate the N-type well region (NW) and the P-type well region (PW), for example, the isolation structure 29 with a thickness of 1 μm or more. Thus, after the N-well (NW) and the P-well (PW) are formed, the N-well (NW) and the P-well (PW) are separated by the P-substrate (P _ sub) and do not contact each other.

Further, since the concentration of the P-type substrate (P _ sub) is low, the junction breakdown voltage between the N-type well region (NW) and the P-type substrate (P _ sub) is higher than the junction breakdown voltage when the highly doped N-type well region (NW) and the highly doped P-type well region (PW) are in contact with each other. Therefore, junction breakdown (junction breakdown) does not occur when the nonvolatile memory 20 is erased. However, designing the isolation structure 29 wider in the p-type substrate (p _ sub) results in a larger area of the memory cell of the nonvolatile memory 20.

Referring to fig. 4A and 4B, a second embodiment of the present invention is shown. FIG. 4A is a top view of a non-volatile memory; and FIG. 4B is a cross-sectional view of the nonvolatile memory along the dashed line c-d. Moreover, the equivalent circuits and the biases of the nonvolatile memories of the first embodiment and the second embodiment are completely the same, and are not described herein again.

The difference between the first embodiment and the second embodiment is the structure of the well region. The N-type well region comprises a plurality of sub N-type well regions, and the P-type well region comprises a plurality of sub P-type well regions. The following description is given by taking an example in which the N-well includes three sub-N-well regions NW 1-NW 3 and the PN-well includes three sub-P-well regions PW 1-PW 3. Of course, in other embodiments, the N-well region may include two sub-N-well regions or more than three sub-N-well regions. Similarly, the P-well region may include two sub-P-well regions or more than three sub-P-well regions.

As shown in fig. 4A and 4B, the non-volatile memory 40 includes two serially connected P-type transistors fabricated in a first sub-N-well (NW1) and two serially connected N-type transistors fabricated in a first sub-P-well (PW 1). The first sub-N well (NW1) and the first sub-P well (PW1) are separated by an isolation structure 49. Furthermore, the second sub-N-well (NW2) and the second sub-P-well (PW2) are also separated by the isolation structure 49, and the third sub-N-well (NW3) is in contact with the third sub-P-well (PW 3). The isolation structure 40 is, for example, a Shallow Trench Isolation (STI) structure. In addition, the isolation structure 49, the N-well and the P-well are formed in the P-substrate (P _ sub). Of course, the isolation structure 49, the N-well and the P-well may be formed in other semiconductor layers, such as an N-substrate (N-substrate), an N-type buried layer (NBL), and a deep N-well (DNW).

Three p-type doped regions 41, 42, 43 are included in the first sub-N-type well region (NW 1). Wherein a gate SG composed of polysilicon (polysilicon) is formed over the surface between the p-type doped regions 41, 42; a gate FG of polysilicon is formed over the surface between the p-doped regions 42, 43. Wherein the first p-type transistor is used as a first selection transistor with its selection gate SG connected to the selection gate voltage (V)_SG) The p-doped region 41 is connected to a first source line voltage (V)_SL1). Furthermore, the p-type doped region 42 can be considered as a p-type doped region of the first p-type transistor and a p-type doped region of the second p-type transistorThe regions are interconnected. The second p-type transistor, which serves as the first floating gate transistor, includes a floating gate FG above it with a p-type second doped region 43 connected to a first bit line voltage (V)_BL1). The N-well is connected to an N-well voltage (V)_NW)。

Similarly, the first sub P well region (PW1) includes three n-type doped regions 45, 46, 47, and two gates SG, FG made of polysilicon (polysilicon) are disposed above the surface between the three n-type doped regions 45, 46, 47. Wherein the first n-type transistor is used as the second selection transistor, and its selection gate SG is connected to the selection gate voltage (V)_SG) The n-doped region 45 is connected to a second source line voltage (V)_SL2). Furthermore, the n-type doped region 46 can be considered as an n-type doped region of the first n-type transistor and an n-type doped region of the second n-type transistor connected to each other. The second n-type transistor is used as a second floating gate transistor and includes a floating gate FG above it with a second n-type doped region 47 connected to a second bit line voltage (V)_BL2). The P-well is connected to a P-well voltage (V)_PW)。

According to a second embodiment of the present invention, during the formation of the well region, a plurality of ion implantations are performed according to different depths to form a plurality of sub N-well regions and a plurality of sub P-well regions.

As shown in fig. 4B, the N-well region sequentially includes a first sub-N-well region (NW1), a second sub-N-well region (NW2), and a third sub-N-well region (NW3) from the shallow to the deep surface of the p-type substrate (p _ sub); the P-well region sequentially comprises a first sub-P-well (PW1), a second sub-P-well (PW2), and a third sub-P-well (PW 3). Wherein the concentration of the second sub N-well region (NW2) is greater than the concentration of the third sub N-well region (NW3), and the concentration of the second sub P-well region (PW2) is greater than the concentration of the third sub P-well region (PW 3).

Basically, since the third sub N-well region (NW3) and the third sub P-well region (PW3) have low concentrations, the junction breakdown voltage of the third sub N-well region (NW3) and the third sub P-well region (PW3) is high. When the non-volatile memory 40 is erased, junction breakdown will not occur.

Since the nonvolatile memory 40 does not have junction breakdown, the isolation structure 49 with a narrow width, for example, the isolation structure 49 with a width of 0.5 μm or less, can be designed in the p-type substrate (p _ sub). Thus, after the N-well and P-well are formed, the third sub-N-well (NW3) and the third sub-P-well (PW3) are in contact with each other, and it is confirmed that the nonvolatile memory 40 does not have junction breakdown.

In addition, the concentration of the second sub N-well region (NW2) is greater than that of the third sub N-well region (NW3), and the concentration of the second sub P-well region (PW2) is greater than that of the third sub P-well region (PW 3). Therefore, during the erase operation, it is ensured that no punch-through (punch through effect) occurs between the third sub-N-well (NW3) and the three N-type doped regions 45, 46, 47.

As can be seen from the above description, in the nonvolatile memory 40 of the present invention, the area of the memory cell can be effectively reduced by designing the isolation structure 49 to be narrower.

In addition, since the concentration of the first sub N well (NW1) can determine the threshold voltage (threshold voltage) of the first selection transistor, the concentration of the first sub P well (PW1) can determine the threshold voltage of the second selection transistor. Therefore, the concentration of the first sub N well region (NW1) and the concentration of the first sub P well region (PW1) are not limited in the present invention. The concentration of the first sub N-well region (NW1) and the concentration of the first sub P-well region (PW1) can be designed by those skilled in the art according to the actual requirement.

Furthermore, in the above embodiments, the p-type select transistor and the p-type floating gate transistor are used to perform the programming operation and the erasing operation; and the reading operation is performed by using the n-type selection transistor and the n-type floating gate transistor. Of course, the invention is not limited thereto, and those skilled in the art can also use the n-type select transistor and the n-type floating gate transistor designed in the P-well region to perform the programming operation and the erasing operation; and the reading operation is performed by using the p-type selection transistor and the p-type floating gate transistor designed in the N-type well region.

In summary, although the present invention is disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the definition of the appended claims.